JPS60180131A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60180131A JPS60180131A JP59036836A JP3683684A JPS60180131A JP S60180131 A JPS60180131 A JP S60180131A JP 59036836 A JP59036836 A JP 59036836A JP 3683684 A JP3683684 A JP 3683684A JP S60180131 A JPS60180131 A JP S60180131A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- bonding pad
- surface protection
- protection layer
- protruded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置に係り、特にその耐湿性を向上した
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device, and particularly to a semiconductor device with improved moisture resistance.
（ロ）従来技術
第１図は従来の半導体装置のうち、特に集積回路装置の
ボンディングバンド近辺を模型的に図示した平面図であ
り、第２図は第１図のＡ−Ａ断面図である。(b) Prior Art FIG. 1 is a plan view schematically showing the vicinity of a bonding band of a conventional semiconductor device, especially an integrated circuit device, and FIG. 2 is a cross-sectional view taken along line A-A in FIG. .
図において、半導体装置は例えばＰ型の半導体基板１に
形成されており、２は分離拡散層である。In the figure, a semiconductor device is formed on, for example, a P-type semiconductor substrate 1, and 2 is a separation diffusion layer.
３はアルミニウムからなる配線層である。3 is a wiring layer made of aluminum.
４は開口部５を有する表面保護層、６はこの開口部５に
露呈した前記配線層３からなるポンディングパッドであ
り、ボンディングバンド６の近国縁より内側を除く他の
領域を表面保護層４でもって被覆している。4 is a surface protective layer having an opening 5; 6 is a bonding pad made of the wiring layer 3 exposed in this opening 5; other areas except the inner side of the near edge of the bonding band 6 are covered with the surface protective layer; It is coated with 4.
７はボンディングワイヤであって、外部端子とボンディ
ングバンド６とを電気的に接続している。A bonding wire 7 electrically connects the external terminal and the bonding band 6.
このように構成された半導体装置の大部分は、表面保護
層４によって耐湿性が確保され、またボンディングワイ
ヤ７がボンディングされている部分は、半導体基板１、
ボンディングバンド６、ボンディングボール７ａが例え
ばＳｔ−＾ｌ−＾Ｕのように合金化しているため外部か
ら水分が侵入しても比較的腐食は起こりに（い。Most of the semiconductor device configured in this way has moisture resistance ensured by the surface protection layer 4, and the portion to which the bonding wire 7 is bonded is the semiconductor substrate 1,
Since the bonding band 6 and the bonding ball 7a are made of an alloy such as St-^l-^U, corrosion is relatively unlikely to occur even if moisture enters from the outside.
しかし、その他のボンディングバンド６の部分は露出し
ており、電気化学的反応により腐食が進みやすい。従っ
てポンディングパッド６の周辺から腐食が始まり、ボン
デインクホール７ａの周辺が全て腐食した場合にはホン
ディングパッド′６と配線層３とが断線することとなる
ため、外部端子と内部回路間の電気的接続が失われると
いう問題があった。この腐食のメカニズムは、配線層３
として一般に用いられているアルミニうムか大気中では
酸化物を形成して不動体化しているが、湿気の高い状態
では腐食反応が進行して配線抵抗の増大から断線にいた
るものと考えられる。However, other portions of the bonding band 6 are exposed and are susceptible to corrosion due to electrochemical reactions. Therefore, corrosion starts from the area around the bonding pad 6, and if the area around the bonding ink hole 7a is completely corroded, the bonding pad '6 and the wiring layer 3 will be disconnected. There was a problem with electrical connections being lost. The mechanism of this corrosion is that the wiring layer 3
In the atmosphere, aluminum, which is commonly used as a wire, forms oxides and becomes a passivation material. However, in humid conditions, a corrosion reaction progresses, increasing wiring resistance and causing wire breakage.
そこで、表面保護層４の開口部５を小さくしてボンディ
ングボール７ａで開口部５を覆い、ホンディングパッド
６が露呈しないようにすることも考えられるが、この場
合はボンディング時の位置ずれ等によってボンディング
ボール７ａとホンディングパッド６との圧着面積が少な
くなって所定のホンディング強度が得られず、現実問題
として採用出来ないという問題があった。Therefore, it is conceivable to make the opening 5 of the surface protective layer 4 smaller and cover the opening 5 with the bonding ball 7a to prevent the bonding pad 6 from being exposed. There was a problem that the bonding area between the bonding ball 7a and the bonding pad 6 was reduced, and a predetermined bonding strength could not be obtained, so that it could not be adopted as a practical problem.
（ハ）目的
本発明はこのような問題点を解決し、ホンディングパッ
ドの腐食を部分的に抑止して、腐食による断線を未然に
防止出来る耐湿性の向上した半導体装置を提供すること
を目的とする。(c) Purpose The purpose of the present invention is to solve such problems and to provide a semiconductor device with improved moisture resistance that can partially suppress corrosion of the bonding pad and prevent disconnection due to corrosion. shall be.
（ニ）構成
そこで、本発明の特徴とする処は、表面保護層の開口部
に露出したホンディングパッドにボンディングされるボ
ンディングワイヤのホンディングボールと、前記表面保
護層の開口部内周縁からホンディングパッドに内向突出
した突出部とを圧着するようにした点にある。(d) Structure Therefore, the present invention is characterized by a bonding ball of a bonding wire bonded to a bonding pad exposed in an opening of a surface protective layer, and a bonding ball of a bonding wire bonded to a bonding pad exposed in an opening of a surface protective layer, and a bonding ball bonded to a bonding pad exposed in an opening of a surface protective layer. The inwardly projecting protrusion is crimped onto the pad.
（ホ）実施例
第３図は本発明に係る半導体装置のうち、ホンディング
パッド付近の模型的平面図、第４図は第３図のＢ−Ｂ断
面図である。(E) Embodiment FIG. 3 is a schematic plan view of the vicinity of a bonding pad of a semiconductor device according to the present invention, and FIG. 4 is a sectional view taken along line BB in FIG.
第３図、第４図において、従来例と同一部分は同一符合
で示す。２は、半導体基板１に形成された第１図及び第
２図と同様の分離拡散層である。In FIGS. 3 and 4, parts that are the same as those of the conventional example are indicated by the same reference numerals. Reference numeral 2 denotes an isolation diffusion layer similar to that shown in FIGS. 1 and 2 formed on the semiconductor substrate 1.
この半導体基板１はＰ型のシリコン単結晶からなるウェ
ハにて形成される。This semiconductor substrate 1 is formed of a wafer made of P-type silicon single crystal.
３は配線層であって、多くの場合は蒸着したアルミニウ
ムである。3 is a wiring layer, which is often made of vapor-deposited aluminum.
４は開口部５を有する表面保護層、６はこの開口部５に
露出した前記配線層３からなるホンディングパッドであ
り、ホンディングパッド６の周縁部を表面保護層４でも
って被覆している。この表面保護層４は例えば低温気相
成長させたリンシリケートガラス（ＰＳＧ ’）が用い
られる。4 is a surface protection layer having an opening 5; 6 is a bonding pad made of the wiring layer 3 exposed in the opening 5; the peripheral edge of the bonding pad 6 is covered with the surface protection layer 4; . This surface protective layer 4 is made of, for example, phosphosilicate glass (PSG') grown in a low temperature vapor phase.
しかして、４ａは前記表面保護層４の開口部５内周縁か
らホンディングパッド６に内向突出した突出部であり、
ポンディングパッド６にボンディングされるホンディン
グワイヤ７のボンディングホール７ａと圧着される。こ
の突出部はボンディングによる圧着面積に比べて十分小
さく、かつＩＣ加工精度、通電能力に支障を来さない程
度の幅に設定される。またボンディングワイヤ７はＡｕ
線等からなり、外部端子とポンディングパッド６とを電
気的に接続している。Thus, 4a is a protrusion that protrudes inward from the inner peripheral edge of the opening 5 of the surface protection layer 4 to the bonding pad 6,
It is crimped to the bonding hole 7a of the bonding wire 7 which is bonded to the bonding pad 6. This protrusion is sufficiently small compared to the area crimped by bonding, and the width is set to such an extent that it does not interfere with IC processing accuracy or current carrying capacity. Furthermore, the bonding wire 7 is made of Au.
It consists of a wire, etc., and electrically connects the external terminal and the bonding pad 6.
８ば開口部であって、配線層３と半導体基板１上に形成
された素子（図ではＰ形抵抗を示している）とを電気的
に接続するため、半導体基板１表面に被着されたＳｉＯ
２膜で形成された絶縁Ｎ９に開けられたものである。8 is an opening, which is attached to the surface of the semiconductor substrate 1 in order to electrically connect the wiring layer 3 and the element formed on the semiconductor substrate 1 (the figure shows a P-type resistor). SiO
This is an opening in the insulation N9 formed of two films.
なお、本発明は図示の実施例に限定されず、例えば突出
部４ａを複数個所に形成して、表面保護層４の開口部５
内周縁からホンディングパッド６に内向突出するも好ま
しい。また、表面保護層４はリンシリケートガラス（Ｐ
ＳＧ ）の代わりに例えば窒化膜や有機物の薄膜（シリ
コーン、パリレン、ボリイミ１″等）を用いるも望まし
い。Note that the present invention is not limited to the illustrated embodiment; for example, the protrusions 4a may be formed at a plurality of locations to form the openings 5 of the surface protection layer 4.
It is also preferable that the bonding pad 6 protrudes inward from the inner peripheral edge. Furthermore, the surface protective layer 4 is made of phosphorus silicate glass (P
It is also desirable to use, for example, a nitride film or an organic thin film (silicone, parylene, polyimide 1'', etc.) instead of SG).
（へ）効果
本発明は、以上詳述した構成にて所期の目的を有効に達
成した。特に、表面保護層の開口部内周縁からホンディ
ングパッドに内向突出した突出部と、ホンディングワイ
ヤのボンディングボールとを圧着したから、ボンディン
グバンドが水分等の侵入によって腐食し始めてもホンデ
ィングパッドの突出部に相当する部分は腐食することな
く、腐食による断線を未然に防止出来る耐湿性の向上し
た半導体装置となる。従って、半導体装置を長年使用し
たり高湿度中で使用しても水分等の侵入による配線層の
腐食断線や導通不良が生じることなく、耐湿性の高い半
導体装置を提供することが出来る。(F) Effect The present invention has effectively achieved the intended purpose with the configuration detailed above. In particular, since the protrusion that protrudes inward from the inner periphery of the opening of the surface protective layer to the bonding pad and the bonding ball of the bonding wire are crimped, even if the bonding band begins to corrode due to intrusion of moisture, the protrusion of the bonding pad can be maintained. The parts corresponding to the parts do not corrode, resulting in a semiconductor device with improved moisture resistance that can prevent wire breakage due to corrosion. Therefore, even if the semiconductor device is used for many years or in high humidity, there will be no corrosion of the wiring layer or conduction failure due to the intrusion of moisture, and a highly moisture-resistant semiconductor device can be provided.
従って、プリン１〜基板、セラミック基板に直接チップ
をホンディングするハイプリンＩ・構造や超小型パッケ
ージで、しかも苛酷な条件で使用される場合、ポンティ
ングバンドの露呈部が腐食されても断線することなく極
めて信頼性の高い半導体装置となる。Therefore, if the exposed part of the ponting band is corroded, it will not break even if the exposed part of the ponting band is corroded in a high-purin I structure in which chips are bonded directly to a substrate or ceramic substrate, or in an ultra-small package and used under harsh conditions. This results in an extremely reliable semiconductor device.
また、ボンディング部の位置ずれに対してもボンディン
グ部が腐食されないことから、腐食後の形状はボンディ
ング部と突出部との配線層が残存して接続強度が確保さ
れる。Further, since the bonding portion is not corroded even when the bonding portion is misaligned, the wiring layer between the bonding portion and the protruding portion remains in the shape after corrosion, and connection strength is ensured.
このように、今後更に表面保護層の耐湿性能が向」ニジ
、小型化が進み、高い信頼性が要求されるにつれ、ホン
ディングパッドの耐湿性の問題が極めて重要となって来
るが、本発明に係る半導体装置によりこの問題に十分対
応することが可能となった。As described above, as the moisture resistance of the surface protective layer continues to improve, miniaturization progresses, and high reliability is required, the issue of moisture resistance of the bonding pad will become extremely important. The semiconductor device according to the above has made it possible to fully deal with this problem.
第１図は従来の半導体装置のうら、特に築積回路のホン
ディングパッドの近辺を模型的に図示した平面図、第２
図は第１図のＡ−Ａｌｆｉ面図、第３図は本発明に係る
半導体装置のうち、バンド付近の模型的平面図、第４図
は第３図のＢ−Ｂ断面図である。
４・・・表面保護層、４ａ・・・突出部、５・・・開口
部、６・・・ボンディングバット、７・・・ボンディン
グワイヤ、７ａ・・・ボンディングボール。
特許出願人 ローム株式会社
代理人 弁理士 大 西 孝 治Fig. 1 is a plan view schematically showing the back of a conventional semiconductor device, especially the vicinity of the bonding pad of a built-in circuit;
3 is a schematic plan view of the vicinity of a band of the semiconductor device according to the present invention, and FIG. 4 is a sectional view taken along the line BB in FIG. 3. 4... Surface protective layer, 4a... Protrusion, 5... Opening, 6... Bonding bat, 7... Bonding wire, 7a... Bonding ball. Patent Applicant: ROHM Co., Ltd. Agent, Patent Attorney: Takaharu Ohnishi
Claims (1)
ドにボンディングされるボンディングワイヤのボンディ
ングボールと、前記表面保護層の開口部内周縁からポン
ディングパッドに内向突出した突出部とを圧着するよう
にしたことを特徴とする半導体装置。(1) The bonding ball of the bonding wire to be bonded to the bonding band exposed in the opening of the surface protective layer is crimped to the protrusion protruding inward from the inner periphery of the opening of the surface protective layer to the bonding pad. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59036836A JPS60180131A (en) | 1984-02-27 | 1984-02-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59036836A JPS60180131A (en) | 1984-02-27 | 1984-02-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60180131A true JPS60180131A (en) | 1985-09-13 |
Family
ID=12480828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59036836A Pending JPS60180131A (en) | 1984-02-27 | 1984-02-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60180131A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017210131A1 (en) * | 2016-06-02 | 2017-12-07 | Knowles Electronics, Llc | Method for protecting bond pads from corrosion and corresponding device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210639A (en) * | 1981-06-19 | 1982-12-24 | Nec Corp | Semiconductor device |
-
1984
- 1984-02-27 JP JP59036836A patent/JPS60180131A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210639A (en) * | 1981-06-19 | 1982-12-24 | Nec Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017210131A1 (en) * | 2016-06-02 | 2017-12-07 | Knowles Electronics, Llc | Method for protecting bond pads from corrosion and corresponding device |
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