JP2680969B2 - Semiconductor memory device - Google Patents

Semiconductor memory device

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Publication number
JP2680969B2
JP2680969B2 JP4075433A JP7543392A JP2680969B2 JP 2680969 B2 JP2680969 B2 JP 2680969B2 JP 4075433 A JP4075433 A JP 4075433A JP 7543392 A JP7543392 A JP 7543392A JP 2680969 B2 JP2680969 B2 JP 2680969B2
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JP
Japan
Prior art keywords
semiconductor chip
memory device
lead
semiconductor memory
wiring
Prior art date
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Expired - Fee Related
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JP4075433A
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Japanese (ja)
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JPH05243477A (en
Inventor
信子 中西
Original Assignee
日本電気アイシーマイコンシステム株式会社
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Priority to JP4075433A priority Critical patent/JP2680969B2/en
Publication of JPH05243477A publication Critical patent/JPH05243477A/en
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Publication of JP2680969B2 publication Critical patent/JP2680969B2/en
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体記憶装置、さらに
詳しくいえば、半導体チップ上に形成された配線形状を
考慮した半導体記憶装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in consideration of a wiring shape formed on a semiconductor chip.

【０００２】[0002]

【従来の技術】従来の半導体記憶装置のパッケージのう
ち樹脂封入されたものは、アイランドと呼ばれる半導体
チップを固定保持する金属部分と、リードと呼ばれるパ
ッケージのピンにつながった金属部分とから構成されて
いる。そして、半導体チップ上に設けられたボンディン
グパッドとリードが、ボンディングワイヤにより電気的
に接続されている。2. Description of the Related Art A conventional semiconductor memory device packaged with a resin is composed of a metal portion called an island for fixing and holding a semiconductor chip and a metal portion called a lead connected to a pin of the package. There is. The bonding pad and the lead provided on the semiconductor chip are electrically connected by a bonding wire.

【０００３】図３は上記半導体記憶装置の樹脂封入前の
状態の一部を示す平面図である。図３において、半導体
チップ１０はアイランド１１上に固定保持されており、
半導体チップ上に設けられたボンディングパッド１３ａ
〜１３ｄとリード１２ａ〜１２ｄとの間はそれぞれボン
ディングワイヤ１４ａ〜１４ｄにより電気的に接続され
ている。そして、リード１２ａ〜１２ｄはそのまま半導
体記憶装置のパッケージの図示しないピンへと繋がって
いる。FIG. 3 is a plan view showing a part of the semiconductor memory device before being filled with resin. In FIG. 3, the semiconductor chip 10 is fixedly held on the island 11.
Bonding pad 13a provided on the semiconductor chip
13d and the leads 12a to 12d are electrically connected by bonding wires 14a to 14d, respectively. Then, the leads 12a to 12d are directly connected to pins (not shown) of the package of the semiconductor memory device.

【０００４】このような従来の半導体記憶装置に対し、
近年、ＬＯＣ（Lead On Chip）と呼ばれる新しい技術に
より組み立てられた半導体記憶装置が提案されている。
これは半導体チップを固定保持するアイランドを用い
ず、パッケージのピンにつながったリード自体に半導体
チップを固定保持するものである。図４にそのような半
導体記憶装置の樹脂封入する前の状態を示す。図４にお
いて、図３で示した従来の半導体記憶装置と同一機能を
有する部分には同一番号を付してある。リード１２ａ〜
１２ｄと半導体チップ１０との間に粘着テープ１５を挿
入し、熱圧着により半導体チップをリードに固定してい
る。リード１２ａ〜１２ｄと半導体チップ上のボンディ
ングパッド１３ａ〜１３ｄとは図３と同様、ボンディン
グワイヤ１４ａ〜１４ｄにより電気的に接続されてい
る。また、リードによる半導体チップの保持効果を高め
るため、半導体チップ上のリードはある程度、幅を大き
くして粘着テープとの接触面積を大きくしている。In contrast to such a conventional semiconductor memory device,
In recent years, a semiconductor memory device assembled by a new technology called LOC (Lead On Chip) has been proposed.
This does not use an island for fixing and holding the semiconductor chip, but holds and holds the semiconductor chip on the leads themselves connected to the pins of the package. FIG. 4 shows a state of such a semiconductor memory device before resin encapsulation. 4, parts having the same functions as those of the conventional semiconductor memory device shown in FIG. 3 are designated by the same reference numerals. Lead 12a ~
An adhesive tape 15 is inserted between 12d and the semiconductor chip 10 and the semiconductor chip is fixed to the leads by thermocompression bonding. The leads 12a to 12d and the bonding pads 13a to 13d on the semiconductor chip are electrically connected by the bonding wires 14a to 14d, as in FIG. Further, in order to enhance the holding effect of the semiconductor chip by the leads, the leads on the semiconductor chip are made wider to some extent to increase the contact area with the adhesive tape.

【０００５】図５（ａ）に図４のＡ−Ａ’断面図を、図
５（ｂ）に図４のＢ−Ｂ’断面図をそれぞれ示す。図５
において、２１は半導体基板，２２は保護膜（絶縁膜）
であり、１５は粘着テープ，１２ａはリードである。ま
た、１３ａはボンディングパッド，１４ａはボンディン
グワイヤである。このＬＯＣ技術を用いるとアイランド
とリードとを分離する必要がないので、従来の組み立て
技術を用いた場合に比較して、その分離領域に相当する
分だけ大きな半導体チップを同じ大きさのパッケージに
組み込むことができるという利点がある。FIG. 5A is a sectional view taken along the line AA 'of FIG. 4, and FIG. 5B is a sectional view taken along the line BB' of FIG. FIG.
21 is a semiconductor substrate, and 22 is a protective film (insulating film)
15 is an adhesive tape, and 12a is a lead. Further, 13a is a bonding pad, and 14a is a bonding wire. When this LOC technology is used, it is not necessary to separate the island and the lead, so that a semiconductor chip that is larger by the amount corresponding to the separation area is incorporated in a package of the same size as compared with the case where the conventional assembly technology is used. There is an advantage that you can.

【０００６】また、リードが半導体チップ上に配置され
ているため、その形状を変えることにより、半導体チッ
プ上のボンディングパッドの配置の自由度が増すという
利点がある。例えば、ボンディングパッドを半導体チッ
プの中央に配置するということは従来技術ではボンディ
ングワイヤが長くなって半導体チップに接触するという
不具合が発生するが、このＬＯＣ技術では、そのような
問題は生じない。Further, since the leads are arranged on the semiconductor chip, there is an advantage that the degree of freedom in arranging the bonding pads on the semiconductor chip is increased by changing the shape thereof. For example, arranging the bonding pad at the center of the semiconductor chip causes a problem that the bonding wire becomes long and comes into contact with the semiconductor chip in the conventional technique, but such a problem does not occur in the LOC technique.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、このＬ
ＯＣ技術で組み立てた従来の半導体記憶装置では、半導
体ペレット上に形成した保護膜にクラックが発生しやす
いという問題がある。以下、この点について詳しく説明
する。一般に、半導体記憶装置では最も表面に近い配線
には、アルミニュム配線が用いられており、その上には
外部からの汚染や傷に対する保護を目的として酸化シリ
コンや窒化シリコンの保護膜が形成されている。このよ
うな構造を有する半導体記憶装置が高温に保持されるな
どの、熱的ストレスを受けると、アルミニュム配線と保
護膜との熱膨張率の相違から両者の界面に熱応力が発生
する。However, this L
The conventional semiconductor memory device assembled by the OC technique has a problem that cracks are likely to occur in the protective film formed on the semiconductor pellet. Hereinafter, this point will be described in detail. Generally, in the semiconductor memory device, an aluminum wiring is used for the wiring closest to the surface, and a protective film of silicon oxide or silicon nitride is formed on the wiring for the purpose of protection against external contamination and scratches. . When the semiconductor memory device having such a structure is subjected to thermal stress such as being kept at high temperature, thermal stress is generated at the interface between the aluminum wiring and the protective film due to the difference in thermal expansion coefficient between them.

【０００８】アルミニュム配線が太い場合には、この力
も大きく、ついには保護膜が損傷を受けてクラックが発
生したりする。そして、このクラックはアルミニュム配
線が太くて保護膜との接触面積が大きい程、発生しやす
い。半導体記憶装置では、半導体チップ上の周辺部に電
源系配線として５０μｍから１００μｍの幅のアルミニ
ュム配線が設けられている場合が多く、特にこの部分で
保護膜のクラックが発生しやすくなる。If the aluminum wiring is thick, this force is also large, and eventually the protective film is damaged and cracks occur. The crack is more likely to occur as the aluminum wiring is thicker and the contact area with the protective film is larger. In many cases, a semiconductor memory device is provided with an aluminum wiring having a width of 50 μm to 100 μm as a power supply wiring in the peripheral portion on a semiconductor chip, and cracks in the protective film are likely to occur particularly in this portion.

【０００９】一方、ＬＯＣ技術で組み立てた半導体記憶
装置では、半導体チップ表面は粘着テープを介してリー
ドと接触しているため、半導体チップ表面に形成した保
護膜はリードとの接触において熱応力を受ける。このた
め、太いアルミニュム配線とリードとに挟まれた領域の
保護膜は上下から熱応力をうけることとなり、クラック
が一層発生しやすくなるという問題がある。On the other hand, in the semiconductor memory device assembled by the LOC technique, the surface of the semiconductor chip is in contact with the leads through the adhesive tape, and therefore the protective film formed on the surface of the semiconductor chip is subjected to thermal stress when contacting with the leads. . Therefore, the protective film in the region sandwiched between the thick aluminum wiring and the leads is subject to thermal stress from above and below, which causes a problem that cracks are more likely to occur.

【００１０】保護膜にクラックが発生するのを防止する
ためには、アルミニュム配線と保護膜，保護膜とリード
との接触面積を小さくすればよい。アルミニュム配線に
関しては、スリットを入れることが考えられるが、配線
の全領域にわたってスリットを入れると、実行的配線幅
を減少させ、配線抵抗が増して回路動作上の問題が発生
する場合がある。また、接触面積を小さくするためリー
ドを細めると、ＬＯＣ特有のリードにより半導体チップ
を保持するという能力が弱まってしまうという問題があ
った。本発明の目的は上記問題を解決するもので、半導
体チップ表面に形成した保護膜が熱応力により損傷をう
けるのを防止した半導体記憶装置を提供することにあ
る。In order to prevent cracks from occurring in the protective film, the contact area between the aluminum wiring and the protective film and between the protective film and the lead may be reduced. Although it is conceivable to form a slit for the aluminum wiring, if a slit is formed over the entire area of the wiring, the effective wiring width may be reduced, the wiring resistance may increase, and problems in circuit operation may occur. Further, if the leads are thinned in order to reduce the contact area, there is a problem that the ability to hold the semiconductor chip by the leads peculiar to the LOC is weakened. An object of the present invention is to solve the above problems and to provide a semiconductor memory device in which a protective film formed on the surface of a semiconductor chip is prevented from being damaged by thermal stress.

【００１１】[0011]

【課題を解決するための手段】前記目的を達成するため
に本発明による半導体記憶装置は半導体チップ表面とパ
ッケージのリードとを接着手段を用いて前記リードに半
導体チップを固定するとともに前記半導体チップ上に設
けられた金属配線に接続されたボンディングパッドと前
記リードとをボンディングワイヤにより、電気的に接続
した半導体記憶装置において、前記半導体チップ上に形
成された金属配線のうち、少なくとも前記リード下の領
域の金属配線を複数に分割することにより他の領域の金
属配線幅より細く構成してある。To achieve the above object, in a semiconductor memory device according to the present invention, the surface of a semiconductor chip and the leads of a package are fixed to the leads by using an adhesive means and the semiconductor chip is mounted on the semiconductor chip. In a semiconductor memory device in which a bonding pad connected to a metal wiring provided on the above and the lead are electrically connected by a bonding wire, at least a region under the lead of the metal wiring formed on the semiconductor chip. By dividing this metal wiring into a plurality of metal wirings, the width of the metal wirings in other areas is made thinner.

【００１２】[0012]

【実施例】以下、図面を参照して本発明をさらに詳しく
説明する。図１は本発明による半導体記憶装置の実施例
を示す平面図である。この図は従来のＬＯＣ技術を示し
た図４の一部分に相当する場所を拡大して示した図であ
る。図１において、電源系アルミニュム配線６は半導体
チップ１の外周に設けられており、その幅は５０μｍ程
度である。この電源系アルミニュム配線６のリード２ａ
および２ｂの下の領域部分に２〜３μｍのスリット６
ａ，６ｂを設けて、１本当たりの配線幅が１５μｍにな
るようにしている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1 is a plan view showing an embodiment of a semiconductor memory device according to the present invention. This figure is an enlarged view of a portion corresponding to a part of FIG. 4 showing the conventional LOC technology. In FIG. 1, the power supply system aluminum wiring 6 is provided on the outer periphery of the semiconductor chip 1 and has a width of about 50 μm. Lead 2a of this power system aluminum wiring 6
And a slit 6 of 2 to 3 μm in the area below 2b
A and 6b are provided so that the wiring width per wire is 15 μm.

【００１３】このようにリードの下の領域部分にスリッ
トを入れることにより、配線抵抗を殆ど増やすことな
く、アルミニュム配線と保護膜との接触面積を小さくし
てクラックの発生を防止している。また、リードの形状
は何ら変わっていないので、リードによる半導体チップ
の保持能力が低減することはない。By thus forming the slit in the area under the lead, the contact area between the aluminum wiring and the protective film is made small and the generation of cracks is prevented, while the wiring resistance is hardly increased. Further, since the shape of the lead is not changed at all, the holding ability of the semiconductor chip by the lead does not decrease.

【００１４】図２は本発明の第２の実施例を示す平面図
である。図１で示した実施例と同じ場所を示している。
この実施例では半導体チップの太い金属配線７は保護膜
との間に働く熱応力を弱めるため、一定の間隔で１本の
スリット７ｃが設けられ、幅２４μｍ程度に分割されて
いる。そして、リードの下の領域に２本のスリット７
ａ，７ｂを設けて幅１５μｍ程度の配線になるようにし
ている。なお、以上説明した配線幅は特にその値に限定
されるものではなく他の領域より細い幅であれば任意に
設定できる。FIG. 2 is a plan view showing a second embodiment of the present invention. The same location as the embodiment shown in FIG. 1 is shown.
In this embodiment, the thick metal wiring 7 of the semiconductor chip weakens the thermal stress acting between the thick metal wiring 7 and the protective film, so that one slit 7c is provided at a constant interval and divided into a width of about 24 μm. Then, in the area under the lead, two slits 7
A and 7b are provided so that the wiring has a width of about 15 μm. The wiring width described above is not particularly limited to that value and can be arbitrarily set as long as it is narrower than other areas.

【００１５】[0015]

【発明の効果】以上、説明したように本発明は半導体チ
ップ表面とパッケージのリードとを接着する手段を用い
てリードに半導体チップを固定するとともに半導体チッ
プ上に設けられた金属配線に接続されたボンディングパ
ッドとリードとをボンディングワイヤにより、電気的に
接続した半導体記憶装置において、半導体チップ上に形
成された金属配線のうち、少なくともリード下の領域の
金属配線を複数に分割することにより他の領域の金属配
線幅より細く構成することにより、半導体チップ表面に
形成した保護膜が熱応力により損傷うけるのを防止でき
るという効果がある。As described above, according to the present invention, the semiconductor chip is fixed to the lead by using the means for adhering the surface of the semiconductor chip to the lead of the package and is connected to the metal wiring provided on the semiconductor chip. In a semiconductor memory device in which a bonding pad and a lead are electrically connected by a bonding wire, at least the metal wiring in the area under the lead among the metal wiring formed on the semiconductor chip is divided into a plurality of other areas. By making it thinner than the width of the metal wiring, it is possible to prevent the protective film formed on the surface of the semiconductor chip from being damaged by thermal stress.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による半導体記憶装置の実施例を示す平
面図である。FIG. 1 is a plan view showing an embodiment of a semiconductor memory device according to the present invention.

【図２】本発明による半導体記憶装置の他の実施例を示
す平面図である。FIG. 2 is a plan view showing another embodiment of the semiconductor memory device according to the present invention.

【図３】従来の半導体記憶装置の一例を示す平面図で、
半導体チップで固定保持する金属部分アイランドとパッ
ケージにつながった金属部分リードで構成された樹脂封
入前のものである。FIG. 3 is a plan view showing an example of a conventional semiconductor memory device,
It is a resin partial encapsulation consisting of a metal partial island fixedly held by a semiconductor chip and a metal partial lead connected to a package.

【図４】従来の半導体記憶装置の他の一例を示す平面図
である。FIG. 4 is a plan view showing another example of a conventional semiconductor memory device.

【図５】（ａ）は図４のＡ−Ａ’断面図，（ｂ）は図４
のＢ−Ｂ’断面図である。5A is a sectional view taken along the line AA ′ in FIG. 4, and FIG.
It is a BB 'sectional view of.

【符号の説明】[Explanation of symbols]

１，１０…半導体チップ ２ａ，２ｂ，１２ａ，１２ｂ…リード ３ａ，３ｂ，１３ａ〜１３ｄ…ボンディングパッド ６，７，１６…アルミニュム線 １４ａ〜１４ｄ…ボンディングワイヤ １５…粘着テープ ２１…半導体基板 ２２…保護膜 1, 10 ... Semiconductor chips 2a, 2b, 12a, 12b ... Leads 3a, 3b, 13a-13d ... Bonding pads 6, 7, 16 ... Aluminum wires 14a-14d ... Bonding wires 15 ... Adhesive tape 21 ... Semiconductor substrate 22 ... Protection film

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップ表面とパッケージのリード
とを接着手段を用いて前記リードに半導体チップを固定
するとともに前記半導体チップ上に設けられた金属配線
に接続されたボンディングパッドと前記リードとをボン
ディングワイヤにより、電気的に接続した半導体記憶装
置において、 前記半導体チップ上に形成された金属配線のうち、少な
くとも前記リード下の領域の金属配線を複数に分割する
ことにより他の領域の金属配線幅より細く構成したこと
を特徴とする半導体記憶装置。1. A surface of a semiconductor chip and a lead of a package are fixed to the lead by using an adhesive means, and a bonding pad connected to a metal wiring provided on the semiconductor chip is bonded to the lead. In a semiconductor memory device electrically connected by a wire, among the metal wiring formed on the semiconductor chip, at least the metal wiring in the area under the lead is divided into a plurality of metal wirings to be separated from the metal wiring width in other areas. A semiconductor memory device having a thin structure.
JP4075433A 1992-02-26 1992-02-26 Semiconductor memory device Expired - Fee Related JP2680969B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4075433A JP2680969B2 (en) 1992-02-26 1992-02-26 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4075433A JP2680969B2 (en) 1992-02-26 1992-02-26 Semiconductor memory device

Publications (2)

Publication Number Publication Date
JPH05243477A JPH05243477A (en) 1993-09-21
JP2680969B2 true JP2680969B2 (en) 1997-11-19

Family

ID=13576091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4075433A Expired - Fee Related JP2680969B2 (en) 1992-02-26 1992-02-26 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JP2680969B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4676573B1 (en) * 2010-08-25 2011-04-27 スターエンジニアリング株式会社 Method for connecting wound coil and IC chip for non-contact ID identification device

Also Published As

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JPH05243477A (en) 1993-09-21

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