JP2826432B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2826432B2 JP2826432B2 JP1511893A JP1511893A JP2826432B2 JP 2826432 B2 JP2826432 B2 JP 2826432B2 JP 1511893 A JP1511893 A JP 1511893A JP 1511893 A JP1511893 A JP 1511893A JP 2826432 B2 JP2826432 B2 JP 2826432B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead
- semiconductor device
- aluminum wiring
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
パッケージのリード形状の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement in a lead shape of a package.
【０００２】[0002]
【従来の技術】従来の半導体装置のパッケージのうち、
樹脂封入されたものは、アイランドと呼ばれる半導体チ
ップを固定し、保持する金属部分と、リードと呼ばれる
パッケージのピンにつながった金属部分とから構成され
ている。そして半導体チップ上に設けられたボンディン
グパッドとリードとが、ボンディングワイヤにより電気
的に接続されている。2. Description of the Related Art Among conventional semiconductor device packages,
The resin-encapsulated structure includes a metal part called an island for fixing and holding a semiconductor chip, and a metal part called a lead and connected to a pin of a package. The bonding pads and leads provided on the semiconductor chip are electrically connected by bonding wires.
【０００３】図２は、このような半導体装置の樹脂封入
前の状態を示した平面図である。図２に於いて、半導体
チップ１０はアイランド１１の上に固定、保持されてお
り、半導体チップ上に設けられたボンディングパッド１
３ａ〜１３ｄとリード１２ａ〜１２ｄとの間は、それぞ
れボンディングワイヤ１４ａ〜１４ｄにより電気的に接
続されている。そしてリード１２ａ〜１２ｄは、そのま
ま半導体装置のパッケージのピンへとつながっている
が、図２ではリードの途中から省略している。FIG. 2 is a plan view showing a state of such a semiconductor device before resin encapsulation. In FIG. 2, a semiconductor chip 10 is fixed and held on an island 11, and a bonding pad 1 provided on the semiconductor chip is provided.
The leads 3a to 13d and the leads 12a to 12d are electrically connected by bonding wires 14a to 14d, respectively. The leads 12a to 12d are directly connected to the pins of the package of the semiconductor device, but are omitted in FIG.
【０００４】このような従来の半導体装置に対し、近年
ＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉｐの略）と呼ばれる新
しい技術により組立てられた半導体装置が現れている。
これは、半導体装置チップを固定し、保持するアイラン
ドをなくして、パッケージのピンにつながったリード自
体により、半導体チップを固定し、保持するものであ
る。[0004] In recent years, a semiconductor device assembled by a new technique called LOC (abbreviation of Lead On Chip) has emerged from such a conventional semiconductor device.
In this method, the island for fixing and holding the semiconductor device chip is eliminated, and the semiconductor chip is fixed and held by the leads connected to the pins of the package.
【０００５】図３にそのような半導体装置の樹脂封入前
の平面図を示す。なお、図２で示した従来の半導体装置
と同一機能を有する部分には同一番号を付してある。FIG. 3 is a plan view of such a semiconductor device before resin encapsulation. Parts having the same functions as those of the conventional semiconductor device shown in FIG. 2 are denoted by the same reference numerals.
【０００６】図３に於いては、リード１２ａ〜１２ｄと
半導体チップ１０との間に粘着テープ１５を挿入し、熱
圧着により半導体チップをリードに固定している。そし
て、リード１２ａ〜１２ｄと半導体チップ上にボンディ
ングパッド１３ａ〜１３ｄとをボンディングワイヤ１４
ａ〜１４ｄにより電気的に接続することは図２で述べた
従来技術と同じである。またリードによる半導体チップ
の保持効果を高めるため、半導体チップ上のリードはあ
る程度幅を大きくして、粘着テープとの接触面を大きく
している。In FIG. 3, an adhesive tape 15 is inserted between the leads 12a to 12d and the semiconductor chip 10, and the semiconductor chip is fixed to the leads by thermocompression bonding. Then, the leads 12a to 12d and the bonding pads 13a to 13d on the semiconductor chip are
Electrical connection by a to 14d is the same as the prior art described with reference to FIG. Further, in order to enhance the effect of holding the semiconductor chip by the leads, the width of the leads on the semiconductor chip is increased to some extent to increase the contact surface with the adhesive tape.
【０００７】このＬＯＣ技術を用いると、アイランドと
リードとを分離する必要がないので、従来の組立技術を
用いた場合と比較して、その分離領域に相当する分だけ
大きな半導体チップを、同じ大きさのパッケージに組立
てることが出来るという利点がある。また、リードが半
導体チップ上に配置されているため、その形状を変える
ことにより、半導体チップ上のボンディングパッドの配
置の自由度が増すという利点もある。たとえば、ボンデ
ィングパッドを半導体チップの中央に配置するというこ
とも、従来技術ではボンディングワイヤが長くなって、
半導体チップに接触するという不具合が発生したが、こ
のＬＯＣ技術ではそのような問題も生じない。When the LOC technique is used, it is not necessary to separate the islands and the leads. Therefore, as compared with the case where the conventional assembling technique is used, a semiconductor chip larger by an amount corresponding to the separation area has the same size. There is an advantage that it can be assembled into a package. Further, since the leads are arranged on the semiconductor chip, there is an advantage that the degree of freedom of arrangement of the bonding pads on the semiconductor chip is increased by changing the shape. For example, placing the bonding pad in the center of the semiconductor chip also means that the bonding wire is longer in the conventional technology,
Although the problem of contact with the semiconductor chip has occurred, such a problem does not occur in this LOC technology.
【０００８】[0008]
【発明が解決しようとする課題】しかるに前述したＬＯ
Ｃ技術で組立てた従来の半導体装置では、半導体チップ
上に形成した保護膜にクラックが発生しやすいという問
題がある。以下にこの点について詳しく説明する。However, the above-mentioned LO
In a conventional semiconductor device assembled by the C technology, there is a problem that a crack is easily generated in a protective film formed on a semiconductor chip. Hereinafter, this point will be described in detail.
【０００９】一般に半導体装置では、最も表面に近い配
線にはアルミニウム配線が用いられており、その上に
は、外部からの汚染やキズに対する保護を目的として酸
化シリコンや窒化シリコンの保護膜を形成している。In general, in a semiconductor device, an aluminum wiring is used as a wiring closest to the surface, and a protective film of silicon oxide or silicon nitride is formed on the aluminum wiring for the purpose of protecting against external contamination and scratches. ing.
【００１０】一方、ＬＯＣ技術で組立てた半導体装置で
は、半導体チップ表面は粘着テープを介してではある
が、リードと接触している。このような構造を有する半
導体装置が高温に保持されるなどの熱的ストレスを受け
ると、アルミニウム配線と保護膜とリードとの熱膨張率
の違いから、三者の界面に熱応力が発生する。アルミニ
ウム配線とリードに挟まれた領域の保護膜は上下ら熱応
力を受けることになり、保護膜が損傷を受けてクラック
が発生したりする。そして、このクラックはアルミニウ
ム配線が太くて保護膜との接触面積が大きいほど発生し
やすい。On the other hand, in a semiconductor device assembled by the LOC technology, the surface of the semiconductor chip is in contact with the leads, though through an adhesive tape. When a semiconductor device having such a structure is subjected to thermal stress such as being kept at a high temperature, a thermal stress is generated at the interface between the aluminum wiring, the protective film, and the lead due to a difference in thermal expansion coefficient between the lead. The protection film in a region sandwiched between the aluminum wiring and the lead is subjected to thermal stress from above and below, and the protection film is damaged and cracks occur. These cracks are more likely to occur as the aluminum wiring is thicker and the contact area with the protective film is larger.
【００１１】半導体装置では、半導体チップ上の周辺部
に電源系配線として５０μｍから１００μｍ幅のアルミ
ニウム配線が設けられている場合が多く、特にこの部分
で保護膜のクラックが発生しやすくなっている。In a semiconductor device, an aluminum wiring having a width of 50 μm to 100 μm is provided as a power supply wiring in a peripheral portion on a semiconductor chip in many cases. In particular, a crack in a protective film easily occurs in this portion.
【００１２】保護膜にクラックが発生するのを防ぐため
には、アルミニウム配線と保護膜、保護膜とリードとの
接触面積を小さくすればよい。アルミニウム配線に関し
ては、スリットを入れる事が行われているが、配線の全
領域にわたってスリットを入れると、実効的配線幅を減
少させ、配線抵抗が増して回路動作上の問題が発生する
場合がある。又、接触面積を小さくするためにリードを
細めると、ＬＯＣ特有のリードにより半導体チップを保
持するという効果が弱まってしまうという問題が生じ
る。In order to prevent the occurrence of cracks in the protective film, the contact area between the aluminum wiring and the protective film and between the protective film and the lead may be reduced. For aluminum wiring, slitting is performed, but if slitting is performed over the entire area of the wiring, the effective wiring width will be reduced, wiring resistance will increase, and problems in circuit operation may occur . Further, if the leads are narrowed in order to reduce the contact area, there is a problem that the effect of holding the semiconductor chip by the leads specific to the LOC is weakened.
【００１３】そこで本発明の目的は、以上の問題を解決
して半導体チップを保持し、保護膜にクラックが発生す
るのを防ぐ事の出来る半導体装置を提供することにあ
る。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which solves the above problems and holds a semiconductor chip and can prevent a crack from being generated in a protective film.
【００１４】[0014]
【課題を解決するための手段】本発明の半導体装置は、
半導体チップ表面とパッケージのリードとを接着する手
段を用いて、前記リードに半導体チップを固定するとと
もに、半導体チップ上に設けられた金属配線に接続され
たボンディングパッドと前記リードとを、ボンディング
ワイヤにより電気的に接続した半導体装置に於いて、少
なくとも前記半導体チップの周辺部の太いアルミニウム
配線上で前記リードに溝を掘ったことを特徴として構成
される。According to the present invention, there is provided a semiconductor device comprising:
The semiconductor chip is fixed to the lead by using a means for bonding the surface of the semiconductor chip to the lead of the package, and a bonding pad connected to a metal wiring provided on the semiconductor chip and the lead are connected by a bonding wire. In the electrically connected semiconductor device, a groove is dug in the lead at least on a thick aluminum wiring at a peripheral portion of the semiconductor chip.
【００１５】[0015]
【実施例】以下に図面を用いて本発明の実施例について
説明する。図１は本発明の一実施例の平面図で、従来の
ＬＯＣ技術を示した図３の一部分に相当する場所を拡大
した図およびそのＡ−Ａ1 線断面図である。Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows an in plan view of an embodiment, expanding the location corresponding to a portion of FIG. 3 showing a conventional LOC technology figures and its A-A 1 line cross-sectional view of the present invention.
【００１６】図１に於いて１６は半導体チップ１０の周
辺部にもうけられた電源系のアルミニウム配線であり５
０μｍ程度の幅を有する。そして、半導体チップ上のリ
ード１２ａ，１２ｂは、このアルミニウム配線１６の上
の部分のみ溝が掘られている。このように、太いアルミ
ニウム配線上に限ってリードに溝を掘ることで、太いア
ルミニウム配線上の保護膜とリードとの接触面積が小さ
くなるので、太いアルミニウムは配線上の保護膜はリー
ドからの熱応力を受けにくくなり、クラックの発生を防
ぐ事が出来る。In FIG. 1, reference numeral 16 denotes a power supply aluminum wiring provided around the semiconductor chip 10;
It has a width of about 0 μm. In the leads 12a and 12b on the semiconductor chip, a groove is dug only in a portion above the aluminum wiring 16. As described above, by digging a groove in the lead only on the thick aluminum wiring, the contact area between the protective film on the thick aluminum wiring and the lead is reduced. It is less susceptible to stress and can prevent cracks from occurring.
【００１７】又、アルミニウム配線１６の幅は何ら変え
ていないので、配線抵抗が増大するなどの問題も生じな
い。Since the width of the aluminum wiring 16 is not changed at all, there is no problem such as an increase in wiring resistance.
【００１８】[0018]
【発明の効果】以上説明したように本発明は、半導体チ
ップ表面とパッケージのリードとを接着する手段を用い
て、前記リードに半導体チップを固定するとともに、半
導体チップ上に設けられた金属配線に接続されたボンデ
ィングパッドと前記リードとを、ボンディングワイヤに
より電気的に接続した半導体装置に於いて、少なくとも
前記半導体チップの周辺部の太いアルミニウム配線上で
前記リードに溝を掘ることで、半導体チップ表面に形成
した保護膜が熱応力により損傷を受けるのを防ぐ効果を
有する。As described above, according to the present invention, the semiconductor chip is fixed to the lead by using the means for bonding the surface of the semiconductor chip to the lead of the package, and the metal wiring provided on the semiconductor chip is fixed to the lead. In a semiconductor device in which a connected bonding pad and the lead are electrically connected by a bonding wire, a groove is formed in the lead at least on a thick aluminum wiring at a peripheral portion of the semiconductor chip, thereby forming a semiconductor chip surface. Has the effect of preventing the protective film formed on the substrate from being damaged by thermal stress.
【図１】本発明の一実施例の平面図、及びそのＡ−Ａ1
線を軸とし、縦方向に切った断面図である。FIG. 1 is a plan view of an embodiment of the present invention, and AA 1 thereof.
It is sectional drawing cut | disconnected in the longitudinal direction centering on the line.
【図２】半導体チップを固定、保持する金属部分アイラ
ンドと、パッケージにつながった金属部分リードで構成
された樹脂封入前の従来の半導体装置の平面図である。FIG. 2 is a plan view of a conventional semiconductor device before resin encapsulation constituted by a metal part island for fixing and holding a semiconductor chip and a metal part lead connected to a package.
【図３】リード自体により半導体チップを固定、保持す
る樹脂封入前の従来の半導体装置の平面図である。FIG. 3 is a plan view of a conventional semiconductor device before resin encapsulation for fixing and holding a semiconductor chip by a lead itself.
１０ 半導体チップ １１ アイランド １２ａ〜１２ｄ リード １３ａ〜１３ｄ ボンディングパッド １４ａ〜１４ｄ ボンディングワイヤ １５ 粘着テープ １６ アルミニウム配線 １７ 保護膜 １８ 半導体基板 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 11 Island 12a-12d Lead 13a-13d Bonding pad 14a-14d Bonding wire 15 Adhesive tape 16 Aluminum wiring 17 Protective film 18 Semiconductor substrate
Claims (2)
ードとを接着する手段を用いて、前記リードに半導体チ
ップを固定するとともに、半導体チップ上に設けられた
金属配線に接続されたボンディングパッドと前記リード
とを、ボンディングワイヤにより電気的に接続してなる
半導体装置に於いて、少なくとも前記半導体チップの周
辺部の太いアルミニウム配線上で前記リードに溝が形成
されていることを特徴とする半導体装置。A semiconductor chip is fixed to a lead by means of bonding a semiconductor device chip surface to a package lead, and a bonding pad connected to a metal wiring provided on the semiconductor chip and the lead are provided. And a semiconductor device electrically connected by bonding wires, wherein a groove is formed in the lead at least on a thick aluminum wiring at a peripheral portion of the semiconductor chip.
ニウム配線が電源系のアルミニウム配線であることを特
徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the thick aluminum wiring around the semiconductor chip is a power supply aluminum wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1511893A JP2826432B2 (en) | 1993-02-02 | 1993-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1511893A JP2826432B2 (en) | 1993-02-02 | 1993-02-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06232322A JPH06232322A (en) | 1994-08-19 |
| JP2826432B2 true JP2826432B2 (en) | 1998-11-18 |
Family
ID=11879916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1511893A Expired - Fee Related JP2826432B2 (en) | 1993-02-02 | 1993-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2826432B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5716997A (en) | 1994-09-01 | 1998-02-10 | Bridgestone Corporation | Polymeric reticulated structure and method for making |
-
1993
- 1993-02-02 JP JP1511893A patent/JP2826432B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06232322A (en) | 1994-08-19 |
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