JPH05251496A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPH05251496A JPH05251496A JP4050221A JP5022192A JPH05251496A JP H05251496 A JPH05251496 A JP H05251496A JP 4050221 A JP4050221 A JP 4050221A JP 5022192 A JP5022192 A JP 5022192A JP H05251496 A JPH05251496 A JP H05251496A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- bonding pad
- bonding
- polyimide resin
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ボンディングパッド領
域の下にポリイミド樹脂を有する半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a polyimide resin under a bonding pad region.
【０００２】[0002]
【従来の技術】従来、半導体素子は図３に示すように、
半導体基板１上に電子回路を形成する回路素子２と、第
１絶縁膜３上に形成されこの回路素子２を互いに接続す
る配線５と、第２絶縁膜６の開口に形成された、電子回
路の入出力端子であるボンディングパッド７とを有して
いる。また、この半導体素子をリードフレーム９のアイ
ランドに固着し、リードフレームのリードと前記ボンデ
ィングパッドとを金属細線８で接続して組立てた後、そ
れら構成品を樹脂封止して半導体装置として形成されて
いた。2. Description of the Related Art Conventionally, as shown in FIG.
A circuit element 2 that forms an electronic circuit on the semiconductor substrate 1, a wiring 5 that is formed on the first insulating film 3 and connects the circuit element 2 to each other, and an electronic circuit that is formed in the opening of the second insulating film 6. And the bonding pad 7 which is an input / output terminal. Further, the semiconductor element is fixed to the island of the lead frame 9, the leads of the lead frame and the bonding pads are connected by the fine metal wires 8 and assembled, and then these components are resin-sealed to form a semiconductor device. Was there.
【０００３】この半導体素子のボンディングパッド７と
リードフレームのリードとを金属細線８で接続する際
は、通常、ワイヤーボンディング装置を使用していた。
また、このワイヤーポンディング装置で金属細線を接続
するときには、ボンディングパッドに温度及び圧着荷重
による熱的及び機械的衝撃が加わるため、ボンディング
パッド下層の絶縁膜、電子回路を形成する回路素子、及
び半導体基板を破壊する危険があり、それを防止するた
めに、ボンディング時の温度及び圧着荷重の厳密な制御
を行なっていた。When connecting the bonding pad 7 of the semiconductor element and the lead of the lead frame with the fine metal wire 8, a wire bonding device is usually used.
Further, when connecting a thin metal wire with this wire bonding device, thermal and mechanical impacts due to temperature and pressure load are applied to the bonding pad, so that an insulating film under the bonding pad, a circuit element forming an electronic circuit, and a semiconductor. There is a risk of breaking the substrate, and in order to prevent it, the temperature during bonding and the pressure bonding load are strictly controlled.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の半導体
素子では、ボンディング時に急激な温度変化又は、圧着
荷重の変化があると、ボンディングパッドに熱的及び機
械的衝撃が加わり、ボンディングパッド下層の絶縁膜、
電子回路を形成する回路素子、及び半導体基板を破壊す
るという欠点がある。このため、信頼性のある接続方法
を得るためには、ボンディング時の温度及び圧着荷重を
厳密に制御しなければならないという欠点がある。In the conventional semiconductor device described above, if a rapid temperature change or a change in pressure bonding force is applied during bonding, thermal and mechanical impact is applied to the bonding pad, and the insulation of the lower layer of the bonding pad is prevented. film,
There is a drawback that the circuit element forming the electronic circuit and the semiconductor substrate are destroyed. Therefore, in order to obtain a reliable connection method, there is a disadvantage in that the temperature and pressure bonding load during bonding must be strictly controlled.
【０００５】本発明の目的は、かかる問題を解消し、信
頼性のある接続を有する半導体素子を提供することにあ
る。An object of the present invention is to solve the above problems and provide a semiconductor device having a reliable connection.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体素子は、
半導体基板上に積層された絶縁膜上に形成されたポリイ
ミド樹脂と、このポリイミド樹脂の上部に形成されたボ
ンディングパッドとを有している。The semiconductor device of the present invention comprises:
It has a polyimide resin formed on an insulating film laminated on a semiconductor substrate, and a bonding pad formed on the polyimide resin.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図１および図２は本発明の一実施例を示す半導体素
子の断面図である。この半導体素子は、図１に示すよう
に、Ｎ型又はＰ型半導体基板１に形成された回路素子２
と、半導体基板１及び回路素子２の上に積層された第１
絶縁膜３の上に、ポリイミド樹脂４が形成されている。
また、このポリイミド樹脂４の上に金属配線５に接続さ
れているボンディングパッド７が形成されており、第１
絶縁膜３の表面及び金属配線５の表面は第２絶縁膜６で
保護されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 and 2 are sectional views of a semiconductor device showing an embodiment of the present invention. As shown in FIG. 1, this semiconductor element is a circuit element 2 formed on an N-type or P-type semiconductor substrate 1.
And the first laminated on the semiconductor substrate 1 and the circuit element 2.
A polyimide resin 4 is formed on the insulating film 3.
Further, a bonding pad 7 connected to the metal wiring 5 is formed on the polyimide resin 4, and
The surface of the insulating film 3 and the surface of the metal wiring 5 are protected by the second insulating film 6.
【０００８】次に、この半導体素子における金属細線で
リードフレームとの接続について図２を参照して説明す
る。ワイヤボンディング時にボンディングパッド７には
ボンディングパッド７とリードフレーム９とを接続する
ための金属細線８が接続される。このワイヤボンディン
グ時にボンディンギュパッド７及びリードフレーム９に
は制御された温度が加えられ、金属細線８には制御され
た圧着荷重が加えられ溶着される。この溶着される際、
ボンディングパッド７には温度、圧着荷重による応力が
加わわるが、ボンディングパッド７の下層にあるポリイ
ミド樹脂４はボンディングパット７及び第１絶縁膜３よ
り柔らかく、衝撃を吸収できるので、第１絶縁膜３、回
路素子２、半導体基板１の破壊を防止できる。Next, the connection of the thin metal wire to the lead frame in this semiconductor element will be described with reference to FIG. A thin metal wire 8 for connecting the bonding pad 7 and the lead frame 9 is connected to the bonding pad 7 during wire bonding. At the time of this wire bonding, a controlled temperature is applied to the bonding pad 7 and the lead frame 9, and a controlled crimping load is applied to the thin metal wire 8 to weld them. When this is welded,
Although stress due to temperature and pressure load is applied to the bonding pad 7, the polyimide resin 4 under the bonding pad 7 is softer than the bonding pad 7 and the first insulating film 3 and can absorb shock, so the first insulating film 3 It is possible to prevent the circuit element 2 and the semiconductor substrate 1 from being broken.
【０００９】[0009]
【発明の効果】以上説明したように本発明は、半導体素
子のボンディングパッドの下にポリイミド樹脂を形成す
ることによって、ワイヤボンディング時の急激な温度変
化又は、圧着荷重の変化によるボンディングパッドに加
わる熱的及び機械的衝撃を吸収することができ、ボンデ
ィングパッド下層の絶縁膜、電子回路を形成する回路素
子及び半導体基板の破壊を防止できる。ワイヤーボンデ
ィング時の温度及び圧着荷重の変化の影響を受け難いた
め、温度及び圧着荷重の制御を容易にでき、さらに信頼
度の高い半導体素子が得られるという効果がある。As described above, according to the present invention, by forming the polyimide resin under the bonding pad of the semiconductor element, the heat applied to the bonding pad due to a rapid temperature change during wire bonding or a change in the pressure bonding load. It is possible to absorb physical and mechanical shocks and prevent damage to the insulating film under the bonding pad, the circuit element forming the electronic circuit, and the semiconductor substrate. Since it is not easily affected by changes in temperature and pressure bonding load at the time of wire bonding, there is an effect that the temperature and pressure bonding load can be easily controlled and a highly reliable semiconductor element can be obtained.
【図１】本発明の一実施例を示す半導体素子の断面図。FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.
【図２】本発明の一実施例の半導体素子をボンディング
したときの状態を示す断面図。FIG. 2 is a cross-sectional view showing a state when the semiconductor element of one embodiment of the present invention is bonded.
【図３】従来の半導体素子の断面図。FIG. 3 is a sectional view of a conventional semiconductor device.
１ 半導体基板 ２ 回路素子 ３ 第１絶縁膜 ４ ポリイミド樹脂 ５ 金属配線 ６ 第２絶縁膜 ７ ボンディングパッド ８ 金属細線 ９ リードフレーム 1 Semiconductor Substrate 2 Circuit Element 3 First Insulating Film 4 Polyimide Resin 5 Metal Wiring 6 Second Insulating Film 7 Bonding Pad 8 Metal Fine Wire 9 Lead Frame
Claims (1)
成されたポリイミド樹脂と、このポリイミド樹脂の上部
に形成されたボンディングパッドを有することを特徴と
する半導体素子。1. A semiconductor device comprising: a polyimide resin formed on an insulating film laminated on a semiconductor substrate; and a bonding pad formed on the polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4050221A JPH05251496A (en) | 1992-03-09 | 1992-03-09 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4050221A JPH05251496A (en) | 1992-03-09 | 1992-03-09 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05251496A true JPH05251496A (en) | 1993-09-28 |
Family
ID=12852999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4050221A Withdrawn JPH05251496A (en) | 1992-03-09 | 1992-03-09 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05251496A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378978C (en) * | 1997-01-17 | 2008-04-02 | 精工爱普生株式会社 | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| JP2017212595A (en) * | 2016-05-25 | 2017-11-30 | 日本電波工業株式会社 | Piezoelectric device |
| CN113841237A (en) * | 2019-05-30 | 2021-12-24 | 三菱电机株式会社 | Power semiconductor module and power conversion device |
-
1992
- 1992-03-09 JP JP4050221A patent/JPH05251496A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378978C (en) * | 1997-01-17 | 2008-04-02 | 精工爱普生株式会社 | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| JP2017212595A (en) * | 2016-05-25 | 2017-11-30 | 日本電波工業株式会社 | Piezoelectric device |
| CN107437929A (en) * | 2016-05-25 | 2017-12-05 | 日本电波工业株式会社 | Piezoelectric element |
| CN113841237A (en) * | 2019-05-30 | 2021-12-24 | 三菱电机株式会社 | Power semiconductor module and power conversion device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5793108A (en) | Semiconductor integrated circuit having a plurality of semiconductor chips | |
| US6461890B1 (en) | Structure of semiconductor chip suitable for chip-on-board system and methods of fabricating and mounting the same | |
| KR100825784B1 (en) | Semiconductor package suppressing a warpage and wire open defects and manufacturing method thereof | |
| CN212136426U (en) | Flip chip and chip packaging structure | |
| JPH02184054A (en) | Hybrid type resin sealed semiconductor device | |
| JPH11260962A (en) | Ball grid array type of semiconductor device | |
| JPH0722454A (en) | Semiconductor integrated circuit device | |
| JPH0547998A (en) | High density mounting semiconductor device | |
| JPH05251496A (en) | Semiconductor element | |
| JP2002026073A (en) | Semiconductor device and its manufacturing method | |
| JP2756791B2 (en) | Resin-sealed semiconductor device | |
| KR970069482A (en) | Semiconductor device, manufacturing method thereof and mounting method thereof | |
| JP2001094228A (en) | Mounting structure of semiconductor device | |
| KR100201379B1 (en) | Attaching method of semiconductor chip using a solder ball and structure of the same | |
| JP2007042702A (en) | Semiconductor device | |
| JP2680969B2 (en) | Semiconductor memory device | |
| JP2551243B2 (en) | Semiconductor device | |
| JP3348973B2 (en) | Semiconductor device | |
| JPH10214934A (en) | Semiconductor device and its manufacture | |
| JP2972679B2 (en) | Lead frame, resin-encapsulated semiconductor device and method of manufacturing the same | |
| JP3145892B2 (en) | Resin-sealed semiconductor device | |
| JPH11145374A (en) | Method of connecting semiconductor chip, and semiconductor integrated circuit | |
| KR19980044255A (en) | Lead Finger Structure of Flip Chip Substrate | |
| JP3115432B2 (en) | Semiconductor device | |
| CN113851437A (en) | Flip chip and chip packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |