JP2865224B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2865224B2 JP2865224B2 JP4014507A JP1450792A JP2865224B2 JP 2865224 B2 JP2865224 B2 JP 2865224B2 JP 4014507 A JP4014507 A JP 4014507A JP 1450792 A JP1450792 A JP 1450792A JP 2865224 B2 JP2865224 B2 JP 2865224B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- sealing resin
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置、
特に樹脂封止後の封止樹脂の硬化収縮によって封入され
る回路基板（以後、半導体チップと記す）の機能および
封止樹脂自体の特性が劣化するのを軽減するための構造
の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device,
In particular, the present invention relates to an improvement in a structure for reducing deterioration of the function of a circuit board (hereinafter, referred to as a semiconductor chip) and the characteristics of the sealing resin itself due to curing shrinkage of the sealing resin after resin sealing.
【０００２】[0002]
【従来の技術】樹脂封止型半導体装置は、半導体素子、
配線、保護膜等が多数作り込まれた半導体ウエハを半導
体チップ（以下チップと略記する）に分割し、得られた
チップをリードフレームに搭載し、チップの電極とリー
ドフレームのリードとを金線などで結線した後、リード
フレームを金型にセットしてエポキシ樹脂等を主成分と
する樹脂により封止している。2. Description of the Related Art A resin-encapsulated semiconductor device includes a semiconductor element,
A semiconductor wafer on which a large number of wirings, protective films, etc. are formed is divided into semiconductor chips (hereinafter abbreviated as chips), and the obtained chips are mounted on a lead frame, and the electrodes of the chips and the leads of the lead frame are connected to gold wires. After connection, the lead frame is set in a mold and sealed with a resin mainly composed of epoxy resin or the like.
【０００３】近年の大規模集積回路では、チップ寸法が
益々大きくなる傾向にあり、封止樹脂の硬化収縮によっ
て発生する内部応力が急激に増大している。[0003] In recent large-scale integrated circuits, the chip size tends to become larger and larger, and the internal stress generated by the shrinkage of the sealing resin due to curing has rapidly increased.
【０００４】その結果、応力の集中するチップ周辺、特
にコーナー部での装置構成材料の変形や割れ、素子特性
の劣化等、さまざまな問題が顕在化してきた。As a result, various problems such as deformation and cracking of the constituent materials of the device around the chip where stress is concentrated, particularly at the corners, deterioration of element characteristics, and the like have become apparent.
【０００５】図５−６は、従来の従来の樹脂封止型半導
体装置の要部構造を示す断面概略図である。FIG. 5-6 is a schematic sectional view showing a main structure of a conventional conventional resin-encapsulated semiconductor device.
【０００６】図５はパッケージ内全体を表す断面図であ
る。図６は半導体チップ周辺領域の部分断面図である。FIG. 5 is a sectional view showing the entire package. FIG. 6 is a partial sectional view of a semiconductor chip peripheral region.
【０００７】図５において、１はエポキシ等の樹脂から
なる封止用樹脂、２は封止樹脂中のフィラー、３はリー
ドフレーム、４は半導体素子（図示せず）が形成された
半導体チップ、５はアルミニウム等から成る金属配線、
６はアルミニウム等から成る外部端子取出し電極すなわ
ちボンディングパッド、７はシリコン酸化膜（Ｓｉ
Ｏ 2）もしくはポリイミド樹脂等からなる表面保護膜、
８は結線用の金線を表わす。In FIG. 5, reference numeral 1 denotes a resin such as an epoxy resin.
Sealing resin, 2 is a filler in the sealing resin, 3 is a lead
The semiconductor element (not shown) was formed on the frame 4 and 4.
A semiconductor chip, 5 is a metal wiring made of aluminum or the like,
Reference numeral 6 denotes an external terminal extraction electrode made of aluminum or the like.
The bonding pad 7 is a silicon oxide film (Si
O Two) Or a surface protective film made of polyimide resin, etc.
Reference numeral 8 denotes a gold wire for connection.
【０００８】また図６において、９は半導体基板内の不
純物拡散層、１０はシリコン酸化膜等の層間絶縁層、１
１は該層間絶縁層の一部に設けた接続用開口部を表わ
す。In FIG. 6, reference numeral 9 denotes an impurity diffusion layer in a semiconductor substrate; 10, an interlayer insulating layer such as a silicon oxide film;
Reference numeral 1 denotes a connection opening provided in a part of the interlayer insulating layer.
【０００９】なおチップ分割を容易にするためにチップ
周縁部（基板周縁層）１２上の表面保護膜は通常除去す
る。The surface protection film on the chip peripheral portion (substrate peripheral layer) 12 is usually removed to facilitate chip division.
【００１０】このようなチップ４を樹脂封止し、この樹
脂封止型半導体装置を低温と高温の雰囲気に繰り返しさ
らした場合（このような工程を熱衝撃試験と読んでい
る）、樹脂封止の硬化収縮により半導体チップ４に応力
が加わる。この応力は半導体チップ４の端部、特にコー
ナー部で大きい。このためコーナー部近傍の封止樹脂１
には割れが生じたり、チップ周縁部１２上のシリコン酸
化膜から剥離したりする。When such a chip 4 is sealed with a resin and the resin-sealed semiconductor device is repeatedly exposed to a low-temperature and high-temperature atmosphere (this process is referred to as a thermal shock test), Stress is applied to the semiconductor chip 4 by the curing shrinkage of the semiconductor chip 4. This stress is large at the end of the semiconductor chip 4, especially at the corner. For this reason, the sealing resin 1 near the corner portion
Cracks or peel off from the silicon oxide film on the chip peripheral portion 12.
【００１１】特に封止用樹脂はシリコン、シリコン酸化
膜、シリコン窒化膜等との接着力が弱く、収縮応力によ
り封止用樹脂が割れたり、剥離したりしやすい。In particular, the sealing resin has a weak adhesive force with silicon, a silicon oxide film, a silicon nitride film and the like, and the sealing resin is easily broken or peeled off due to shrinkage stress.
【００１２】その結果、応力の集中場所がより内側に移
動し、この応力によりチップ上の表面保護膜７がシリコ
ン酸化膜の場合には、それに割れが生じる。表面保護膜
７がポリイミド樹脂膜の場合には、変形、剥離が生じ、
その結果金属配線５が変形、断線、短絡したりする故障
が問題となっている。As a result, the location where the stress is concentrated moves further inward, and when the surface protection film 7 on the chip is a silicon oxide film, the stress causes cracks. When the surface protection film 7 is a polyimide resin film, deformation and peeling occur,
As a result, there is a problem that the metal wiring 5 is deformed, disconnected, or short-circuited.
【００１３】また、封止用樹脂に割れが生じると、外部
からの水の浸入を促すため、配線金属等の腐食を加速さ
せたり外部端子接続用の金線とボンディングパッドとの
接合を破壊し、半導体装置自体の信頼性を低下させる重
大な問題となる。Further, when cracks occur in the sealing resin, the penetration of water from the outside is promoted, so that the corrosion of the wiring metal or the like is accelerated or the bonding between the gold wire for connecting the external terminal and the bonding pad is broken. This is a serious problem that lowers the reliability of the semiconductor device itself.
【００１４】このような問題に対して、従来からいくつ
かの対策が講じられている。このような方法としては、
封止樹脂１を改良して低応力化すること、チップ上の表
面保護膜７を改良して低応力化することの２つに大別で
きる。Several countermeasures have been taken against such a problem. Such methods include:
It can be broadly classified into two types: improving the sealing resin 1 to reduce the stress, and improving the surface protective film 7 on the chip to reduce the stress.
【００１５】このうち、表面保護膜の改良方法として以
下の公知例などがある。特公昭６１−３４２５６号公報
には表面保護膜として用いるシリコン酸化膜７の厚みを
金属配線５の厚み以上にする。また特開昭６１−２８４
９３０号公報には半導体チップの外周部だけに表面保護
膜として機械的強度の大きな窒化膜を設ける。さらに特
開平１−２６１８５０号公報には半導体チップの周縁部
領域において基板周縁層と封止用樹脂の間に金属、金属
の酸化物、窒化物もしくは硅化物よりなる接着層を介在
させることにより半導体チップと封止樹脂との密着性を
向上させることが記載されている。Among these methods, there are the following known examples as methods for improving the surface protective film. In Japanese Patent Publication No. 61-34256, the thickness of the silicon oxide film 7 used as a surface protection film is set to be greater than the thickness of the metal wiring 5. Also, Japanese Patent Application Laid-Open No. 61-284
In Japanese Patent No. 930, a nitride film having high mechanical strength is provided only on the outer peripheral portion of a semiconductor chip as a surface protective film. Japanese Patent Application Laid-Open No. 1-261850 discloses a semiconductor device in which a bonding layer made of a metal, a metal oxide, a nitride or a silicide is interposed between a substrate peripheral layer and a sealing resin in a peripheral region of a semiconductor chip. It describes that the adhesion between the chip and the sealing resin is improved.
【００１６】また、他の例として、特開昭６０−１４０
７３９号公報には表面保護膜としてシリコン酸化膜から
成る層の上にさらにポリイミド樹脂等の比較的弾性率の
小さな材料を設け応力を吸収するもの。また、特開昭６
１−１７１１５６号公報には半導体チップ周縁部にシリ
コン樹脂等の軟質材を設け同じく応力負荷を吸収するも
のが提案されている。Another example is disclosed in Japanese Patent Application Laid-Open No. 60-140.
No. 739 discloses a method in which a material having a relatively small elastic modulus such as a polyimide resin is further provided on a layer made of a silicon oxide film as a surface protective film to absorb stress. In addition, Japanese Unexamined Patent Publication
Japanese Patent Application Laid-Open No. 1-171156 proposes a device in which a soft material such as a silicon resin is provided at a peripheral portion of a semiconductor chip to absorb a stress load.
【００１７】さらにまた特開昭５８−２７３４９号公報
に記載の半導体装置は、半導体チップの周囲に溝を形成
し、半導体チップと封止樹脂との密着性を向上させ半導
体装置の信頼性を高めることが提案されている。Further, in the semiconductor device described in Japanese Patent Application Laid-Open No. 58-27349, a groove is formed around the semiconductor chip to improve the adhesion between the semiconductor chip and the sealing resin, thereby improving the reliability of the semiconductor device. It has been proposed.
【００１８】[0018]
【発明が解決しようとする課題】しかし上記従来の樹脂
封止型半導体装置では以下の問題点があった。However, the conventional resin-encapsulated semiconductor device has the following problems.
【００１９】半導体装置の集積化が進み、チップの大型
化や素子、配線の微細化が急速に進んだ結果、チップサ
イズが１０ｍｍ□を越えたり、配線の幅や間隔がサブミ
クロン領域にまで縮小された集積回路が実現されてい
る。これらのチップを樹脂封止した場合、従来技術では
チップに加わる応力が大きいため、その軽減が不十分と
なってきている。As the integration of semiconductor devices has progressed, the chip size has increased, and elements and wiring have rapidly become finer. As a result, the chip size has exceeded 10 mm □, and the width and spacing of wiring have been reduced to the submicron region. Integrated circuit is realized. When these chips are sealed with a resin, the stress applied to the chips in the related art is large, so that the reduction is insufficient.
【００２０】特に従来の最初の３つの例では、表面保護
酸化膜としてのシリコン酸化膜、窒化膜あるいは金属、
金属の酸化物、窒化物もしくは硅化物と封止用樹脂との
接着力が弱いという欠点を依然有してている。また、収
縮応力の増大にともない封止用樹脂が割れたり、剥離し
たりし半導体装置の信頼性を低下させる。In particular, in the first three conventional examples, a silicon oxide film, a nitride film or a metal as a surface protective oxide film,
It still has the disadvantage that the adhesive force between the metal oxide, nitride or silicide and the sealing resin is weak. In addition, the sealing resin is cracked or peeled off with an increase in shrinkage stress, which lowers the reliability of the semiconductor device.
【００２１】また、その次の２つの公知例のようにチッ
プ表面や周縁部にポリイミド樹脂やシリコン樹脂等の軟
質材を設けても、本構造の場合以下の点で問題があっ
た。Further, even if a soft material such as a polyimide resin or a silicon resin is provided on the chip surface or the peripheral portion as in the following two known examples, this structure has the following problems.
【００２２】半導体ウエハをチップに分割する時には、
分離のためにダイヤモンドポイントやダイヤモンドブレ
ードで溝を入れるスクライビング工程および溝に応じて
ウエハを割り個々のチップに分割するクラッキング工程
を行なう必要がある。When dividing a semiconductor wafer into chips,
It is necessary to perform a scribing step of forming a groove with a diamond point or a diamond blade for separation and a cracking step of dividing a wafer into individual chips according to the groove.
【００２３】従来構造では、スクライブ領域にもポリイ
ミド樹脂やシリコーン樹脂等の軟質剤があり、スクライ
ビング時にはこれらの材料をも切断することになる。し
かしながらポリイミド樹脂やシリコーン樹脂等の軟質剤
の切断は極めて作業性が悪い。また、本工程はこれらの
樹脂層の剥離の原因ともなり、樹脂封止後の半導体装置
の信頼性の低下をきたす要因ともなる。In the conventional structure, a softening agent such as a polyimide resin or a silicone resin is also provided in the scribe region, and these materials are also cut during scribing. However, cutting of a softener such as a polyimide resin or a silicone resin is extremely poor in workability. In addition, this step causes separation of these resin layers, and also causes reduction in reliability of the semiconductor device after resin sealing.
【００２４】また最後に示した従来例においては、半導
体チップ周辺に設けた溝内へ、封止樹脂が充填されにく
いためにその効果が少なく、封止樹脂の割れ、表面保護
膜の剥離、配線特性の劣化等に起因した故障が発生す
る。In the conventional example shown last, the effect is small because the sealing resin is hardly filled in the groove provided around the semiconductor chip, so that the effect is small. A failure occurs due to deterioration of characteristics or the like.
【００２５】なお大規模化、複雑化する集積回路の実現
に不可欠な多層配線構造においても、封止樹脂の収縮応
力に起因して生じる配線層間の絶縁性の劣化や配線層間
の接続（コンタクト）特性の劣化等がより深刻な問題と
なっている。Even in a multilayer wiring structure which is indispensable for realizing a large-scale and complicated integrated circuit, deterioration of insulation between wiring layers and connection (contact) between wiring layers caused by contraction stress of sealing resin. Deterioration of characteristics has become a more serious problem.
【００２６】本発明の目的は、前述の問題、特に封止用
樹脂の割れや剥離の問題を解決し、ひいては表面保護膜
の変形、剥離、配線特性の劣化の問題を解決し大型化、
微細化、多層配線化する樹脂封止半導体装置の信頼性を
向上することにある。An object of the present invention is to solve the above-mentioned problems, in particular, the problems of cracking and peeling of the sealing resin, and to solve the problems of deformation and peeling of the surface protective film and deterioration of wiring characteristics, thereby increasing the size.
An object of the present invention is to improve the reliability of a resin-encapsulated semiconductor device to be miniaturized and formed into a multilayer wiring.
【００２７】[0027]
【課題を解決するための手段】上記目的を達成するため
に、本発明の樹脂封止型半導体装置は、半導体素子を形
成した半導体基板と、前記半導体基板上に形成された層
間絶縁膜と、前記層間絶縁膜上の所定領域に形成された
ボンディングパッドと、前記ボンディングパッドの所定
領域を除く前記半導体基板上に形成された表面保護膜
と、前記ボンディングパッドと接続されたボンディング
ワイヤーとを備え、前記表面保護膜に接着層を介してフ
ィラーが固着されている。In order to achieve the above object, a resin-encapsulated semiconductor device according to the present invention comprises: a semiconductor substrate on which a semiconductor element is formed; an interlayer insulating film formed on the semiconductor substrate; comprising a bonding pad formed on a predetermined region on the interlayer insulating film, said protective surface formed on a semiconductor substrate film except the predetermined area of the bonding pad, the bonding wire connected to said bonding pad, The surface protective film is covered by an adhesive layer.
Error is fixed .
【００２８】[0028]
【作用】本発明においては、表面保護膜上に固着された
フィラーが封止用樹脂により包み込まれ表面保護膜と封
止用樹脂が強固に接着される。In the present invention, the filler fixed on the surface protective film is wrapped by the sealing resin, and the surface protective film and the sealing resin are firmly bonded.
【００２９】半導体チップと封止用樹脂の密着力が強く
なると、封止用樹脂の割れや剥離が生じにくくなり、そ
の結果表面保護膜の変形や剥離、金属配線の変形、断
線、短絡等の故障の発生率が低減する。If the adhesive force between the semiconductor chip and the sealing resin is increased, cracking and peeling of the sealing resin is less likely to occur, and as a result, deformation or peeling of the surface protective film, deformation of metal wiring, disconnection, short circuit, etc. The failure rate is reduced.
【００３０】[0030]
【実施例】以下、本発明を実施例により図面を参照して
詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail by way of embodiments with reference to the drawings.
【００３１】図１〜図４は本発明の樹脂封止型半導体装
置の一例である。図１は、半導体チップの周縁領域の部
分断面概略図である。図１〜図３は半導体ウエハ上での
製作過程を示しす。図４は半導体チップを組立て、封止
した後の樹脂封止型半導体装置を示す。FIGS. 1 to 4 show an example of a resin-sealed semiconductor device according to the present invention. FIG. 1 is a schematic partial cross-sectional view of a peripheral region of a semiconductor chip. 1 to 3 show a manufacturing process on a semiconductor wafer. FIG. 4 shows a resin-sealed semiconductor device after a semiconductor chip is assembled and sealed.
【００３２】以下図１に従って説明するが、製作方法は
すべて周知の半導体装置製造技術によるものである。As described below with reference to FIG. 1, the manufacturing method is all based on a well-known semiconductor device manufacturing technique.
【００３３】さらにここで用いる番号で従来の技術で用
いたと同様のものを指すものには同一番号を用いた。そ
れ以外の番号では、１３は境界、１４はＳＯＧ（Spin O
n Glass）である。Further, the same reference numerals are used for the same reference numerals as those used in the prior art. In other numbers, 13 is a boundary and 14 is SOG (Spin O
n Glass).
【００３４】まず図１に示すように、不純物拡散層９を
形成したシリコン基板４上に、電極取出し孔１１および
半導体チップの周縁領域（基板周縁層）１２以外を０．
５μｍ程度の厚さを有するシリコン酸化膜から成る層間
絶縁膜１０によって被覆する。First, as shown in FIG. 1, on a silicon substrate 4 on which an impurity diffusion layer 9 has been formed, an area other than an electrode extraction hole 11 and a peripheral region (substrate peripheral layer) 12 of a semiconductor chip is set to 0.
It is covered with an interlayer insulating film 10 made of a silicon oxide film having a thickness of about 5 μm.
【００３５】なお、境界１３で示した位置は隣接する半
導体チップとの境界である。この位置で半導体ウエハが
切断され、チップに分割されることになる。The position indicated by the boundary 13 is a boundary with an adjacent semiconductor chip. At this position, the semiconductor wafer is cut and divided into chips.
【００３６】次に図２に示すようにアルミニウム合金等
からなる厚さ約１μｍの金属配線５を被覆し、所望のパ
ターンに加工後、表面保護膜７を形成する。Next, as shown in FIG. 2, a metal wiring 5 made of an aluminum alloy or the like and having a thickness of about 1 μm is coated, processed into a desired pattern, and a surface protective film 7 is formed.
【００３７】本表面保護膜は１００ｎｍ程度の厚さを有
するＰＳＧ膜の上に７００ｎｍ程度の厚さを有するプラ
ズマ窒化膜を堆積したものからなる。This surface protective film is formed by depositing a plasma nitride film having a thickness of about 700 nm on a PSG film having a thickness of about 100 nm.
【００３８】次に図３に示すように、封止用樹脂に混入
されるシリコン酸化物より成るフィラー２をシリコン酸
化膜や窒化膜よりなる表面保護膜上に、ＳＯＧ（Spin O
n Glass）１４を接着層として固着した。Next, as shown in FIG. 3, a filler 2 made of silicon oxide mixed into the sealing resin is coated on a surface protection film made of a silicon oxide film or a nitride film by SOG (Spin O 2).
n Glass) 14 was fixed as an adhesive layer.
【００３９】液状のＳＯＧ１４をプラズマ窒化膜上に厚
さ１.０μｍで塗布後、半径１０μｍ程度の球形のフィ
ラー２を液状のＳＯＧ１４上に散布する。ＳＯＧ１４を
温度４５０℃で３０分加熱することにより固化し、フィ
ラー２を表面保護膜７に固着させる。After applying the liquid SOG 14 to the plasma nitride film with a thickness of 1.0 μm, the spherical filler 2 having a radius of about 10 μm is sprayed on the liquid SOG 14. The SOG 14 is solidified by heating at a temperature of 450 ° C. for 30 minutes, and the filler 2 is fixed to the surface protective film 7.
【００４０】ボンディングパッド６および基板周縁層１
２上の表面保護膜は除去した。その後、半導体ウエハを
スクライブライン１３に沿って通常のスクライビングお
よびクラッキング工程によりチップ分割した。その後周
知の封止樹脂組立技術により、図４に示すように該チッ
プをリードフレーム（図示せず）に搭載し、チップの電
極とリードフレームのリードとを金線８で結線し、該リ
ードフレームを金型にセットして、フィラー２を混入し
たエポキシ等を主成分とする封止用樹脂１により封止し
た。Bonding pad 6 and substrate peripheral layer 1
The surface protective film on No. 2 was removed. Thereafter, the semiconductor wafer was divided into chips along a scribe line 13 by a normal scribing and cracking process. Thereafter, the chip is mounted on a lead frame (not shown) as shown in FIG. 4 by a well-known sealing resin assembling technique, and the electrodes of the chip and the leads of the lead frame are connected by gold wires 8. Was set in a mold, and sealed with a sealing resin 1 mainly composed of epoxy or the like mixed with a filler 2.
【００４１】本実施例で適用した表面保護膜上に固着さ
れたフィラーは、封止の際に封止用樹脂１により包み込
まれる。このため、表面保護膜と封止用樹脂が強固に接
着され、その接着力は極めて強い。したがって、本実施
例によれば半導体チップ表面と封止用樹脂との被着強度
が向上し、熱衝撃試験による封止用樹脂の割れや剥離を
防止する効果がある。したがって、封止用樹脂の割れや
はがれに起因した半導体回路の劣化を防ぐことができ
る。The filler fixed on the surface protective film applied in this embodiment is wrapped by the sealing resin 1 at the time of sealing. For this reason, the surface protective film and the sealing resin are firmly bonded, and the bonding strength is extremely strong. Therefore, according to the present embodiment, the adhesion strength between the semiconductor chip surface and the sealing resin is improved, and there is an effect of preventing cracking and peeling of the sealing resin by a thermal shock test. Therefore, deterioration of the semiconductor circuit due to cracking or peeling of the sealing resin can be prevented.
【００４２】また、本実施例ではチップ分割工程（スク
ライビング、クラッキング）での作業性の低下や製品歩
留りの低下といった問題は全く生じなかった。Further, in the present embodiment, no problems such as a decrease in workability and a decrease in product yield in the chip dividing process (scribing and cracking) did not occur at all.
【００４３】[0043]
【発明の効果】以上説明したように本発明によれば、封
止用樹脂と半導体チップの接着強度が向上し、熱衝撃等
で生じる封止用樹脂の応力によって引き起こされる封止
用樹脂の割れや剥離、表面保護膜の変形やクラックや剥
離等を防止することができる。したがって、それらに起
因した配線の変形、断線、短絡等の劣化による装置の品
質の低下が防止されるので半導体装置の信頼性が向上す
る。As described above, according to the present invention, the bonding strength between the sealing resin and the semiconductor chip is improved, and cracking of the sealing resin caused by stress of the sealing resin caused by thermal shock or the like. And peeling, deformation of the surface protective film, cracks and peeling, and the like can be prevented. Therefore, the quality of the device is prevented from deteriorating due to the deterioration of the wiring such as deformation, disconnection, short circuit, etc., and the reliability of the semiconductor device is improved.
【図１】本発明の一実施例の樹脂封止型半導体装置の部
分断面概略図FIG. 1 is a schematic partial sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例の樹脂封止型半導体装置の部
分断面概略図FIG. 2 is a schematic partial sectional view of a resin-sealed semiconductor device according to one embodiment of the present invention;
【図３】本発明の一実施例の樹脂封止型半導体装置の部
分断面概略図FIG. 3 is a schematic partial cross-sectional view of a resin-sealed semiconductor device according to one embodiment of the present invention.
【図４】本発明の一実施例の樹脂封止型半導体装置の部
分断面概略図FIG. 4 is a schematic partial cross-sectional view of a resin-sealed semiconductor device according to one embodiment of the present invention.
【図５】従来の樹脂封止型半導体装置の全体断面概略図
および部分断面概略図FIG. 5 is a schematic cross-sectional view and a schematic partial cross-sectional view of a conventional resin-encapsulated semiconductor device.
【図６】従来の樹脂封止型半導体装置の全体断面概略図
および部分断面概略図FIG. 6 is an overall cross-sectional schematic view and a partial cross-sectional schematic view of a conventional resin-sealed semiconductor device.
１ 封止用樹脂 ２ フィラー ３ リードフレーム ４ 半導体チップ ５ 金属配線層 ６ ボンディングパッド ７ 表面保護膜 ８ ボンディングワイヤ ９ 不純物拡散層 １０ 層間絶縁膜 １１ 電極取出し孔 １２ 基板周縁層 １３ スクライブライン １４ ＳＯＧ REFERENCE SIGNS LIST 1 sealing resin 2 filler 3 lead frame 4 semiconductor chip 5 metal wiring layer 6 bonding pad 7 surface protection film 8 bonding wire 9 impurity diffusion layer 10 interlayer insulating film 11 electrode extraction hole 12 substrate peripheral layer 13 scribe line 14 SOG
Claims (2)
記半導体基板上に形成された層間絶縁膜と、前記層間絶
縁膜上の所定領域に形成されたボンディングパッドと、
前記ボンディングパッドの所定領域を除く前記半導体基
板上に形成された表面保護膜と、前記ボンディングパッ
ドと接続されたボンディングワイヤーとを備え、前記表
面保護膜に接着層を介してフィラーが固着されているこ
とを特徴とする樹脂封止型半導体装置。A semiconductor substrate on which a semiconductor element is formed; an interlayer insulating film formed on the semiconductor substrate; a bonding pad formed in a predetermined region on the interlayer insulating film ;
And a surface protective film formed on the semiconductor substrate except predetermined regions of the bonding pad, and a bonding wire connected to said bonding pad, filler via an adhesive layer to the surface protective film is affixed A resin-encapsulated semiconductor device, comprising:
載の樹脂封止型半導体装置。Mounted semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4014507A JP2865224B2 (en) | 1992-01-30 | 1992-01-30 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4014507A JP2865224B2 (en) | 1992-01-30 | 1992-01-30 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05206335A JPH05206335A (en) | 1993-08-13 |
| JP2865224B2 true JP2865224B2 (en) | 1999-03-08 |
Family
ID=11862985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4014507A Expired - Fee Related JP2865224B2 (en) | 1992-01-30 | 1992-01-30 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2865224B2 (en) |
-
1992
- 1992-01-30 JP JP4014507A patent/JP2865224B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05206335A (en) | 1993-08-13 |
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