JP3296344B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a flip-chip type semiconductor device having a semiconductor chip mounted on a wiring board and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 23 shows a conventional flip-chip type semiconductor device 100. As shown in FIG. 23, external terminals (not shown) are formed in a predetermined area array arrangement on a peripheral portion of the semiconductor chip 101 or on an active region thereof, and solder, Au, Sn-Ag based alloy is formed on the external terminals. A bump 102 made of a metallic material such as that described above is formed. In a region on the semiconductor chip 101 where the bumps 102 are not formed, a passivation film 103 for protecting an active region on the chip surface is formed.

[0003] Such a flip-chip type semiconductor device 1
24 is mounted on a multilayer wiring board 104 having electrode pads (not shown) formed in the same pattern as the bump arrangement pattern of the flip-chip type semiconductor device 100 as shown in FIG. As described above, when the flip-chip type semiconductor device 100 is mounted on the multilayer wiring substrate 104, when solder is used as a bump material, an IR reflow process using Flux is usually used.

However, since there is a difference in the linear expansion coefficient between the multilayer wiring substrate and the flip-chip type semiconductor device, when the flip-chip type semiconductor device 100 is mounted on the multilayer wiring substrate 104 by such a method, a subsequent heat treatment is performed. Due to the shear stress acting on the bumps 102, the reliability of the connection between the bumps 102 and the multilayer wiring board 104 is lowered, that is, there is a problem that the temperature cycling characteristic is particularly poor in the mounting reliability. Conventionally, the following two types of mounting methods have been adopted to solve this problem.

First, as a first method, a multilayer wiring board 1
As 04, a ceramic-based material having a linear expansion coefficient close to that of silicon, such as ALN, muride, and glasslaser, is used to minimize the mismatch of the linear expansion coefficient with the semiconductor chip 101 to improve mounting reliability. Attempts have been made. Although this attempt is effective from the viewpoint of improving the mounting reliability, since the material of the multilayer wiring board is an expensive ceramic material, it is generally limited to high-end supercomputers and specific applications of large computers. Has been used.

Further, the flip chip type semiconductor chip 10
1 is generally used for a high-spec LSI, so that the product itself is expensive. Therefore, in the electric sorting process after mounting the flip-chip type semiconductor device 100 on the multilayer wiring board 104, if a defect is caused due to a portion other than the semiconductor chip 101, the non-defective semiconductor chip 1
01 needs to be repaired. As shown in FIG. 25, a non-defective semiconductor chip 101 can be removed by melting the bonding portion of the bump 102 and pulling up the semiconductor chip 101 on the back surface of the semiconductor chip 101 using a suction heating tool 105 for repair.

[0007] As shown in FIG. 26, the shape of the solder bump 106 after the adsorption and removal has been lost, so that the solder bump 106 cannot be reused as it is. Therefore, heat treatment is performed again,
The solder bump 106 having the deformed shape is melted and removed.
After that, the semiconductor device in which the solder bumps are newly formed is reused.

However, since the solder bumps 106 are formed on the barrier metal junction formed of Cu or the like provided on the semiconductor chip 101, the above-described three heat treatments of formation, removal, and re-formation are performed. Then, Sn, which is a composition of the solder bump, and Cu constituting the barrier metal are interdiffused, and the barrier metal is alloyed. There are layers of Ti and Cr below the barrier metal, and peeling is likely to occur at the interface between these layers and the alloyed barrier metal.
As a result, there arises a problem that the re-formed solder bumps come off the semiconductor chip.

Further, on the semiconductor chip, there is provided a multilayer structure including an interlayer insulating film, wiring of Al, Cu, etc. The multilayer structure has a difference in thermal expansion coefficient between a plurality of materials and a via. There is a residual stress due to a pattern such as a position and a wiring configuration. After the three heat treatments, at least the uppermost passivation film 103 (for the purpose of protecting the active region of the semiconductor chip 101, an inorganic material such as a PI organic material or a silicon oxide film is formed under the influence of the residual stress caused by these patterns) (Made of material) is cracked. After the solder bumps are formed again, a cleaning step is performed to remove residual impurities.Halogen ions contained in the cleaning liquid and moisture in the air enter the multilayer wiring layer from cracks in the passivation film, and The resulting hydrochloric acid and Al wiring cause a chemical reaction,
There was a problem of disconnection.

As described above, when a multilayer wiring board made of a ceramic material is used, since the semiconductor chip is heated to a high temperature and pulled up, it is formed for the purpose of protecting the active region of the semiconductor chip 101. In some cases, the passivation film 103 may be damaged, resulting in a defective semiconductor chip.

As a second method, recently, Japanese Patent Publication No. 6-07
The technology disclosed in Japanese Patent No. 1030 has become a plasterer. This is a technology that can improve the mounting reliability even when a multilayer wiring board using an organic material that is relatively inexpensive and has a large linear expansion coefficient is used for flip-chip mounting. An underfill resin is arranged between the substrate and a multilayer wiring board using a base material. As shown in FIG. 27, by disposing the underfill resin 207 between the semiconductor chip 201 and the multilayer wiring board 204 using an organic material, the underfill resin 207 is placed between the semiconductor chip and the multilayer wiring board using the organic material. The shear stress acting on the existing bump 202 connection portion is dispersed, and the mounting reliability is improved. Multilayer wiring board 204
On the top, electrode pads 208 are provided in the same pattern as the bump arrangement pattern of the semiconductor chip.

In this mounting method, the underfill resin 2
By interposing 07 between the semiconductor chip and the multilayer wiring board using an organic material, the multilayer wiring board 204 using an inexpensive organic material can be used. However, in the electrical sorting process after mounting, if a defect occurs in a part other than the semiconductor chip, repair of a good semiconductor chip is almost impossible due to the presence of the underfill resin between the semiconductor chip and the multilayer wiring board. It is possible. In this case, a defect occurs in peripheral devices including a multilayer wiring board using an organic material, so that the device becomes low.
It cannot be said that cost reduction can be promoted.

As described above, in each of the conventional techniques, there is a problem that it is difficult to reuse a good flip-chip type semiconductor chip.

When an expensive ceramic material is used for the multilayer wiring board, which is the first method, the difference in the thermal expansion coefficient between the semiconductor chip and the multilayer wiring board becomes small, and the shear stress acting on the bump connection portion becomes small. Become. However, since the cost of the ceramic multilayer wiring board is very large, there is a problem that the use application of the flip-chip type semiconductor device is limited to a high-end region such as a high-performance computer.

In addition, in the electrical sorting process after mounting the flip-chip type semiconductor chip on the multilayer wiring board, if a defect other than the semiconductor chip is caused, it is necessary to repair a good semiconductor chip. Comes up. However, in the step of heating the semiconductor chip up to a high temperature, the passivation film on the removed semiconductor chip is cracked, and there is a problem that an active region including the Al wiring under the passivation film is damaged. .

Further, in this case, in order to reuse, 3
Times of heat treatment, the Sn of the barrier metal solder material
Alloying occurs, and peeling occurs at the interface between the alloyed barrier metal and the Ti layer or Cr layer below the barrier metal.

In the second method, when an inexpensive organic material is used for the multilayer wiring board, an underfill resin is interposed between the semiconductor chip and the organic multilayer wiring board, and the semiconductor chip and the multilayer wiring board are interposed. The mounting reliability is ensured by dispersing the shear stress acting on the bump connection portion with the wiring board. In this case as well, in the electrical selection process after mounting the flip-chip type semiconductor chip on the multilayer wiring board, if a defect occurs due to a part other than the semiconductor chip, it is necessary to repair a good semiconductor chip. Comes up. However, the conventional flip-chip type semiconductor chip provided with an underfill resin has a problem that repair is technically difficult.

[0018]

SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-chip type semiconductor device which is repairable and has excellent mounting reliability. In particular, the present invention provides a flip-chip type semiconductor device capable of repairing a semiconductor chip from a multilayer wiring board and having no damage to an active region including an Al wiring of the semiconductor chip at the time of repair.

[0019]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor chip having a bump electrode, a conductive column provided on the bump electrode, a ball electrode provided on the conductive column, and a wiring board having an external electrode pad to which the ball electrode is connected; It is characterized by having.

According to the method of manufacturing a semiconductor device of the present invention, there are provided a step of forming a plurality of bump electrodes on a semiconductor wafer, a step of providing an insulating material layer between the plurality of bump electrodes, and a step of forming a conductive layer on the bump electrodes. A step of forming a column; and a step of forming a ball electrode on the conductive column.

According to still another method of manufacturing a semiconductor device of the present invention, a step of forming a plurality of bump electrodes on a semiconductor chip, a step of providing an insulating material layer between the plurality of bump electrodes, Forming a conductive column on the conductive column; and forming a ball electrode on the conductive column.

Still another method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of bump electrodes on a semiconductor wafer, and a step of connecting the semiconductor wafer to a temporary conductive substrate via the bump electrodes. A step of providing an insulating material layer between the plurality of bump electrodes between the semiconductor wafer and the conductive temporary substrate, and patterning the conductive temporary substrate to form a conductive column on the bump electrodes. Forming a ball electrode on the conductive column.

Still another method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of bump electrodes on a semiconductor chip and a step of connecting the semiconductor chip to a temporary conductive substrate via the bump electrodes. A step of providing an insulating material layer between the plurality of bump electrodes between the semiconductor chip and the conductive temporary substrate, and patterning the conductive temporary substrate to form a conductive column on the bump electrodes. Forming a ball electrode on the conductive column.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A flip-chip type semiconductor device relates to a bump-like bump electrode (hereinafter, referred to as: "bump") which is previously formed on a semiconductor wafer using a solder material mainly composed of Sn or Pb.
Solder bumps) are formed in a predetermined pattern. Next, Cu
Alternatively, a semiconductor wafer on which solder bumps are formed is aligned and arranged on a temporary substrate made of a solid metal material having excellent solder wettability such as Ni. Thereafter, the semiconductor wafer and the temporary substrate are passed through a heating reflow process in a state where they are aligned, and the semiconductor wafer and the temporary substrate are joined by solder bumps. At this time, in order to stabilize soldering, flux may be used, or a heating reflow process may be performed in an inert gas atmosphere.

After that, an insulating material layer mainly composed of an organic insulating material is disposed in a gap between solder bumps existing between the semiconductor wafer and the temporary substrate. Thereafter, the temporary substrate is patterned so as to leave the temporary substrate portion on the solder bump formation pattern. Thereafter, a stress buffer resin is arranged around the metal column for the purpose of mechanical protection of the metal column made of a metal material having excellent solder wettability such as Cu or Ni remaining on the solder bump. .

After that, when a very small amount of insulating material adheres to the vicinity of the top of the metal column, a plasma surface treatment technique, a CMP technique, or a laser is used to ensure the cleanliness of the top of the metal column. Use processing technology to ensure the cleanliness of the metal column.

Thereafter, a solder ball having an external terminal function is formed on the metal column portion by using a solder material containing Sn or Pb as a main component.

A semiconductor wafer in which solder balls are formed as external terminals on a metal column portion is cut in a predetermined pattern, and the semiconductor wafer is separated into semiconductor chips.

According to the above process, the external terminal having the insulating material layer on the passivation film of the semiconductor chip, including the solder bumps, the metal column portions, and the solder bumps on the semiconductor chip, and having a large height from the surface of the semiconductor chip. A flip-chip type semiconductor device provided with a solder bump electrode as a semiconductor device can be manufactured.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a sectional view of a semiconductor wafer used in a semiconductor device according to the present invention. As shown in FIG. 1B, a bump-shaped bump electrode 2 is formed on a semiconductor wafer 1 in a predetermined pattern. The bump electrode 2 is made of, for example, S
It is formed using a solder material containing n or Pb as a main component. Hereinafter, it is referred to as a solder bump 2. Semiconductor wafer 1
The solder bump 2 is formed by, for example, a plating method, a vapor deposition method, or a screen printing method using a solder paste material. A passivation film (not shown) for protecting the active region on the surface of the semiconductor wafer 1 is formed in a region other than the region where the solder bumps 2 are formed on the semiconductor wafer 1.

Next, as shown in FIG.
The semiconductor wafer 1 provided with the solder bumps 2 is positioned and arranged on a temporary substrate 3 made of a solid metal material having excellent solder wettability.

The material of the temporary substrate 3 is, for example, a material in which a Cu plate is subjected to Ni plating or a material in which the Ni plate is C-plated.
u-plated or SUS plate with Cu
Alternatively, it is preferable to use a Ni-plated one.

Next, as shown in FIG.
A heating reflow process is performed in a state where the semiconductor substrate 1 and the temporary substrate 3 are aligned, and the semiconductor wafer 1 and the temporary substrate 3 are
To join. At this time, in order to stabilize the soldering, for example, flux is used, or a heating reflow process is performed in an inert gas atmosphere. When using Flux, it is preferable to perform the Flux cleaning step in consideration of the process stability and quality stability in the next step from the viewpoint of ensuring PKG quality.

Next, as shown in FIG.
An insulating material 4 containing an organic insulating material as a main component is disposed in a gap between the solder bumps 2 provided between the solder substrate 2 and the temporary substrate 3. As a means for disposing the insulating material 4, when the insulating material 4 is a liquid resin, for example, the resin is dropped on the side surface of the wafer by potting, and the liquid is formed by utilizing the capillary phenomenon between the solder bumps 2. There is a method of injecting resin. Alternatively, there is a method of disposing a liquid resin by a printing / vacuum defoaming method. When the insulating material 4 is a solid resin, a transfer molding method may be used. The film thickness of the insulating material 4 is, for example, 100 μm to 150 μm.

The four layers of insulating material are made of epoxy resin, silicon resin, polyimide resin, polyolefin resin,
It is preferable that any one of the cyanate ester-based resin, the phenol-based resin, and the naphthalene-based resin be used as a main component.

Next, as shown in FIG. 5, the temporary substrate 3 is subjected to a patterning process so as to leave a portion on the solder bumps 2 of the temporary substrate. As a patterning method, for example, a photoresist material is coated on the temporary
There is a method of performing a development process and performing wet etching using a photoresist material as a mask. As the etchant, for example, a liquid such as ferric chloride or sulfuric acid + hydrogen peroxide solution can be used. As a patterning method, or
Patterning can be performed by a laser processing method. If the pattern of the solder bumps 2 on the semiconductor wafer 1 is very fine, patterning may be performed using a dry etching technique.

As described above, the conductive columns 5 are formed on the solder bumps 2. Conductive column 5 in this embodiment
Is made of a metal material having excellent solder wettability, such as Cu or Ni, and is hereinafter referred to as a metal column 5. The height of the metal column 5 is, for example, 50 μm to 15 μm.
0 μm.

As a result, the surface of the insulating material layer 4 on the semiconductor wafer 1 is at substantially the same height as the interface between the solder bump 2 and the metal column 5.

Thereafter, as shown in FIG.
A ball electrode 7 serving as an external terminal function is formed thereon.
The ball electrode 7 is made of, for example, a solder material containing Sn or Pb as a main component. Hereinafter, it is referred to as a solder ball 7.

Next, as shown in FIG. 7A, the semiconductor wafer 1 in which the solder balls 7 as external terminals are formed on the metal columns 5 is placed with the surface on which the solder balls 7 are formed on the upper side. Then, cutting is performed in a predetermined pattern using a dicing blade 8 or the like, and as shown in FIG. 7B, a process of singulating the semiconductor wafer 1 into the semiconductor chips 9 is performed.

Through the above steps, the insulating material layer 4 is provided on the passivation film of the semiconductor chip 9 and comprises the solder bumps 2, the metal column portions 5, and the solder balls 7,
A flip-chip type semiconductor device provided with an external terminal having a large height from the surface of a semiconductor chip is manufactured.

After the semiconductor device manufactured by such a manufacturing method is mounted on a multilayer wiring board, an electric sorting process is performed.
As a result, when the semiconductor chip needs to be repaired, the solder ball 7 is heated at a temperature at which the solder ball 7 can be melted, and the solder ball 7 is separated from the multilayer wiring board. Thereafter, a heating step is further performed to remove the solder balls 7 and form solder balls on the metal columns 5 again. In the present invention, since the insulating material layer 4 is formed on the passivation film,
Even after the formation, removal, and re-formation of the solder balls and the three heating steps, the possibility of cracks occurring in the passivation film is reduced. Furthermore, since the insulating material layer is formed of a material having a low elastic modulus, no cracks are generated in the insulating material layer. Ions can be prevented from entering the wiring layer of the semiconductor chip.

The insulating material 4 is preferably a soft material having a low elastic modulus such as an organic material. As a result, even after the three heat treatments described above, no crack is formed in the insulating material layer 4 and even if a crack occurs in the passivation film,
Water and fluorine ions can be prevented from entering. In other words, it is preferable that the four layers of the insulating material are formed of a material having an elastic modulus that does not cause cracking even when heat treatment is performed at a temperature at which the solder balls 7 are melted.

Further, as the insulating material 4, it is preferable to use a material having chemical resistance. That is, it is preferable that the four layers of the insulating material be made of a material having resistance to a chemical containing a fluorine-based ion, such as a cleaning liquid.

In the first embodiment, three heat treatments are performed to separate the solder balls 7 and form solder balls again. At this time, melting of the solder bumps 2 occurs and alloying of the barrier metal occurs. However, the solder ball 2 is mechanically fixed to the semiconductor chip 2 by the insulating material layer 4, and the solder bump 2 does not peel off.

Further, in the first embodiment, the bump electrode 2 may be formed of a material having a higher melting temperature than the ball electrode 7. For example, the compositions of the solder forming the solder bumps 2 and the solder balls 7 are changed, and the melting points are set to different values. Specifically, the melting point of the solder ball 7 is set lower than the melting point of the solder bump 2. This allows
Even after three heat treatments for forming, melting, and re-forming the solder balls 7, the solder bumps 2 do not melt, and the alloying of the barrier metal can be prevented.

More specifically, the solder bump 2 is made of Sn 5%, P
The solder bumps 7 can be formed from solder having a melting point of about 183 ° C., which has a melting point of about 63% Sn and Pb 37%. For example, by performing a heat treatment at about 230 ° C. to about 250 ° C., the solder ball 7 can be removed and reformed, but at this time, the solder constituting the solder ball 2 does not melt and does not alloy with the barrier metal. .

As a result, a highly reliable semiconductor device can be reused.

Referring to FIGS. 8 to 15, a second embodiment of the present invention will be described.
An example will be described.

FIGS. 8 to 12 show the same steps as in the first embodiment.

Thereafter, as shown in FIG. 13, a stress buffer resin 6 is disposed around the metal column 5 for the purpose of mechanically protecting the conductive column 5 (hereinafter, referred to as the metal column 5).

At this time, when the stress buffer resin 6 is a liquid resin, for example, a spin coating method or a printing method is used. In the case of a solid material, the stress buffering resin 6 can be arranged around the metal column 5 by using, for example, a transfer molding method.

The stress buffer resin 6 is formed mainly of any one of epoxy resin, silicon resin, polyimide resin, polyolefin resin, cyanate ester resin, phenol resin and naphthalene resin. Is preferred.

Then, near the top of the metal column 5,
If a very small amount of the stress buffer resin 6 adheres, a plasma surface treatment technique, a laser processing technique, or a CMP (Ch)
electrical Mechanical Polish
ng) Using a polishing technique typified by a technique, the cleanliness of the metal column portion is ensured.

Next, as shown in FIG. 14, a ball electrode 7 as an external terminal function is formed on the metal column 5. The ball electrode 7 is made of, for example, a solder material containing Sn or Pb as a main component. Hereinafter, it is referred to as a solder ball 7.

Next, as shown in FIG. 15, the semiconductor wafer 1 in which the solder balls 7 as the external terminals are formed on the metal column 5 is placed on the upper side with the surface on which the solder balls 7 are formed. Cutting is performed in a predetermined pattern using a dicing blade 8 or the like, and individualization processing from the semiconductor wafer 1 to the semiconductor chips 9 ′ is performed as shown in FIG.

In the second embodiment, a stress buffer resin 6 is provided between the metal column portions 5. In the configuration of the first embodiment, when a shear stress is generated at a connection portion between the semiconductor chip and the multilayer wiring board due to a difference in thermal expansion coefficient between the semiconductor chip and the multilayer wiring board, the stress in the configuration of the first embodiment is Is the solder bump 2 of the metal column 5
Tends to concentrate on the connection with the solder ball 7 of the metal column 5. However, in the second embodiment, the stress can be absorbed and absorbed by the stress buffer resin 6 and can be reduced.

The stress buffer resin 6 can reliably insulate the metal columns 5 from each other, and can prevent the metal columns from contacting each other and causing a short circuit when stress is generated.

The insulating material 4 preferably has chemical resistance. Further, a material having a low elastic modulus such as an organic material is preferable because cracks do not occur. For example, a liquid epoxy resin is used.

As the stress buffer resin 6, a resin having a low elastic modulus is used in order to buffer the column stress caused by the thermal expansion coefficient of the semiconductor chip and the multilayer wiring board. Furthermore, since the resin is poured between the metal columns at the time of formation, a resin having a lower viscosity is easier to form. For example, a liquid epoxy resin is used.

A third embodiment of the present invention will be described with reference to FIGS.

FIG. 16 is a sectional view of a semiconductor chip used in the semiconductor device according to the present invention. As shown in FIG.
On the semiconductor chip 10, bump-shaped bump electrodes 2 are formed in a predetermined pattern. The bump electrode 2 is made of Sn or P
It is formed using a solder material containing b as a main component. Less than,
Called solder bump 2. The solder bumps 2 of the semiconductor chip 10 are formed by, for example, a plating method, a vapor deposition method, or a screen printing method using a solder paste material. In a region other than the region where the solder bumps 2 are formed on the semiconductor chip 10, a passivation film (not shown) for protecting an active region on the surface of the semiconductor chip 10 is formed.

Next, as shown in FIG.
On a temporary substrate 3 made of a solid metal material having excellent solder wettability such as i, a semiconductor chip 10 having solder bumps 2 is aligned and arranged.

The material of the temporary substrate 3 is, for example, a material in which a Cu plate is subjected to Ni plating or a material in which
u-plated or SUS plate with Cu
Alternatively, it is preferable to use a Ni-plated one.

Next, as shown in FIG.
A heating reflow process is performed in a state where the temporary substrate 3 and the temporary substrate 3 are aligned, and the semiconductor chip 10 and the temporary substrate 3 are joined by the solder bumps 2. At this time, in order to stabilize the soldering, for example, flux is used, or a heating reflow process is performed in an inert gas atmosphere. Flux
In the case where is used, it is preferable to carry out the flux cleaning step in consideration of the process stability and the quality stability of the next step from the viewpoint of ensuring the PKG quality.

Next, as shown in FIG.
In the gap between the solder bump 2 and the temporary substrate 3, a stress buffer resin 4 composed mainly of an organic insulating material is provided.
Is placed. As a means for disposing the insulating material 4, when the insulating material 4 is a liquid resin, for example, the resin is dropped on the side surface of the wafer by potting, and the liquid is formed by utilizing the capillary phenomenon between the solder bumps 2. There is a method of injecting resin. Alternatively, there is a method of disposing a liquid resin by a printing / vacuum defoaming method. When the insulating material 4 is a solid resin, a transfer molding method may be used.

Next, as shown in FIG. 20, the temporary substrate 3 is patterned so that the portion of the temporary substrate 3 on the solder bumps 2 is left. As a patterning method, for example, a photoresist material is coated on the temporary
There is a method of performing a development process and performing wet etching using a photoresist material as a mask. As the etchant, for example, a liquid such as ferric chloride or sulfuric acid + hydrogen peroxide solution can be used. As a patterning method, or
Patterning can be performed by a laser processing method. If the pattern of the solder bumps 2 on the semiconductor chip 10 is very fine, patterning may be performed using a dry etching technique.

As described above, the conductive columns 5 are formed on the solder bumps 2. Conductive column 5 in this embodiment
Is made of a metal material having excellent solder wettability, such as Cu or Ni, and is hereinafter referred to as a metal column 5. The height of the metal column 5 is, for example, 50 μm to 15 μm.
0 μm.

Thereafter, as shown in FIG. 21, a stress buffer resin 6 is disposed around the metal column 5 for the purpose of mechanical protection of the metal column 5.

At this time, when the stress buffer resin 6 is a liquid resin, for example, a spin coating method or a printing method is used. In the case of a solid material, the stress buffering resin 6 can be arranged around the metal column 5 by using, for example, a transfer molding method.

Then, near the top of the metal column 5,
If a very small amount of the stress buffer resin 6 is adhered, a plasma surface treatment technology, a laser processing technology, or a CMP (Che) is used to secure the cleanliness of the top of the metal column.
mechanical Mechanical Polish
g) Using a polishing technique typified by the technique, the cleanliness of the metal column portion is ensured.

Next, as shown in FIG. 22, a ball electrode 7 as an external terminal function is formed on the metal column 5. The ball electrode 7 is made of, for example, a solder material containing Sn or Pb as a main component. This is called a solder ball 7.

[0074]

According to the flip chip type semiconductor device of the present invention, an insulating material layer is previously formed on the passivation film of the semiconductor chip. Therefore, even if a crack occurs in the passivation film on the semiconductor chip due to the heat treatment at the time of repair, it is possible to prevent moisture and fluorine-based ions in the cleaning liquid from entering, thereby preventing corrosion and disconnection of the wiring. As described above, a repairable flip-chip semiconductor device can be provided.

As external terminals on the semiconductor chip,
Since the external terminals including the solder bumps, the metal column portions, and the solder balls are provided, the height as the external terminals can be increased. That is, when the flip-chip type semiconductor device of the present invention is mounted on a multilayer wiring board, the stand-off height between the multilayer wiring board and the semiconductor chip is high, so that a stress buffering effect is brought about and the mounting reliability of the flip-chip type semiconductor device is improved. Is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing steps of a method for manufacturing a flip-chip type semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing steps of a method of manufacturing the flip-chip type semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a step of the method of manufacturing the flip-chip type semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the first embodiment of the present invention.

FIG. 7A is a sectional view showing a step in the method for manufacturing the flip-chip type semiconductor device according to the first embodiment of the present invention. FIG. 2B is a sectional view showing the flip-chip type semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing steps of a method for manufacturing a flip-chip type semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a sectional view showing steps of a method for manufacturing a flip-chip type semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a sectional view showing steps of a method for manufacturing a flip-chip type semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a sectional view showing steps of a method for manufacturing a flip-chip type semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a sectional view showing steps of a method for manufacturing a flip-chip type semiconductor device according to the second embodiment of the present invention.

FIG. 15A is a sectional view showing a step in a method for manufacturing a flip-chip semiconductor device according to the second embodiment of the present invention. FIG. 2B is a sectional view showing a flip-chip type semiconductor device according to a second embodiment of the present invention.

FIG. 16 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the third embodiment of the present invention.

FIG. 17 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the third embodiment of the present invention.

FIG. 18 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the third embodiment of the present invention.

FIG. 20 is a sectional view showing a step of the method of manufacturing the flip-chip type semiconductor device according to the third embodiment of the present invention.

FIG. 21 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the third embodiment of the present invention.

FIG. 22 is a sectional view showing a step of the method for manufacturing the flip-chip type semiconductor device according to the third embodiment of the present invention.

FIG. 23 is a cross-sectional view of a conventional flip-chip type semiconductor device.

FIG. 24 is a diagram illustrating a method for mounting a conventional flip-chip type semiconductor device on a multilayer wiring board.

FIG. 25 is a diagram illustrating a method for repairing a conventional flip-chip type semiconductor device from a multilayer wiring board.

FIG. 26 is a cross-sectional view of a conventional flip-chip type semiconductor device after repair from a multilayer wiring board.

FIG. 27 is a cross-sectional view of another conventional flip-chip type semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Solder bump 3 Temporary substrate 4 Insulating material layer 5 Metal column 6 Stress buffer resin 7 Solder ball 8 Dicing blade 9 Semiconductor chip 10 Semiconductor chip 100 Semiconductor device 101 Semiconductor chip 102 Solder bump 103 Passivation film 104 Multilayer wiring board 105 Repair suction heating tool 106 Solder bump after suction removal 201 Semiconductor chip 202 Bump 204 Multilayer wiring board 207 Underfill resin 208 Pad

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 23/12

Claims (17)

(57) [Claims] A semiconductor chip having a bump electrode; a conductive column provided on the bump electrode; a ball electrode provided on the conductive column; and an external electrode pad to which the ball electrode is connected. And a wiring substrate having the following. 2. The semiconductor device according to claim 1, wherein an insulating material layer is provided between said bump electrodes. 3. The semiconductor device according to claim 2, wherein a stress buffer layer is provided between the conductive columns. 4. The semiconductor device according to claim 2, wherein the surface of the insulating material layer on the semiconductor chip is at substantially the same height as an interface between the bump electrode and the conductive column.
13. The semiconductor device according to claim 1. 5. The insulating material layer is mainly composed of any one of an epoxy resin, a silicon resin, a polyimide resin, a polyolefin resin, a cyanate ester resin, a phenol resin, and a naphthalene resin. 4. The semiconductor device according to claim 2, wherein: 6. The insulating material layer according to claim 2, wherein the insulating material layer is formed of a material having an elastic modulus that does not cause cracking when heated at a temperature at which the ball electrode melts. Semiconductor device. 7. The semiconductor device according to claim 2, wherein said insulating material layer is made of a material having resistance to a chemical containing fluorine-based ions. 8. The semiconductor device according to claim 1, wherein the bump electrode is formed of a material having a higher melting temperature than the ball electrode. 9. The semiconductor device according to claim 1, wherein the conductive column has a height substantially equal to that of the bump electrode. 10. The conductive column is made of Cu or N.
3. The semiconductor device according to claim 1, comprising a metal material such as i. 11. The stress buffer layer is an epoxy resin,
Silicone resin, polyimide resin, polyolefin resin, cyanate ester resin, phenol resin,
4. The semiconductor device according to claim 3, wherein one of the naphthalene-based resins is used as a main component. 12. A step of forming a plurality of bump electrodes on a semiconductor wafer, a step of providing an insulating material layer between the plurality of bump electrodes, a step of forming a conductive column on the bump electrodes, Forming a ball electrode on the conductive column. 13. A method of forming a plurality of bump electrodes on a semiconductor chip, a step of providing an insulating material layer between the plurality of bump electrodes, and a step of forming a conductive column on the bump electrodes. Forming a ball electrode on the conductive column. 14. A step of forming a plurality of bump electrodes on a semiconductor wafer, a step of connecting said semiconductor wafer to a conductive temporary substrate via said bump electrodes, and a step of connecting said semiconductor wafer and said conductive temporary substrate. A step of providing an insulating material layer between the plurality of bump electrodes; a step of patterning the conductive temporary substrate to form a conductive column on the bump electrode; and a step of forming a ball on the conductive column. Forming an electrode. 15. A step of forming a plurality of bump electrodes on a semiconductor chip, a step of connecting said semiconductor chip to a conductive temporary substrate via said bump electrodes, and a step of connecting said semiconductor chip and said conductive temporary substrate. A step of providing an insulating material layer between the plurality of bump electrodes; a step of patterning the conductive temporary substrate to form a conductive column on the bump electrode; and a step of forming a ball on the conductive column. Forming an electrode. 16. The method according to claim 13, further comprising a step of forming a stress buffer layer between the conductive columns. 17. The method for manufacturing a semiconductor device according to claim 13, wherein a Ni-plated Cu plate is used as the conductive temporary substrate.