JP3836449B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device.SetThe present invention relates to a manufacturing method, and in particular, a semiconductor device of a wafer level CSP.SetIt relates to a manufacturing method.
[0002]
[Prior art]
  In recent years, as represented by mobile devices and mobile devices, electronic devices are becoming smaller and lighter, and semiconductor packages are also required to be smaller and lighter.
[0003]
  In order to meet this demand, CSP (Chip Size Package), which is packaged in a size almost equal to that of a semiconductor chip, has appeared in place of conventional packages such as QFP and TSOP, and has been put into practical use.
[0004]
  Currently, the mainstream form of CSP is CSP with face-up structure using wire bond technology, but in recent years, this wire bond type CSP can be further reduced in size and weight, and can be packaged in the same size as the chip size. A product called a wafer level CSP that can manufacture a CSP at a lower cost has appeared.
[0005]
  In this wafer level CSP, an insulating layer, a redistribution layer, and an external electrode are formed on each chip in the state of the semiconductor wafer, instead of individually packaging the chips after separating the chips from the semiconductor wafer as in the conventional CSP. After completing the packaging to complete the packaging, singulation is performed. As a result, a package having the same size as the chip size is possible, and manufacturing is possible at low cost.
[0006]
  An example of the simplest structure of the wafer level CSP is shown in FIG. FIG. 6 is a cross-sectional view showing a schematic configuration of the wafer level CSP. In the wafer level CSP structure shown in the figure, an Al electrode 42 and a first insulating layer 43 made of an inorganic material having an opening in the Al electrode 42 are formed on a semiconductor substrate 41. Further, a second insulating layer 44 having an opening at the Al electrode 42 portion is formed on the first insulating layer 43. On the Al electrode 42 and the first insulating layer 43, for example, a barrier metal layer 45 made of chromium (Cr), titanium (Ti), etc., a base metal layer 46b made of, for example, copper (Cu), and a main conductor A rewiring layer 46 made of the layer 46a is formed. A third insulating layer 48 having an opening exposing a part of the rewiring layer 46 is formed on the rewiring layer 46, and the projecting electrode 49 made of a solder ball serves as an external output terminal in the opening. Is formed.
[0007]
  The wafer level CSP shown in FIG. 6 has a high Si ratio and a low organic material ratio relative to the conventional CSP. Therefore, the difference in linear expansion coefficient between the wafer level CSP and a mounting substrate made of an organic material that is generally used. The reliability after mounting tends to decrease.
[0008]
  Therefore, various methods have been proposed to improve the reliability after mounting the wafer level CSP. For example, there is a method of forming a metal column between the land portion of the rewiring layer and the external output terminal. As a typical method, for example, as seen in a wafer level CSP that has already been commercialized, a metal column is formed by plating such as copper (Cu), or by bump formation using a wire bond. There is a way to do it.
[0009]
  However, in the method of forming a metal column by plating with Cu or the like, it takes a lot of time to form a metal column having a height exceeding 100 μm.
[0010]
  Also, when forming metal pillars with bumps formed by wire bonding, wire bumps are formed one by one over a wide area on the substrate, requiring a lot of time, and controlling the shape of the metal pillars strictly It is difficult to do.
[0011]
  As a method in consideration of these points, for example, as disclosed in Patent Document 1 and Patent Document 2, a metal column is formed by reflowing solder, and then the gap between the solder balls is filled with a filler and polished. Thus, there is a method of forming a metal column made of solder. In this way, by using solder as the material of the metal pillar, it is possible to reflow after mounting the solder balls on the rewiring layer, or by performing reflow after printing the solder paste on the rewiring layer. Each metal column is formed.
[0012]
[Patent Document 1]
  JP 2001-144204 A (publication date: May 25, 2001)
[0013]
[Patent Document 2]
  Japanese Patent Laid-Open No. 9-213830 (Publication date: August 15, 1997)
[0014]
[Problems to be solved by the invention]
  However, when a solder ball is mounted on a rewiring layer having good wettability with solder and reflow is performed, the solder flows out onto the rewiring layer during reflow, and as a result, the shape of the metal column is not stable. In such a case, in order to stabilize the shape of the metal column, an organic insulating material (organic resin) having an opening only in a portion where the metal column is to be formed is formed by patterning to control the spread of the solder. Many. However, when an organic insulating material is left in the semiconductor device after reflow, it is necessary to use an organic insulating material having high reliability. However, such an organic insulating material is generally expensive. If the organic insulating material is left in the semiconductor device, the number of interfaces increases, and as a result, the reliability of the semiconductor device may be reduced due to the occurrence of peeling between the interfaces.
[0015]
  Also, when peeling off after reflow for ball mounting, a normal resist causes a reaction such as curing due to reflow, and it becomes difficult to peel off, so a special resist or peeling method is required There is.
[0016]
  In the current CSP package, the protruding electrodes are mainly formed by solder balls having a diameter of 200 μm to 800 μm or by solder printing. Further, the wafer level CSP is often used in ICs that are desired to be further reduced in size and weight, and it is necessary to form a protruding electrode smaller than the current state, that is, a metal column having a diameter of 200 μm to 500 μm and a protruding electrode. In addition, the rewiring layer and the metal pillar, and the metal pillar and the protruding electrode should be connected so that the joint will not crack and break even if it is affected by temperature changes after the package is mounted on the board, bending of the packaging, or impact. It is desirable to increase the bonding strength. Therefore, it is conceivable to join metal columns with a conductive adhesive. However, it is difficult to mount tens of thousands of metal columns at predetermined positions, and joining with a conductive adhesive is also strong. There is a problem that it tends to be low.
[0017]
  In the wafer level CSP, since usually one semiconductor substrate has tens of thousands of terminals, the workability is important in the metal column forming method. Furthermore, since the external output terminal is formed at one end of the metal column, the reliability of the semiconductor device is reduced if the size and shape are not uniform.
[0018]
  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a semiconductor device having a metal column having a uniform size and shape and having high reliability even after mounting on the substrate, and such a semiconductor. An object is to provide a method for manufacturing a device at low cost.
[0019]
[Means for Solving the Problems]
  Main departureIn order to solve the above-described problems, a method for manufacturing a semiconductor device includes a step of forming an insulating layer in a region other than a region where an electrode pad is formed on a semiconductor substrate, and an electrical connection to the electrode pad. Including a step of forming a conductor layer, a step of forming a metal layer other than the metal column forming portion, and a step of forming a metal column in the metal column forming portion of at least the metal column side surface of the conductor layer. It is characterized by.
[0020]
  In the present invention, the “metal column forming portion” refers to a region where the metal column is formed on the metal column side surface of the conductor layer.
[0021]
  According to said structure, when forming a metal pillar in a metal pillar formation part by forming a metal layer on conductor layers other than the said metal pillar formation part, the material for comprising a metal pillar is a conductor layer. It will not flow up. Thereby, metal pillars with uniform sizes and shapes can be formed. Moreover, according to said structure, it can prevent that the material for comprising a metal pillar flows out to a conductor layer, without using an expensive organic insulating material. Therefore, the semiconductor device can be manufactured at low cost.
[0022]
  The method for manufacturing a semiconductor device of the present invention further includes a step of forming a barrier metal layer and a base metal layer between the insulating layer and the conductor layer.It is characterized by.
[0023]
  According to said structure, the diffusion between the metal of an electrode pad and an insulating layer and a conductor layer can be prevented by forming a barrier metal layer. Moreover, the adhesion between the barrier metal layer and the conductor layer can be enhanced by forming the base metal layer. Therefore, a highly reliable semiconductor device can be manufactured.
[0024]
  In the method for manufacturing a semiconductor device of the present invention, a step of applying a first photosensitive resin on the base metal layer and forming a first photosensitive resist by exposure and development; A step of forming the conductor layer by plating using a photosensitive resist, a step of removing the first photosensitive resist, a second photosensitive resin is applied on the conductor layer, and exposure and development are performed. A step of forming a second photosensitive resist, a step of forming the metal layer by electrolytic plating using the second photosensitive resist, a step of stripping the second photosensitive resist, And removing the barrier metal layer and the base metal layer.
[0025]
  At this time, when an electroless plating method is used as a method for forming the metal layer, a step of removing the barrier metal layer and the base metal layer after forming the conductor layer, and a step of forming a second resist thereafter Preferably, the method includes a step of forming the metal layer and a step of removing the second photosensitive resist.
[0026]
  By setting it as the manufacturing method of the semiconductor device including such an electroless-plating process, a metal layer can be formed in a conductor layer except the metal pillar formation part which formed the resist. Further, by using such a method, after the metal layer is formed, the metal layer is not adversely affected without being touched with the etching solution of the base metal layer and the barrier metal layer, and the metal layer is not melted. Etching is easy because it is not necessary to use an etchant that selectively etches the base metal layer and the barrier metal layer.
[0027]
  Moreover, since the metal layer also functions as a protective layer against migration of the conductor layer, for example, there is also an advantage that the metal layer can be reliably formed on the conductor layer surface.
[0028]
  The method for manufacturing a semiconductor device of the present invention preferably further includes a step of oxidizing the surface of the metal layer after forming the metal layer.
[0029]
  According to the above configuration, in nickel or the like, a natural oxide film is formed on the surface of the metal layer and the wettability with the solder is poor. Therefore, it is possible to manufacture a semiconductor device that is suitably used.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
  [Embodiment 1]
  An embodiment of the present invention will be described below with reference to FIGS.
[0031]
  FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the present embodiment mainly includes a semiconductor substrate 1, an electrode pad 2, a first insulating layer 3, a second insulating layer 4, a barrier metal layer 5, a base metal layer 6b, and A rewiring layer 6 composed of a main conductor layer (conductor layer) 6a, a metal layer 7, a third insulating layer 8, a metal column 9, and a protruding electrode (external electrode) 10 are provided.
[0032]
  The semiconductor substrate 1 is configured by providing a semiconductor element (not shown) on a silicon wafer.
[0033]
  The electrode pad 2 is formed on the semiconductor substrate 1. The electrode pad 2 is not particularly limited in size and shape as long as it is a metal pad, but preferably aluminum (Al), silicon aluminum (AlSi), copper aluminum (AlCu), copper ( Cu).
[0034]
  A first insulating layer 3 (insulating layer) is provided outside the region where the electrical pads 2 are formed on the semiconductor substrate 1. In the present embodiment, the first insulating layer 3 includes an opening 3 a that exposes the electrode pad 2. In the present embodiment, the first insulating layer 3 is not particularly limited as long as it is made of an insulating material, but preferably, the first insulating layer 3 is made of an inorganic insulating film. More preferably, it is composed of an inorganic insulating film mainly composed of a silicon oxide film or a nitride film.
[0035]
  Although the film thickness of the 1st insulating layer 3 is not specifically limited, It is preferable to exist in the range of 0.1 micrometer-3 micrometers, and it is more preferable to exist in the range of 0.3 micrometer-1 micrometer. If the thickness of the first insulating layer 3 is less than the above preferable range, there is a possibility that the semiconductor substrate 1 and the main conductor layer 6a cannot be insulated, which is not preferable. Moreover, when the film thickness of the 1st insulating layer 3 exceeds the said preferable range, time is required for manufacture of a semiconductor device, and the curvature of a semiconductor device becomes large and is unpreferable.
[0036]
  Furthermore, a second insulating layer 4 having an opening 4 a for exposing the electrode pad 2 is provided on the first insulating layer 3.
[0037]
  In the present embodiment, the second insulating layer 4 is not particularly limited as long as it is made of an insulating material, but preferably, the second insulating layer 4 has low hygroscopicity and is chemically stable. Specifically, it is composed of, for example, a photosensitive imide resin (for example, polyimide) or a PBO resin (for example, polybenzoxazole). That is. Further, when it is necessary to prevent crosstalk of the semiconductor element portion included in the semiconductor substrate 1, an organic insulating material such as BCB (benzocyclobutene) having a low dielectric constant is used as the second insulating layer 4. It is preferable to use it.
[0038]
  Although the film thickness of the 2nd insulating layer 4 is not specifically limited, It is preferable to exist in the range of 0.5 micrometer-35 micrometers, and it is more preferable to exist in the range of 3 micrometers-10 micrometers. If the thickness of the second insulating layer 4 is less than the above preferable range, there is a possibility that the semiconductor substrate 1 and the main conductor layer 6a cannot be insulated, which is not preferable. In addition, when the thickness of the second insulating layer 4 exceeds the above preferable range, there is no particular problem, but it is not preferable because the warp of the semiconductor device increases.
[0039]
  Furthermore, in the present embodiment, the reliability of the semiconductor device is not lowered by the diffusion between the electrode pad 2 and the main conductor layer 6a and the reaction between the second insulating layer 4 and the main conductor layer 6a. Further, a barrier metal layer 5 and a base metal layer 6b are provided.
[0040]
  The barrier metal layer 5 is not particularly limited as long as it is a layer made of a metal, but is preferably made of a metal having good adhesion to the second insulating layer 4, and as such a substance Specific examples include copper (Cu), titanium (Ti), chromium (Cr), tungsten (W), and alloys thereof. Moreover, the film thickness of the barrier metal layer 5 is not particularly limited, and may be appropriately set as necessary, but is preferably in the range of 0.01 μm to 1 μm, preferably 0.1 μm to 0. More preferably, it is within the range of 3 μm. The barrier metal layer 5 having such a thickness may be formed by sputtering, for example.
[0041]
  Furthermore, in the present embodiment, a base metal layer 6b is provided on the barrier metal layer 5 in order to improve the adhesion between the barrier metal layer 5 and the main conductor layer 6a. The base metal layer 6b is not particularly limited as long as it is made of metal, but preferably, the same metal as that constituting the main conductor layer 6a is used. The film thickness of the base metal layer 6b is not particularly limited and may be appropriately set as necessary, but is preferably in the range of 0.01 μm to 3 μm, preferably 0.15 μm to 0. More preferably, it is within the range of 60 μm. The base metal layer 6b having such a thickness may be formed by, for example, a sputtering method.
[0042]
  In the present embodiment, the main conductor layer 6a is provided on the base metal layer 6b and is electrically connected to the electrode pad 2 by projecting one end from the opening 4a and the opening 3a.
[0043]
  As a substance constituting the main conductor layer 6a, for example, a substance having a low electrical resistance is preferably used. Specifically, for example, Cu or the like that can easily form a film thickness of several μm by plating or the like is used. Although these are preferable, these are not particularly limited, and may be set as appropriate.
[0044]
  In the present embodiment, the film thickness of the main conductor layer 6a is not particularly limited, and may be set as appropriate. However, the film thickness of the main conductor layer 6a is in the range of 1 μm to 10 μm. It is preferable to be within, and it is more preferable to be within the range of 5 μm to 10 μm. If the film thickness of the main conductor layer 6a is less than the above preferable range, the electrical resistance may decrease or delay the signal voltage, which is not preferable. On the other hand, if the thickness of the main conductor layer 6 exceeds the above preferable range, a thick insulating film is required, warping is increased, and a long time is required for plating formation, which is not preferable.
[0045]
  And the metal layer is provided on the area | region which is not in contact with the metal pillar 9 among the metal pillar side surfaces of the main conductor layer 6a. In the present embodiment, the metal layer 7 is provided with an opening 7a that exposes a metal column forming portion (not shown) provided in the main conductor layer 6a. The metal layer 7 is provided so that a material for forming the metal column 9 does not flow into the main conductor layer 6a. In the present embodiment, as shown in FIG. 1, the metal layer 7 covers the surface portion of the main conductor layer 6a and the side portions of the laminated portion of the main conductor layer 6a and the base metal layer 6b.
[0046]
  In the present embodiment, although not particularly limited, the metal layer 7 is preferably composed of a metal (or metal compound) having low wettability with solder. Specifically, for example, nickel (Ni ), Chromium (Cr), aluminum (Al), or a metal containing these as a main component, and in particular, Ni having an oxide film formed on the surface thereof is preferable. Thereby, the metal pillar 9 composed of solder is formed by performing reflow after mounting the solder balls on the main conductor layer 6a or by performing reflow after printing the solder paste on the main conductor layer 6a. Can do.
[0047]
  The film thickness of the metal layer 7 is not particularly limited and may be appropriately set as necessary, but is preferably in the range of 0.1 μm to 5 μm, and is preferably in the range of 1 μm to 3 μm. It is more preferable. If the thickness of the metal layer 7 is less than the above preferable range, low wettability may not be secured, which is not preferable. Further, if the thickness of the metal layer 7 exceeds the above preferable range, problems such as strong wiring stress and peeling from the conductive layer may occur.
[0048]
  A metal column 9 is formed in the metal column forming portion of the main conductor layer 6a exposed through the opening 7a. The metal pillar 9 is provided to disperse and relieve stress generated when the semiconductor device of the present embodiment is mounted on a substrate.
[0049]
  In the present embodiment, the metal pillar 9 is preferably made of solder. Thereby, the height of the metal column 9 can be easily prepared, and the bonding strength between the main conductor layer 6a and the metal column 9 can be increased. The solder is not particularly limited. For example, Sn / Pb eutectic solder or lead-free solder typified by Sn / Ag / Cu, which is an environmentally friendly material, and particularly has a high melting point of 260 ° C. or higher. Solder or the like may be used. When the bump electrode 10 is made of solder, it is preferable that the melting point of the solder constituting the metal column 9 is higher than the melting point of the solder constituting the bump electrode 10. As a result, the metal pillar 9 can be prevented from melting when the protruding electrode 10 is formed.
[0050]
  In the present embodiment, on the second insulating layer 4 and the metal layer 7, the third insulating layer 8 provided with the opening 8 a exposing the metal column 9 is provided. The side surface is covered with the third insulating layer 8.
[0051]
  The third insulating layer 8 has good adhesion to the second insulating layer 4 and the metal layer 7, and can be formed to have a thickness equal to or higher than the height of the metal column 9, specifically, 100 μm or more. It is preferably composed of a material having excellent mechanical polishing properties and a low thermal expansion coefficient and low elastic modulus, specifically, a resin such as an epoxy resin, a phenol resin, and an acid anhydride resin. The third insulating layer 8 may contain a filler made of silica in the resin.
[0052]
  A protruding electrode 10 is formed on the metal column 9 exposed from the opening 8a. In the present embodiment, the protruding electrode 10 is preferably composed of solder. By configuring the metal column 9 and the protruding electrode 10 from solder, the bonding strength between the metal column 9 and the protruding electrode 10 can be increased. The solder constituting the protruding electrode 10 is not particularly limited. For example, Sn / Pb eutectic solder or lead-free solder typified by Sn / Ag / Cu which is an environment-friendly material can be used.
[0053]
  Next, an example of the manufacturing process of the semiconductor device shown in FIG. 1 will be described with reference to FIGS. In addition, the manufacturing method of the semiconductor device concerning this invention is not limited to this.
[0054]
  2 and 3 are diagrams schematically showing a manufacturing process of the semiconductor device according to the present embodiment.
[0055]
  In the method for manufacturing a semiconductor device according to the present embodiment, first, as shown in FIG. 2A, an electrode pad 2 is formed on a semiconductor substrate 1 having a semiconductor element (not shown). In addition to the region where the electrode pad 2 is formed on the semiconductor substrate 1, the first insulating layer 3 is formed.
[0056]
  Next, a photosensitive resin (for example, a photosensitive polyimide resin or PBO resin) is applied on the first insulating layer 3 by a spin coating method, and then pre-baking is performed. Thereafter, the pattern shape is exposed using an aligner, a stepper, etc., the photosensitive resin in this portion is exposed so as to have an opening in the electrode pad 2, the solution is made soluble in a developer, and is removed by development. Thereafter, a temperature of 200 ° C. to 350 ° C. is applied to the photosensitive resin on the first insulating layer 3 to form the second insulating layer 4 as shown in FIG.
[0057]
  Next, as shown in FIG. 2C, Ti having a film thickness of, for example, 0.1 μm to 0.3 μm is formed as a barrier metal layer 5 on the electrode pad 2 and the second insulating layer 4 by sputtering. . On the barrier metal layer 5, for example, Cu having a thickness of 0.15 μm to 0.60 μm is formed by sputtering as the base metal layer 6 b.
[0058]
  Next, the main conductor layer 6a electrically connected to the electrode pad 2 is formed. In this Embodiment, the formation method of the main conductor layer 6a is not specifically limited, For example, the main conductor layer 6a can be formed efficiently by implementing the following processes.
[0059]
  Specifically, for example, as shown in FIG. 2 (d), a first photosensitive resin is applied on the base metal layer 6b, and the first conductor portion 6a is removed from the portion where the main conductor layer 6a is formed by exposure and development. The photosensitive resist 11a is formed. After the formation of the first photosensitive resist 11a, temporary curing is performed (FIG. 2E).
[0060]
  Then, for example, the main conductor layer 6a is formed using the first photosensitive resist 11a such as PMER manufactured by Tokyo Ohka Kogyo Co., Ltd. Specifically, as shown in FIG. 2 (f), by performing electrolytic plating on the opening of the first photosensitive resist 11a using a copper plating solution made of, for example, copper sulfate, the lead made of Cu is made. The body layer 6a is formed. After forming the main conductor layer 6a, the photosensitive resist 11a is removed (FIG. 2G).
[0061]
  Next, the metal layer 7 is formed on the main conductor layer 6a other than the metal column forming portion on the metal column side surface of the main conductor layer 6a. In this Embodiment, the formation method of the metal layer 7 is not specifically limited, For example, the metal layer 7 can be formed efficiently by implementing the following processes.
[0062]
  Specifically, for example, the second conductive resin is applied on the main conductor layer 6a, and the main conductor excluding a part of the main conductor layer 6a exposed to form the metal pillar 9 by exposure and development. The second photosensitive resist 11b is formed so that the upper surface or only the surface of the layer 6a is exposed. Thereafter, temporary curing is performed (FIG. 2 (h)).
[0063]
  Then, the metal layer 7 is formed using the second photosensitive resist 11b. Specifically, a Ni layer having a film thickness of 1 μm to 3 μm is formed in the opening of the second photosensitive resist 11b by, for example, electrolytic plating. Thereafter, the second photosensitive resist 11b is removed with a stripping solution (FIG. 3 (i)).
[0064]
  Next, for example, an etching solution containing ammonium persulfate as a main component and a hydrogen peroxide solution or inorganic ammonia as a main component, and preferably a surface protective layer is temporarily formed on the main conductor layer 6a to protect it from the etching solution. Etching is performed on the underlying metal layer 6b in the portion other than the rewiring layer portion, that is, the portion where the metal layer 7 is not formed, and the barrier metal layer 5 located under this portion by using an etching solution containing an additive having a role. It is removed (FIG. 3 (j)).
[0065]
  Next, the metal pillar 9 is formed in the metal pillar formation part of the main conductor layer 6a. In this Embodiment, the formation method of the metal pillar 9 is not specifically limited, For example, it can form as follows.
[0066]
  Specifically, for example, as shown in FIG. 3 (k), the metal pillar 9 is formed by mounting a solder ball on a portion where the main conductor layer 6a is exposed or performing solder printing and reflowing. Here, if the metal layer 7 is Ni, a natural oxide film is formed on the surface of the metal layer 7. Therefore, the difference in wettability between the main conductor layer 6 a and the metal layer 7 is used to obtain the main conductor layer. The metal pillar 9 can be formed without solder flowing other than the exposed portion 6a. Thus, by utilizing the low wettability of the metal layer 7 with the solder, the metal pillar 9 having a uniform size and shape can be formed. At this time, for example, if high-temperature solder consisting of Sn: 95% and Sn: 5% or solder having a high melting point of 260 ° C. or higher is reflowed, the metal column will not melt in the subsequent reflow process, and the wire breaks due to deformation. Thus, a highly reliable semiconductor device can be formed without degrading the reliability.
[0067]
  As described above, it is desirable that the metal column 9 not be melted when the protruding electrode 10 is formed. However, if reliability can be ensured, solder that is the same as the protruding electrode 10 or does not have a high melting point is used. Also good.
[0068]
  Thereafter, as shown in FIG. 3L, a third insulating layer 8 made of, for example, silica filler and acid anhydride resin is formed by printing so as to cover the metal pillar 9.
[0069]
  Thereafter, as shown in FIG. 3M, the third insulating layer 8 is polished by mechanical polishing, CMP (Chemical Mechanical Polish), or the like until the surface of the metal column 9 is exposed.
[0070]
  Next, a solder ball is mounted on the exposed metal pillar 9, or Sn / Pb eutectic solder or Sn / Ag / Cu solder is printed and reflowed in a nitrogen atmosphere, as shown in FIG. 3 (n). The protruding electrode 10 is formed.
[0071]
  According to the present embodiment, when the reflow is performed, the first photosensitive resist 11a and the second photosensitive resist 11b described above are removed. Therefore, according to the present embodiment, there is no need to consider problems such as hardening and embrittlement of the first photosensitive resist 11a and the second photosensitive resist 11b due to heat of reflow. Therefore, a semiconductor device can be manufactured using a general inexpensive photosensitive resin as the first photosensitive resist 11a and the second photosensitive resist 11b.
[0072]
  In addition, the manufacturing method of the semiconductor device of this invention is not restricted to the structure mentioned above, For example, after forming the metal layer 7 shown in FIG. On the other hand, the surface of the metal layer 7 is intentionally oxidized by heat treatment in the range of 150 ° C. to 350 ° C. or surface treatment with a chemical solution, etc., whereby a metal film (oxide film) is formed on the surface of the metal layer 7. May be formed. An oxide film is also formed on the main conductor layer 6a where the metal layer 7 is not formed, that is, the metal forming portion, due to the oxidation of the surface of the metal layer 7. This oxide film is, for example, the above-described base metal layer 6b. An etching solution used for removing the metal layer may be selectively removed simultaneously with the removal of the base metal layer 6b. Thereby, a layer with poor wettability can be formed on the metal layer 7. As described above, if the surface of the metal layer 7 is oxidized, the metal film (oxide film) formed on the surface of the metal layer 7 has a poor wettability with solder as compared with the natural oxide film, and the spread of the solder can be controlled. . The step of oxidizing the surface of the metal layer 7 can also be performed after the main conductor layer 6a is formed and after the barrier metal layer 5 and the base metal layer 6b are removed.
[0073]
  [Embodiment 2]
  The following will describe another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 are given the same reference numerals, and explanation thereof is omitted. FIGS. 4 and 5 are diagrams showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.
[0074]
  First, as shown in FIG. 4A, an electrode pad 2 is formed on a semiconductor substrate 1 having a semiconductor element (not shown). Then, the first insulating layer 3 is formed in a region other than the region where the electrode pad 2 is formed on the semiconductor substrate 1.
[0075]
  Next, a photosensitive resin (for example, a photosensitive polyimide resin or PBO resin) is applied on the first insulating layer 3 by a spin coating method, and then pre-baking is performed. Thereafter, the pattern shape is exposed using an aligner, a stepper, etc., the photosensitive resin in this portion is exposed so as to have an opening in the electrode pad 2, the solution is made soluble in a developer, and is removed by development. Then, the 2nd insulating layer 4 is formed as shown in FIG.4 (b) by applying the temperature of 250 to 350 degreeC to the photosensitive resin on the 1st insulating layer 3. Then, as shown in FIG.
[0076]
  Next, as shown in FIG. 4C, Ti having a thickness of, for example, 0.15 μm to 0.30 μm is formed by sputtering as the barrier metal layer 5 on the electrode pad 2 and the second insulating layer 4. . On the barrier metal layer 5, for example, Cu having a thickness of 0.15 μm to 0.60 μm is formed by sputtering as the base metal layer 6 b.
[0077]
  Next, as shown in FIG. 4 (d), a first photosensitive resin is applied on the base metal layer 6b, and the first photosensitive resin is formed on the portion excluding the portion where the main conductor layer 6a is formed by exposure and development. The resist 11a is formed. After the formation of the first photosensitive resist 11a, temporary curing is performed (FIG. 4E).
[0078]
  Then, the main conductor layer 6a is formed using the first photosensitive resist 11a. Specifically, the main conductor layer 6a made of Cu is formed in the opening of the first photosensitive resist 11a by, for example, electrolytic plating using a copper plating solution made of copper sulfate. After forming the main conductor layer 6a, the first photosensitive resist 11a is removed (FIG. 4F).
[0079]
  Next, for example, an etching solution containing ammonium persulfate as a main component and an etching solution containing hydrogen peroxide solution or inorganic ammonia as a main component and preferably having an additive that does not affect the main conductor layer 6a are used. Then, the base metal layer 6b where the main conductor layer 6a is not formed and the barrier metal layer 5 located under this part are removed by etching (FIG. 4G).
[0080]
  Next, as shown in FIG. 4H, a second photosensitive resin is applied onto the main conductor layer 6a, and the main conductor layer 6a exposed to form the metal pillar 9 by exposure and development. The second photosensitive resist 11b is formed so that only the upper surface or only the surface of the main conductor layer 6a excluding a part is exposed. Thereafter, temporary curing is performed.
[0081]
  Next, as shown in FIG. 5 (i), a metal different from the metal constituting the main conductor layer 6 a on the main conductor layer 6 a, for example, by electroless plating, preferably wettability to solder. A metal layer 7 made of a low metal or a metal that forms a metal film on the surface, such as Ni, is formed. Thereafter, the second photosensitive resist 11b is removed (FIG. 5 (j)). This method also has an advantage that the metal layer can be reliably formed on the surface of the conductor layer because it also serves as a protective layer against migration of the conductor layer.
[0082]
  And preferably, the surface of the metal layer 7 is oxidized by subjecting the surface of the metal layer 7 to heat treatment or surface treatment with a chemical solution in the atmosphere before the removal of the second photosensitive resist 11b. A metal film is formed on. In this case, the conductor layer 6 is protected by the second photosensitive resist and can form a metal column made of solder without being oxidized and post-processed. Here, when the second photosensitive resist 11b cannot withstand the heating or chemical treatment, after the second photosensitive resist 11b is removed, the above-mentioned treatment is performed on the metal layer 7 to form a metal film (oxide film). After that, only the metal film formed on the main conductor layer 6a is selectively removed with a chemical solution using the difference in chemical resistance between the metal films formed on the metal layer 7 and the main conductor layer 6a.
[0083]
  Then, as shown in FIG. 5 (k), a metal ball 9 is formed by mounting a solder ball on a portion where the main conductor layer 6a is exposed or performing solder printing and reflowing.
[0084]
  Thereafter, as shown in FIG. 5L, a third insulating layer 8 made of, for example, silica filler and acid anhydride resin is formed by printing so as to cover the metal column 9.
[0085]
  Next, as shown in FIG. 5M, the third insulating layer 8 is polished by mechanical polishing, CMP (Chemical Mechanical Polish), or the like until the surface of the metal column 9 is exposed.
[0086]
  Next, as shown in FIG. 5 (n), solder balls are mounted on the exposed metal pillars 9, or Sn / Pb eutectic solder or Sn / Ag / Cu solder is printed and reflowed in a nitrogen atmosphere. Thus, the protruding electrode 10 is formed.
[0087]
  In order to solve the above problems, a semiconductor device of the present invention has an electrode pad formed on a semiconductor substrate, an insulating layer provided in a region other than the region where the electrode pad is formed on the semiconductor substrate, Of the conductor layer electrically connected to the electrode pad, a metal column that electrically connects a part of the surface of the conductor layer and an external electrode, and the metal column-side surface of the conductor layer, the metal And a metal layer provided on a region not in contact with the column.
[0088]
In the present invention, the “metal column side surface” refers to the surface of the conductor layer on the side where the metal column is provided, and more specifically, is not in contact with the insulating layer or the metal pad. An area.
[0089]
  According to the above configuration, since the metal layer having poor wettability with the metal column material is formed on the conductor layer other than the region where the metal column and the conductor layer are in contact with each other, the material constituting the metal column is a conductor. It does not flow out into the layers, and the size and shape of the metal pillars are uniform. Moreover, even if it does not use an organic insulating material (organic resin), it can prevent that the material which comprises a metal pillar flows out to a conductor layer. According to this, since the organic resin can be reduced and the resin interface in the semiconductor device is reduced, it is possible to prevent a decrease in the reliability of the semiconductor device due to occurrence of peeling between the interfaces. In addition, since the stress generated when the semiconductor device is mounted on the substrate is dispersed and relaxed by the metal pillar provided in the semiconductor device, the metal layer is not cracked. Therefore, a semiconductor device having high reliability even after mounting on the substrate can be provided.
[0090]
  In the semiconductor device of the present invention, it is preferable that the metal column and the protruding electrode are made of solder.
[0091]
  If the metal column is composed of solder, the height of the metal column can be easily adjusted, and the bonding strength with the conductor layer can be increased. Furthermore, if the protruding electrode is made of solder, the bonding strength between the metal column and the protruding electrode can be increased. Therefore, according to the above configuration, it is possible to provide a semiconductor device with improved reliability by increasing the bonding strength between the conductor layer and the metal column and between the metal column and the protruding electrode.
[0092]
  At this time, it is preferable that the melting point of the solder constituting the metal column is higher than the melting point of the solder constituting the protruding electrode.
[0093]
  According to this, the metal column does not melt when the protruding electrode is formed. Therefore, it is possible to provide a highly reliable semiconductor device that is not deformed by melting when the protruding electrode is formed.
[0094]
  Moreover, it is preferable that the said metal layer consists of nickel, aluminum, chromium, or the metal which has these as a main component.
[0095]
  Nickel, aluminum, chromium, or a metal containing these as a main component is a substance having poor wettability with solder or a substance having a surface film such as an oxide film. Therefore, if the metal layer is made of such a material, when the metal column is formed of solder, the solder does not spread outside the region where the metal column and the conductor layer are in contact with each other. A semiconductor device with improved uniformity can be provided.
[0096]
  In the semiconductor device of the present invention, it is preferable that a barrier metal layer and a base metal layer are provided between the insulating layer and the conductor layer.
[0097]
  According to said structure, the fall of the reliability by the reaction between an insulating layer and a conductor layer is prevented by a barrier metal layer. Further, the adhesion between the barrier metal layer and the conductor layer can be enhanced by the base metal layer. Therefore, a semiconductor device with further improved reliability can be provided.
[0098]
  The conductor layer is preferably made of copper.
[0099]
  By using a conductor layer made of copper with low electrical resistance, electrical signals can be efficiently transmitted between the electrical pads and the protruding electrodes. Further, if copper is used, a conductor layer having a thickness of several μm can be easily formed by plating, for example.
[0100]
【The invention's effect】
  Main departureAs described above, the method for manufacturing a semiconductor device includes a step of forming an insulating layer in a region other than the region where the electrode pad is formed on the semiconductor substrate, and a conductive layer electrically connected to the electrode pad. And a step of forming a metal layer on the metal column side surface of the conductor layer other than the metal column forming portion, and a step of forming a metal column on the metal column forming portion.
[0101]
  Therefore, a metal column having a uniform size and shape can be formed. Moreover, according to this, it can prevent that the material which comprises a metal pillar flows out to a conductor layer, without using an expensive organic insulating material. Therefore, the semiconductor device can be manufactured at a low cost.
[0102]
  The semiconductor device manufacturing method of the present invention further includes a step of forming a barrier metal layer and a base metal layer between the electrode pad and insulating layer and the conductor layer.Configuration.
[0103]
  Thereby, there is an effect that it is possible to manufacture a semiconductor device whose reliability is not lowered by reaction / diffusion.
[0104]
  In the method for manufacturing a semiconductor device of the present invention, a step of applying a first photosensitive resin on the base metal layer and forming a first photosensitive resist by exposure and development; A step of forming the conductor layer by plating using a photosensitive resist, a step of applying a second photosensitive resin on the conductor layer, and forming a second photosensitive resist by exposure and development; A structure including a step of forming the metal layer by plating using the second photosensitive resist, and a step of removing the barrier metal layer and the base metal layer.Is.
[0105]
  At this time, for example, after the conductor layer is formed by plating, the barrier metal layer and the base metal layer may be removed.
[0106]
  According to the method for manufacturing a semiconductor device of the present invention, by including such a step, there is an effect that the metal layer can be efficiently formed.
[0107]
  The method for manufacturing a semiconductor device of the present invention may further include a step of oxidizing the surface of the metal layer after forming the metal layer.
[0108]
  Thereby, the metal film formed on the surface of the metal layer can control the spread of the solder more reliably, and it is possible to produce a semiconductor device that is suitably used.
[0109]
  As described above, the semiconductor device of the present invention includes an electrode pad formed on a semiconductor substrate, an insulating layer provided in a region other than the region where the electrode pad is formed on the semiconductor substrate, and the electrode pad. A conductive layer that is electrically connected; a metal column that electrically connects a part of the surface of the conductor layer to an external electrode; and a metal column side surface of the conductor layer that is in contact with the metal column. And a metal layer provided on a non-existing region.
[0110]
  Therefore, by providing the metal layer, it is possible to provide a semiconductor device in which the size and shape of the metal pillars are uniform. In addition, since the stress generated when the semiconductor device is mounted on the substrate is dispersed and relaxed by the metal pillar provided in the semiconductor device, the metal layer is not cracked. Therefore, it is possible to provide a semiconductor device having high reliability even after mounting on the substrate.
[0111]
  As described above, the semiconductor device of the present invention has a configuration in which the metal column and the protruding electrode are made of solder.
[0112]
  Therefore, by increasing the bonding strength between the conductor layer and the metal column and between the metal column and the protruding electrode, there is an effect that a semiconductor device with improved reliability can be provided.
[0113]
  In the semiconductor device of the present invention, as described above, the melting point of the solder constituting the metal column is higher than the melting point of the solder constituting the protruding electrode.
[0114]
  Therefore, there is an effect that it is possible to provide a highly reliable semiconductor device without deformation of the metal column made of solder at the time of forming the protruding electrode.
[0115]
  In the semiconductor device of the present invention, as described above, the metal layer is made of nickel, chromium, aluminum, or a metal containing these as a main component.
[0116]
  Therefore, it is possible to provide a semiconductor device in which a surface layer with low wettability of solder can be formed and the uniformity of the shape and size of the metal pillar can be improved.
[0117]
  The semiconductor device of the present invention has a configuration in which a barrier metal layer and a base metal layer are provided between the insulating layer and the conductor layer.
[0118]
  Therefore, there is an effect that a semiconductor device with further improved reliability can be provided.
[0119]
  In the semiconductor device of the present invention, the conductor layer is made of copper.
[0120]
  Therefore, it is possible to provide a semiconductor device with low signal loss and low signal resistance and good signal transmission.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a drawing schematically showing a manufacturing process of the method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 3 is a drawing schematically showing manufacturing steps of the method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 4 is a diagram schematically showing a manufacturing process of a method of manufacturing a semiconductor device according to another embodiment of the present invention.
FIG. 5 is a drawing schematically showing manufacturing steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a schematic configuration of a conventional wafer level CSP.
[Explanation of symbols]
  1 Semiconductor substrate
  2 electrode pads
  3 First insulating layer
  3a opening
  4 Second insulating layer
  4a opening
  5 Barrier metal layer
  6a Main conductor layer (conductor layer)
  6b Underlying metal layer
  7 Metal layer
  8 Third insulating layer
  9 Metal pillar
  10 Projection electrode (external electrode)

Claims (3)

Forming an insulating layer in a region other than the region where the electrode pads on the semiconductor substrate are formed;
Forming a barrier metal layer and a base metal layer on the electrode pad and the insulating layer;
Applying a first photosensitive resin on the base metal layer and forming a first photosensitive resist by exposure and development;
Using the first photosensitive resist to form a conductive layer electrically connected to the electrode pad through the barrier metal layer and the base metal layer by plating;
Applying a second photosensitive resin to at least the metal column forming portion on the conductor layer, and forming a second photosensitive resist by exposure and development;
Using the second photosensitive resist, forming a metal layer by electrolytic plating on a portion other than the metal column forming portion on the conductor layer;
Removing the barrier metal layer and the base metal layer after forming the metal layer;
Forming a metal column in the metal column forming portion on the conductor layer. Forming an insulating layer in a region other than the region where the electrode pads on the semiconductor substrate are formed;
Forming a barrier metal layer and a base metal layer on the electrode pad and the insulating layer;
Applying a first photosensitive resin on the base metal layer and forming a first photosensitive resist by exposure and development;
Using the first photosensitive resist to form a conductive layer electrically connected to the electrode pad through the barrier metal layer and the base metal layer by plating;
Removing the barrier metal layer and the base metal layer in a portion where the conductor layer is not formed;
Applying a second photosensitive resin to at least the metal column forming portion on the conductor layer, and forming a second photosensitive resist by exposure and development;
Using the second photosensitive resist, a step of forming the electroless plating metallic layer on a portion other than the metal column forming portion on the conductive layer,
Forming a metal column in the metal column forming portion on the conductor layer. The method for manufacturing a semiconductor device according to claim 1 , further comprising a step of oxidizing the surface of the metal layer at least before the step of forming the metal pillar .

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