JP2005064228A - Electronic component and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component that is excellent in weather resistance and can be reduced in thickness, and to provide a method of manufacturing the component. <P>SOLUTION: A semiconductor device 10 is provided with a structure constituted by successively laminating an insulating layer 3, a conductive layer 4, and a sealing layer 5 on one surface 1a of a semiconductor substrate 1 in this order; and solder bumps 7 formed on electrode pads 6. In the device, tops 7a of the solder bumps 7 have flat surfaces, and a protective layer 8 is provided over the whole surface of the structure on which the solder bumps 8 are formed so that the flat surfaces of the bumps 7 are exposed. Heights d<SB>1</SB>of the solder bumps 7 and the thickness d<SB>2</SB>of the semiconductor substrate 1 are adjusted to be d<SB>1</SB>≥d<SB>2</SB>. The method of manufacturing the electronic component includes a step A of forming the solder bumps 7 on the electrode pads 6, a step B of forming the protective layer 8, and a step C of grinding the surface of the protective layer 8 so that the tops 7a of the solder bumps 7 are exposed and have the flat surfaces. The method also includes a step D of back-grinding the other surface of the semiconductor substrate 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, an electronic component that can be electrically connected between substrates through solder bumps, represented by a flip chip, which is a mounting method in which an LSI chip is turned over and bonded to a circuit board, and a manufacturing method thereof. Is.

  Conventionally, as a semiconductor device structure used in an electronic component, for example, in a package in which a semiconductor chip is sealed with a resin (so-called Dual Inline Package or Quad Flat Package), a peripheral terminal arrangement type in which metal lead wires are arranged on the side surface around the resin package Was the mainstream.

  On the other hand, as a semiconductor device structure that has been rapidly widespread in recent years, for example, a CSP (Chip Size / Scale Package) is called a so-called ball grid array (Ball) in which electrodes are arranged in a plane on a flat surface of a package. The Grid Array (hereinafter abbreviated as “BGA”) has made it possible to mount a semiconductor chip having the same number of electrode terminals and having the same projected area on an electronic circuit board with a smaller area than the conventional one. There is a package structure.

In a BGA type semiconductor device, a so-called chip scale package (CSP), in which the area of the package is almost equal to the area of the semiconductor chip, was developed together with the above-described BGA electrode arrangement structure to reduce the size and weight of electronic devices. It contributes greatly.
In the chip scale package, a silicon wafer on which a circuit is formed is cut, a package process is individually performed on each semiconductor chip, and a package is completed.

 On the other hand, in a manufacturing method generally called “wafer level CSP”, an insulating layer, a rewiring layer, a sealing layer, and the like are formed on this silicon wafer, and solder bumps are formed. Then, by cutting the wafer into a predetermined chip size in the final process, a semiconductor chip having a package structure can be obtained. Since these circuits are stacked on the entire surface of the wafer and the wafer is diced in the final process, the size of the cut chip itself becomes a packaged semiconductor chip, which has a minimum projected area with respect to the mounting substrate. Can be obtained.

FIG. 8 is a schematic cross-sectional view showing the structure of a conventional semiconductor device.
The semiconductor device 100 includes a semiconductor substrate 101, an electrode 102 formed on the surface thereof, an insulating layer 103 provided on the surface of the semiconductor substrate 101, and a conductive wire connected to the electrode 102 and wired on the insulating layer 103. A layer 104, a sealing layer 105 covering the conductive layer 104, an electrode pad 106 in which the conductive layer 104 is exposed on the sealing layer 105, and a solder bump 107 placed on the electrode pad 106. (For example, refer to Patent Document 1).

 In the semiconductor device 100, portions that are not directly involved in connection with a printed circuit board or the like, that is, portions where the solder bumps 107 are not provided on the semiconductor substrate 101 and side surfaces of the solder bumps 106 are exposed. For this reason, there is a problem that the semiconductor device 100 is inferior in weather resistance.

In addition, since the thermal expansion coefficient of a semiconductor device having solder bumps is different from that of a printed circuit board, stress based on the difference in thermal expansion coefficient is concentrated on the terminals of the semiconductor device, resulting in defective products such as defective connections. The reliability of the semiconductor device was lowered.
Therefore, the solder bump used here is required to make the height of the solder bump 107 as high as possible in order to disperse the stress based on the difference in thermal expansion coefficient.

 However, when the height of the solder bump 107 is, for example, 100 μm or more, the unevenness on the surface of the semiconductor device 100 is increased accordingly. For this reason, if the surface protection sheet 110 is pasted on the surface of the semiconductor device 100 in order to perform the back grinding process of the semiconductor substrate 101, the surface of the protection sheet 110 is not flat and cannot be vacuum-adsorbed. .

  As a result, there is a problem that the back grinding process of the semiconductor substrate 101 cannot be performed.

  Further, this type of semiconductor device is still highly demanded for miniaturization of mobile devices typified by mobile phones, and further reduction in thickness of the semiconductor device is required due to the spread of IC cards. In order to meet these requirements, back-grinding of semiconductor chips has been implemented.

In order to reduce the thickness of the semiconductor device, it is considered to perform back grinding of the semiconductor substrate 101 in advance before processing of the wafer level CSP. When such back grinding is performed, the semiconductor substrate 101 may be warped and CSP processing may not be performed. Further, the semiconductor substrate 101 is easily broken, and the possibility that the semiconductor substrate 101 is broken during CSP processing is increased.
Japanese Patent Laid-Open No. 2002-16178

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic component that is excellent in weather resistance and can be thinned and a method for manufacturing the same.

  In order to solve the above-described problems, the present invention provides a structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad that exposes the conductive layer is provided on the sealing layer. And an electronic component including a solder bump placed on the electrode pad, the top of the solder bump opposite to the electrode pad has a flat surface, and the flat surface is exposed. Provided is an electronic component in which a protective layer is provided over the entire surface of the structure on which the solder bumps are placed.

  The present invention includes a structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad that exposes the conductive layer is provided on the sealing layer. In a semiconductor device including a solder bump placed thereon, the entire structure on the surface of the structure on which the solder bump is placed is protected so that the top of the solder bump opposite to the electrode pad is exposed. Provided is an electronic component provided with a layer.

In the electronic component having the above configuration, it is preferable that d ₁ ≧ d ₂ , where d _{1 is} the height of the solder bump and d ₂ is the thickness of the semiconductor substrate.

  According to the present invention, at least the electrode pad is formed using a structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad that exposes the conductive layer is provided on the sealing layer. A solder bump forming step A for forming a solder bump thereon, and a protective layer having a thickness substantially equal to or greater than the height of the solder bump is formed over the entire surface of the structure on which the solder bump is placed. Step B, exposing a top portion of the solder bump opposite to the electrode pad, grinding the surface of the protective layer so that the solder bump has a flat surface, and the other surface of the semiconductor substrate The manufacturing method of the electronic component which performs the process D which back-grind-processes is provided.

According to the present invention, at least the electrode pad is formed using a structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad that exposes the conductive layer is provided on the sealing layer. Step F for forming solder bumps thereon, Step G for forming a protective layer having a thickness substantially equal to or greater than the height of the solder bumps over the entire surface of the structure on which the solder bumps are placed. And the manufacturing method of the electronic component which performs the process H which back-grind-processes the other surface of the said semiconductor substrate sequentially.

  The first electronic component according to the present invention is provided so that the protective layer has the same thickness as the height of the solder bump over the entire area of the sealing layer, and the top of the solder bump is slightly exposed. Thus, the weather resistance of the solder bump is improved, and the electronic component is excellent in long-term reliability.

  In addition, the second electronic component according to the present invention has a configuration in which a protective layer is provided over the entire sealing layer so that the top of the solder bump is slightly exposed. As a result, the electronic components have excellent long-term reliability.

  According to the first method for manufacturing an electronic component according to the present invention, by providing a protective layer so as to have a thickness substantially equal to or higher than the height of the solder bump, and grinding and flattening the surface thereof, An electronic component having excellent weather resistance can be obtained. Further, the structure provided with the solder bumps and the protective layer can be stably fixed without being affected by the shape of the solder bumps, so that the back grinding process of the semiconductor substrate can be performed. As a result, it is possible to manufacture an electronic component in which the thickness of the semiconductor substrate is significantly reduced as compared with the conventional case.

  In addition, according to the second method for manufacturing an electronic component according to the present invention, since the protective layer is provided so that the top of the solder bump is slightly exposed, an electronic component having excellent weather resistance can be obtained. In addition, since the step between the top and the surface of the protective layer is slight, the electronic component can be stably fixed by vacuum-sucking the surface of the protective layer, so that the back grinding process of the semiconductor substrate can be performed. it can.

The present invention will be described in detail below.
FIG. 1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device used in an electronic component of the present invention.
The semiconductor device 10 includes a semiconductor substrate 1, an electrode 2 formed on the surface thereof, an insulating layer 3 provided on the surface of the semiconductor substrate 1, and a conductive wire connected to the electrode 2 and wired on the insulating layer 3. A layer 4, a sealing layer 5 covering the conductive layer 4, an electrode pad 6 in which the conductive layer 4 is exposed on the sealing layer 5, a solder bump 7 placed on the electrode pad 6, and a sealing The protective layer 8 provided on the layer 5 is schematically configured.
In this semiconductor device 10, the protective layer 8 is provided so as to have almost the same thickness as the height of the solder bump 7 over the entire area on the sealing layer 5, and the opposite side of the solder bump 7 from the electrode pad 6. The top portion 7a has a flat surface.

In the semiconductor device 10, d ₁ ≧ d ₂ where d _{1 is} the height of the solder bump 7 and d ₂ is the thickness of the semiconductor substrate 1. From this configuration, the semiconductor device 10 can be obtained for the first time by a manufacturing method described later. As a result, the semiconductor substrate 1 can be made thinner than the solder bump 7 while sufficiently securing the height of the solder bump 7, and as a result, the semiconductor device 10 with a reduced thickness can be obtained. .

Further, specifically, the height d ₁ of the solder bump 7 is preferably 100 μm or more. If the height d ₁ of the solder bump 7 is 100 μm or more, even if a stress based on the difference in thermal expansion coefficient between the semiconductor device 10 and the printed circuit board is generated, the stress is applied to the solder bump 7. Can be dispersed. In addition, sufficient connection strength can be ensured in the connection between the semiconductor device 10 and a printed circuit board.

  Although it does not restrict | limit especially as the semiconductor substrate 1, For example, the board | substrate used for semiconductor devices, such as wafer level CSP which does not use a wiring board (interbother), various semiconductor devices, various electronic devices, etc. is used.

As a material forming the conductive layer 4 (electrode pad 6), a metal having good conductivity such as copper (Cu) is used.
As a material forming the insulating layer 3, for example, a synthetic resin such as photosensitive polyimide, photosensitive epoxy, photosensitive benzocyclobutene (BCB) is used.

As a material for forming the sealing layer 5, for example, a synthetic resin material such as a photosensitive acrylic resin or an epoxy resin is used.
As a material for forming the solder bump 7, a solder used for forming a solder bump or for solder connection in a circuit or between circuits is used.
As a material for forming the protective layer 8, a photosensitive resin made of acrylic resin, silicone resin, or the like, or phenolic resin is used.

  A buffer portion may be provided between the electrode pad 6 and the insulating layer 3 for the purpose of relaxing the force generated when the solder bump 7 is pressed against the electrode pad 6.

  In this semiconductor device 10, the protective layer 8 is provided so as to have the same thickness as the height of the solder bump 7 over the entire area on the sealing layer 5, and on the opposite side of the solder bump 7 from the electrode pad 6. Since only the top portion 7a located at is slightly exposed, the weather resistance of the solder bump 7 is improved, and the semiconductor device 10 is excellent in long-term reliability.

  Further, since the outermost surface of the protective layer 8 and the flat surface of the top portion 7a of the solder bump 7 exist on the same plane, the semiconductor device 10 can absorb the surface of the protective layer 8 by vacuum suction. Since it can be stably fixed without being influenced by the shape, the back grinding process of the semiconductor substrate 1 can be performed.

FIG. 2 is a schematic cross-sectional view showing a second embodiment of a semiconductor device used in the electronic component of the present invention.
The semiconductor device 20 includes a semiconductor substrate 11, an electrode 12 formed on the surface thereof, an insulating layer 13 provided on the surface of the semiconductor substrate 11, and a conductive wire connected to the electrode 12 and wired on the insulating layer 13. Layer 14, sealing layer 15 covering conductive layer 14, electrode pad 16 with conductive layer 14 exposed at sealing layer 15, solder bump 17 placed on electrode pad 16, sealing The protective layer 18 provided on the layer 15 is schematically configured.
In the semiconductor device 20, the protective layer 18 is provided over the entire area of the sealing layer 15 so that the top 17 a of the solder bump 17 on the side opposite to the electrode pad 16 is slightly exposed.

In the semiconductor device 20, d ₁ ≧ d ₂ where d _{1 is} the height of the solder bump 17 and d ₂ is the thickness of the semiconductor substrate 11. From this configuration, the semiconductor device 20 can be obtained for the first time by a manufacturing method described later. As a result, the semiconductor substrate 11 can be made thinner than the solder bumps 17 while ensuring the height of the solder bumps 17 sufficiently, and as a result, the semiconductor device 20 with a reduced thickness can be obtained. .

Further, specifically, the height d ₁ of the solder bump 17 is preferably 100 μm or more. If the height d ₁ of the solder bump 17 is 100 μm or more, even if a stress based on the difference in thermal expansion coefficient between the semiconductor device 20 and the printed circuit board is generated, the stress is applied to the solder bump 17. Can be dispersed. In addition, sufficient connection strength can be ensured in the connection between the semiconductor device 20 and the printed circuit board.

  The semiconductor substrate 11 is not particularly limited. For example, a substrate used for a semiconductor device such as a wafer level CSP that does not use a wiring substrate (interbother), various semiconductor devices, various electronic devices, and the like is used.

As a material forming the conductive layer 14 (electrode pad 16), a metal having good conductivity such as copper (Cu) is used.
As a material forming the insulating layer 13, for example, a synthetic resin such as photosensitive polyimide, photosensitive epoxy, photosensitive benzocyclobutene (BCB) is used.

As a material for forming the sealing layer 15, for example, a synthetic resin material such as a photosensitive acrylic resin or an epoxy resin is used.
As a material for forming the solder bump 17, solder used for solder bump formation or for solder connection in a circuit or between circuits is used.
As a material for forming the protective layer 18, a photosensitive resin made of an acrylic resin, a silicone resin, or the like, or a phenol resin is used.

  Note that a buffer portion may be provided between the electrode pad 16 and the insulating layer 13 for the purpose of relaxing the force generated when the solder bump 17 is pressed against the electrode pad 16.

  In this semiconductor device 20, the protective layer 18 is provided over the entire area on the sealing layer 15 so that the top 17 a of the solder bump 17 opposite to the electrode pad 16 is slightly exposed. The weather resistance is improved, and the semiconductor device 20 is excellent in long-term reliability.

  In addition, since the semiconductor device 20 has a slight step between the top portion 17a and the surface of the protective layer 18, the semiconductor device 20 can be stably fixed by vacuum-sucking the surface of the protective layer 18. The back grind processing of the semiconductor substrate 11 can be performed without warping during the processing.

Next, a first embodiment of a method for manufacturing a semiconductor device used in an electronic component according to the present invention will be described with reference to FIGS. The first embodiment includes the following steps A to D.
In this embodiment, conventionally known methods can be used except for the steps relating to the formation of the protective layer, the grinding of the surface of the protective layer, and the back grinding of the semiconductor substrate.

  For example, first, a semiconductor substrate 1 on which an electrode 2 is formed is prepared, and an insulating layer 3 made of a synthetic resin is formed on one surface 1 a of the semiconductor substrate 1. Next, an opening is formed on the electrode 2 by photolithography to form an opening. Next, a seed layer for electrolytic plating made of copper or titanium is formed in the opening and on the insulating layer 3 by RF (Radio Frequency) sputtering. Next, a liquid resist is applied on the seed layer by a spin coating method, and a resist film for electrolytic plating having a predetermined pattern is formed by photolithography. Next, a conductive layer 4 is formed on the electrode 2 and the insulating layer 3 by electrolytic copper plating. Next, after the formation of the conductive layer 4, the resist film is peeled off, and then the seed layer is removed by etching. Next, a sealing layer 5 made of a synthetic resin is formed on the insulating layer 3 and the conductive layer 4. Next, after the sealing layer 5 is formed, the sealing layer 5 is perforated to expose the copper surface of the conductive layer 4 to form an electrode pad 6 to produce a structure as shown in FIG. .

  Next, as shown in FIG. 3B, a solder paste is placed on the electrode pad 6 by a ball mounting method or a printing method, and then a reflow process is performed to form solder bumps 7 (process A).

Next, as shown in FIG. 4A, the height of the solder bumps 7 made of synthetic resin over the entire area of the structure on the surface on which the solder bumps 7 are placed (on the sealing layer 5). A protective layer 8 having a thickness of 5 mm is formed (step B).
The protective layer 8 in the step B is formed by the following methods (1) and (2), for example.

(1) A liquid resin is applied to the surface of the above structure on which the solder bumps 7 are placed (on the sealing layer 5) by a method such as spin coating, roll coating, curtain coating, or screen printing. The protective layer 8 is formed by coating the entire surface of the solder bump 7 to a thickness greater than the height of the solder bumps 7.
As the liquid resin, an acrylic resin, a silicone resin, or the like is used.

(2) Using a mold, a synthetic resin is molded to a thickness equal to or greater than the height of the solder bumps 7 on the entire surface of the structure on which the solder bumps 7 are placed (on the sealing layer 5). The protective layer 8 is formed by molding.
A phenol resin or the like is used as the synthetic resin.

  Next, as shown in FIG. 4B, the surface of the protective layer 8 is ground to flatten the surface of the protective layer 8, and at the same time, the top 7a located on the opposite side of the solder bump 7 from the electrode pad 6 is slightly formed. Exposed (Step C). By this step, the height of the solder bump 7 and the thickness of the protective layer 8 become substantially the same.

Next, the structure provided with the solder bumps 7 and the protective layer 8 is fixed by vacuum-adsorbing the surface of the protective layer 8, and the other surface 1b of the semiconductor substrate 1 is back-grinded (step D). As shown in FIG. 5, the semiconductor substrate 1 is thinned to obtain a semiconductor device 10.
In the back grinding process, for example, the other surface 1b is ground using a back grinder or the like.

  In this embodiment, a protective layer 8 having a thickness equal to or greater than the height of the solder bump 7 made of a synthetic resin is provided over the entire region of the structure on the sealing layer 5 on which the solder bump 7 is placed. By grinding and flattening, the semiconductor device 10 having excellent weather resistance can be obtained. Further, since the structure provided with the solder bumps 7 and the protective layer 8 can be stably fixed without being affected by the shape of the solder bumps 7, the back grinding process of the semiconductor substrate 1 can be performed. As a result, it is possible to manufacture the semiconductor device 10 in which the thickness of the semiconductor substrate 1 is significantly reduced as compared with the prior art.

Next, a second embodiment of a method for manufacturing a semiconductor device used in an electronic component according to the present invention will be described with reference to FIGS. The second embodiment includes the following steps F to H.
In this embodiment, conventionally known methods can be used except for the steps relating to the formation of the protective layer and the back grinding of the semiconductor substrate.
For example, as in the first embodiment described above, a structure as shown in FIG.

  Next, as shown in FIG. 6B, after a solder paste is placed on the electrode pad 16 by a ball mounting method or a printing method, a reflow process is performed to form solder bumps 17 (process F).

Next, as shown in FIG. 7A, on the surface on which the solder bumps 17 are placed (on the sealing layer 15 so that the tops 17a of the solder bumps 17 opposite to the electrode pads 16 are slightly exposed). ) Is formed over the entire region (step G).
The protective layer 30 of the process G is formed by the following method, for example.

(1) Solder the liquid resin by spin coating, roll coating, curtain coating, screen printing, or the like so that the top 17a of the solder bump 17 opposite to the electrode pad 16 is slightly exposed. The protective layer 18 is formed by coating the entire surface of the surface on which the bumps 17 are placed (on the sealing layer 15) to a thickness slightly smaller than the height of the solder bumps 17.
As the liquid resin, an acrylic resin, a silicone resin, or the like is used.

Next, the surface protective sheet 30 is attached and the surface thereof is vacuum-sucked to fix the structure provided with the solder bumps 17 and the protective layer 18, and the other surface 11b of the semiconductor substrate 11 is back-grinded ( Step H), as shown in FIG. 7B, the semiconductor substrate 11 is thinned to obtain the semiconductor device 10.
In the back grinding process, for example, the other surface 11b is ground using a back grinder or the like.
After back grinding, peel off the protective sheet on the surface.

  In this embodiment, since the protective layer 18 is provided so that the top portions 17a of the solder bumps 17 are slightly exposed, the semiconductor device 20 having excellent weather resistance and heat uniformity can be obtained. Further, since the step between the top portion 17a and the surface of the protective layer 18 is small, the semiconductor device 20 can be stably fixed by vacuum-sucking the surface of the protective layer 18, and thus warp during processing. In addition, the back grinding process of the semiconductor substrate 11 can be performed. As a result, it is possible to manufacture the semiconductor device 20 in which the thickness of the semiconductor substrate 11 is significantly reduced as compared with the prior art.

  EXAMPLES Hereinafter, although an Example demonstrates this invention further more concretely, this invention is not limited to a following example.

(Example 1)
In this example, a semiconductor device was manufactured by the first embodiment of the method for manufacturing a semiconductor device according to the present invention described above.
In the first embodiment described above, a structure having a thickness of 5 μm of the insulating layer 3 and a thickness of 5 μm of the conductive layer 4 was manufactured using the semiconductor substrate 1 having a diameter of 8 inches and a thickness of 725 μm.

Next, a solder bump 7 having a height of 320 μm made of tin (Sn) -lead (Pb) eutectic was formed on the electrode pad 6 by a printing method.
Next, a phenolic resin was molded using a mold over the entire sealing layer 5 to form a protective layer 8 having a thickness of 330 μm.
Next, the surface of the protective layer 8 was polished until the height of the solder bump 7 reached 270 μm, and the surface of the protective layer 8 was flattened, and at the same time, the top 7a of the solder bump 7 was slightly exposed.

Next, the structure provided with the solder bumps 7 and the protective layer 8 is fixed by vacuum-sucking the surface of the protective layer 8, and the other surface 1 b of the semiconductor substrate 1 is back-grinded. The semiconductor device 10 was obtained with a thickness of 300 μm.
The obtained semiconductor device 10 was excellent in weather resistance.

(Comparative Example 1)
A semiconductor device was fabricated in the same manner as in Example 1 except that the other surface of the semiconductor substrate was not back-grinded.

  Table 1 shows a comparison between the semiconductor device 10 obtained in Example 1 and the semiconductor device obtained in Comparative Example 1.

  From Table 1, the thickness of the semiconductor device of Example 1 could be about 60% of the thickness of the semiconductor device of Comparative Example 1.

(Example 2)
In this example, a semiconductor device was manufactured by the second embodiment of the method for manufacturing a semiconductor device according to the present invention described above.
In the second embodiment described above, a structure having a thickness of 20 μm of the insulating layer 13 and a thickness of 16 μm of the conductive layer 14 was manufactured using the semiconductor substrate 11 having a diameter of 8 inches and a thickness of 725 μm.

Next, a solder bump 17 having a height of 200 μm made of tin (Sn) -lead (Pb) eutectic was formed on the electrode pad 16 by a printing method.
Next, a liquid having a viscosity of 5000 cP is formed over the entire area on the surface on which the solder bump 17 is placed (on the sealing layer 15) so that the top portion 17a of the solder bump 17 opposite to the electrode pad 16 is slightly exposed. The ultra-high viscosity silicone resin was applied by a curtain coating method to form a protective layer 18 having a thickness of 180 μm.
Next, the silicone resin slightly adhered to the tops 17a of the solder bumps 17 was removed by dry etching using a mixed gas of argon and nitrogen as a reaction gas.

Next, the surface of the protective layer 18 is vacuum-adsorbed to fix the structure provided with the solder bumps 17 and the protective layer 18, and the other surface 11 b of the semiconductor substrate 11 is back-grinded to form the semiconductor substrate 11. The semiconductor device 20 was obtained with a thickness of 350 μm.
The obtained semiconductor device 20 was excellent in weather resistance.

(Comparative Example 2)
A semiconductor device was fabricated in the same manner as in Example 2 except that the other surface of the semiconductor substrate was not back-grinded.

  Table 2 shows a comparison between the semiconductor device 20 obtained in Example 2 and the semiconductor device obtained in Comparative Example 2.

  From Table 2, the thickness of the semiconductor device of Example 2 could be about 60% of the thickness of the semiconductor device of Comparative Example 2.

  The electronic component and the manufacturing method thereof according to the present invention can be applied to semiconductor devices other than the CSP.

1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device used in an electronic component of the present invention. It is a schematic sectional drawing which shows 2nd embodiment of the semiconductor device used with the electronic component of this invention. It is a schematic sectional drawing which shows 1st embodiment of the manufacturing method of the semiconductor device used with the electronic component which concerns on this invention. It is a schematic sectional drawing which shows 1st embodiment of the manufacturing method of the semiconductor device used with the electronic component which concerns on this invention. It is a schematic sectional drawing which shows 1st embodiment of the manufacturing method of the semiconductor device used with the electronic component which concerns on this invention. It is a schematic sectional drawing which shows 2nd embodiment of the manufacturing method of the semiconductor device used with the electronic component which concerns on this invention. It is a schematic sectional drawing which shows 2nd embodiment of the manufacturing method of the semiconductor device used with the electronic component which concerns on this invention. It is a schematic sectional drawing which shows the structure of the conventional semiconductor device. It is a schematic sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,11 ... Semiconductor substrate, 2,12 ... Electrode, 3,13 ... Insulating layer, 4,14 ... Conductive layer, 5,15 ... Sealing layer, 6, 16, ... Electrode pads, 7, 17 ... solder bumps, 7a, 17a ... top, 8, 18 ... protective layer, 10, 20 ... semiconductor device, 30 ... surface protective sheet.

Claims (5)

A structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad in which the conductive layer is exposed is provided on the sealing layer, and a solder placed on the electrode pad In electronic parts with bumps,
The top of the solder bump opposite to the electrode pad has a flat surface, and a protective layer is provided over the entire surface of the structure on which the solder bump is placed so that the flat surface is exposed. Electronic parts characterized by being. A structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad in which the conductive layer is exposed is provided on the sealing layer, and a solder placed on the electrode pad In electronic parts with bumps,
An electronic component, wherein a protective layer is provided over the entire surface of the structure on which the solder bump is placed so that a top portion of the solder bump opposite to the electrode pad is exposed. . 3. The electronic component according to claim ₁ , wherein d ₁ ≧ d ₂ , where d _{1 is} a height of the solder bump and d ₂ is a thickness of the semiconductor substrate.   Using a structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad that exposes the conductive layer is provided on the sealing layer, solder bumps are provided on at least the electrode pad. Forming a protective layer having a thickness substantially equal to or greater than the height of the solder bumps over the entire surface of the structure on which the solder bumps are placed; A step C of exposing the top of the solder bump opposite to the electrode pad and grinding the surface of the protective layer so that the solder bump has a flat surface; and backgrinding the other surface of the semiconductor substrate. The manufacturing method of the electronic component characterized by performing the process D to do. Using a structure in which an insulating layer, a conductive layer, and a sealing layer are sequentially stacked on one surface of a semiconductor substrate, and an electrode pad that exposes the conductive layer is provided on the sealing layer, solder bumps are provided on at least the electrode pad. Forming a protective layer having a thickness substantially equal to or greater than the height of the solder bumps over the entire surface of the structure on which the solder bumps are placed; and A method for manufacturing an electronic component, comprising sequentially performing a step H of backgrinding the other surface of the semiconductor substrate.

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