JP2006269804A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2006269804A
JP2006269804A JP2005086557A JP2005086557A JP2006269804A JP 2006269804 A JP2006269804 A JP 2006269804A JP 2005086557 A JP2005086557 A JP 2005086557A JP 2005086557 A JP2005086557 A JP 2005086557A JP 2006269804 A JP2006269804 A JP 2006269804A
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semiconductor device
recess
mounting substrate
solder portion
solder
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Kaoru Usui
薫 碓井
Shuichi Sawamoto
修一 澤本
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Mitsumi Electric Co Ltd
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Mitsumi Electric Co Ltd
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Priority to JP2005086557A priority Critical patent/JP2006269804A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

<P>PROBLEM TO BE SOLVED: To further reduce packaging height in a WLCSP semiconductor device. <P>SOLUTION: In the WLCSP semiconductor device, an electrode post 28 embedded in a mold resin film 29 is made to form a spherical recess 28a in its end face, and a sold 30 is formed to embed the inside of the recess 28a. The semiconductor device is packaged in a state where a land enters the recess 28a, and in a state where the mold resin film 29 is brought into contact with a packaged substrate on the same. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置に係り、特に、WLCSP(Wafer Level Chip Size Package)の半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device of WLCSP (Wafer Level Chip Size Package).

携帯電話やメモリカード等の小型機器には、実装したときの高さが低くなる半導体装置が使用されている。この要求を満たす半導体装置は、表面実装タイプであり、その中の一つとしてWLCSP型であってランドグリッドアレイ型である半導体装置がある。   Small devices such as mobile phones and memory cards use semiconductor devices that have a low height when mounted. A semiconductor device satisfying this requirement is a surface mount type, and one of them is a WLCSP type and a land grid array type semiconductor device.

図４は従来のWLCSP型であってランドグリッドアレイ型である半導体装置１を示す。半導体装置１は、下面に集積回路部２が形成してある半導体チップ３の下面に銅製の電極ポスト４が配置してあり、半導体チップ３の下面がモールド樹脂膜５で覆われており、各ポスト４の端面４ａに半田バンプ６が形成してある構成である。   FIG. 4 shows a semiconductor device 1 of a conventional WLCSP type and a land grid array type. In the semiconductor device 1, copper electrode posts 4 are disposed on the lower surface of the semiconductor chip 3 on which the integrated circuit portion 2 is formed on the lower surface, and the lower surface of the semiconductor chip 3 is covered with the mold resin film 5. In this configuration, solder bumps 6 are formed on the end surface 4 a of the post 4.

この半導体装置１は、図５に示すように、半田バンプ６をランド１１と半田付けして、且つ、必要に応じて下面側をアンダーフィル１２で埋めて、実装基板１０上に実装してある。１５は半田部である。
特開２００４−２９６７７５号公報 As shown in FIG. 5, the semiconductor device 1 is mounted on a mounting substrate 10 by soldering solder bumps 6 to lands 11 and filling the lower surface side with underfill 12 as necessary. . Reference numeral 15 denotes a solder portion.
JP 2004-296775 A

この半導体装置１は、実装状態では実装基板１０の上面から寸法Ｓ浮いた状態にあり、この浮き分が、実装高さＨ１を無用に高くしていた。   The semiconductor device 1 is in a state where the dimension S is lifted from the upper surface of the mounting substrate 10 in the mounted state, and this floating portion unnecessarily increases the mounting height H1.

そこで、本発明は、上記課題を解決した半導体装置を提供することを目的とする。   Therefore, an object of the present invention is to provide a semiconductor device that solves the above-described problems.

本発明は、下面に集積回路部を有する半導体チップと、該半導体チップの下面に並んでおり、前記集積回路部と電気的に接続されて立っている複数の導電性のポストと、該半導体チップの下面を覆っている絶縁性の保護膜と、各ポストの端面上に形成してある外部端子としての半田部とを有し、
該半田部によって、実装基板上に実装される半導体装置において、
前記ポストは、その端面が前記保護膜の面より凹んでいる凹部を有する構成であり、
前記半田部が、この凹部に設けてある構成としたことを特徴とする。 The present invention includes a semiconductor chip having an integrated circuit portion on a lower surface, a plurality of conductive posts arranged on the lower surface of the semiconductor chip and electrically connected to the integrated circuit portion, and the semiconductor chip Insulating protective film covering the lower surface of each and a solder part as an external terminal formed on the end face of each post,
In the semiconductor device mounted on the mounting substrate by the solder portion,
The post is configured to have a recess whose end surface is recessed from the surface of the protective film,
The solder portion is provided in the concave portion.

本発明によれば、半導体装置は、凹部内に、実装基板上のランドが相対的に入り込んだ状態となって半田部がランドと接合されて、且つ保護膜が実装基板の上面に当接した状態で、実装高さを低くされて実装されるようになる。   According to the present invention, in the semiconductor device, the land on the mounting substrate relatively enters the recess, the solder portion is bonded to the land, and the protective film is in contact with the upper surface of the mounting substrate. In the state, the mounting height is lowered and mounting is started.

次に本発明の実施の形態について説明する。   Next, an embodiment of the present invention will be described.

図１は本発明の実施例１になる半導体装置２０を実装するときの姿勢で示す。この半導体装置２０は、WLCSP型であってランドグリッドアレイ型である。半導体装置２０は、完成したウェハから切りだされたものであって、下面に集積回路部２２が形成してある半導体チップ２１と、パッシベーションＳｉＮ膜２４と、アルミニウムパッド２５と、ポリイミド膜２６と、引き出し端子２７と、立っている銅製の電極ポスト２８と、保護膜としてのモールド樹脂膜２９と、外部端子としての半田部３０とを有する構成である。   FIG. 1 shows a posture when the semiconductor device 20 according to the first embodiment of the present invention is mounted. The semiconductor device 20 is a WLCSP type and a land grid array type. The semiconductor device 20 is cut from a completed wafer, and includes a semiconductor chip 21 having an integrated circuit portion 22 formed on the lower surface, a passivation SiN film 24, an aluminum pad 25, a polyimide film 26, The lead terminal 27, a standing copper electrode post 28, a mold resin film 29 as a protective film, and a solder portion 30 as an external terminal.

集積回路部２２の一部と半田部３０とは、アルミニウムパッド２５、引き出し端子２７、電極ポスト２８を介して電気的に接続している。   A part of the integrated circuit portion 22 and the solder portion 30 are electrically connected via an aluminum pad 25, a lead terminal 27, and an electrode post 28.

パッシベーションＳｉＮ膜２４及びポリイミド膜２６は、集積回路部２２を覆っている。モールド樹脂膜２９は引き出し端子２７を覆っている。電極ポスト２８は、歪むことによって、半導体装置２０が実装されて使用されている状態で半導体チップ２３と実装基板１０との熱膨張係数のミスマッチに起因して発生する熱応力を吸収する役割りを有する。   The passivation SiN film 24 and the polyimide film 26 cover the integrated circuit portion 22. The mold resin film 29 covers the lead terminals 27. The electrode post 28 serves to absorb thermal stress generated due to a mismatch in thermal expansion coefficient between the semiconductor chip 23 and the mounting substrate 10 when the semiconductor device 20 is mounted and used by being distorted. Have.

ポスト２８は、その端に、球面状の凹部２８ａを有する。よって、電極ポスト２８の端は、モールド樹脂膜２９の面２９ａに対して凹んでいる。また、電極ポスト２８の径Ｄは、実装基板１０上のランド１１の大きさよりも大きい。   The post 28 has a spherical recess 28a at its end. Therefore, the end of the electrode post 28 is recessed with respect to the surface 29 a of the mold resin film 29. Further, the diameter D of the electrode post 28 is larger than the size of the land 11 on the mounting substrate 10.

半田部３０は、ポスト２８の端の凹部２８ａの内部に設けてある。なお、半田部３０はポスト２８の端の凹部２８ａ内に設けてあればよく、モールド樹脂膜２９の面２９ａから少し突き出ていてもよい。   The solder portion 30 is provided inside the recess 28 a at the end of the post 28. In addition, the solder part 30 should just be provided in the recessed part 28a of the edge of the post | mailbox 28, and may protrude a little from the surface 29a of the mold resin film 29. FIG.

図２は上記の構成の半導体装置２０が実装基板１０上に表面実装してある状態を示す。１２は配線パターン、１３は半田レジストである。ランド１１は半田レジスト１３より若干突き出ている。半導体装置２０は、半田部３０がランド１１に対向するように実装基板１０上に仮止めされ、リフロー炉を通って実装される。３０Ａは一旦溶融して凝固した半田部である。   FIG. 2 shows a state where the semiconductor device 20 having the above configuration is surface-mounted on the mounting substrate 10. 12 is a wiring pattern and 13 is a solder resist. The land 11 protrudes slightly from the solder resist 13. The semiconductor device 20 is temporarily fixed on the mounting substrate 10 so that the solder part 30 faces the land 11 and is mounted through a reflow furnace. Reference numeral 30A denotes a solder portion which is once melted and solidified.

半導体装置２０は、ランド１１が凹部２８ａ内に相対的に入り込んでおり、モールド樹脂膜２９の面２９ａが実装基板１０に当接している。半田部３０Ａは、ランド１１を包み込んでいる。   In the semiconductor device 20, the land 11 relatively enters the recess 28 a, and the surface 29 a of the mold resin film 29 is in contact with the mounting substrate 10. The solder part 30 </ b> A surrounds the land 11.

半導体装置２０は実装基板１０から実質上浮いていず、よって、実装高さＨ１０は従来の半導体装置１の実装高さＨ１よりも低い。また、実装高さＨ１０のバラツキも小さい。   The semiconductor device 20 is not substantially lifted from the mounting substrate 10, and therefore the mounting height H <b> 10 is lower than the mounting height H <b> 1 of the conventional semiconductor device 1. Further, the variation in the mounting height H10 is small.

半田部３０Ａの電極ポスト２８との接合界面４０は球面であるので、半田部３０Ａと電極ポスト２８との接合面の面積は、従来に比較して広くなり、しかも、立体的となるので、半田部３０Ａは電極ポスト２８から剥離し難い。   Since the bonding interface 40 between the solder portion 30A and the electrode post 28 is a spherical surface, the area of the bonding surface between the solder portion 30A and the electrode post 28 is larger than that of the conventional case and moreover, it is three-dimensional. The portion 30A is difficult to peel off from the electrode post 28.

また、半田部３０Ａの電極ポスト２８の外へのはみ出し量が少なくなり、ブリッヂ不良が生じ難い。   In addition, the amount of protrusion of the solder portion 30A to the outside of the electrode post 28 is reduced, and a bridge failure is unlikely to occur.

よって、半導体装置２０の半田部３０と実装基板１０上のランド１１との接続部分は、従来に比較して高い信頼性を有する。   Therefore, the connection portion between the solder portion 30 of the semiconductor device 20 and the land 11 on the mounting substrate 10 has higher reliability than the conventional one.

次に、上記半導体装置２０の製造工程について、図３を参照して説明する。   Next, the manufacturing process of the semiconductor device 20 will be described with reference to FIG.

先ず、図３（Ａ）に示すように、所定位置にアルミニウムパッド２５を有するウェハ４０の集積回路等が作り込まれた上面にパッシベーションＳｉＮ膜２２を形成し、続いて、同図（Ｂ）に示すように、ポリイミド膜２６を塗布して形成する。   First, as shown in FIG. 3A, a passivation SiN film 22 is formed on the upper surface of the wafer 40 having an aluminum pad 25 at a predetermined position on which an integrated circuit or the like is formed, and then in FIG. As shown, a polyimide film 26 is applied and formed.

次いで、同図（Ｃ）に示すように、ポリイミド膜２６上に引き出し端子２７をアルミニウムパッド２５と接続させて配置して形成する。   Next, as shown in FIG. 3C, lead terminals 27 are formed on the polyimide film 26 so as to be connected to the aluminum pads 25.

次いで、同図（Ｄ）に示すように、メッキによって、引き出し端子２７の端に、電極ポスト２８Ａを形成する。   Next, as shown in FIG. 4D, electrode posts 28A are formed on the ends of the lead terminals 27 by plating.

次いで、同図（Ｅ）に示すように、ウェハ４０の上面を樹脂封止してモールド樹脂膜２９Ａを形成し、次いで、モールド樹脂膜２９Ａの表面を研摩して、同図（Ｆ）に示すように、電極ポスト２８Ａの平らな端面２８Ａａが露出するようにする。モールド樹脂膜２９Ａはモールド樹脂膜２９となる。   Next, as shown in FIG. 5E, the upper surface of the wafer 40 is resin-sealed to form a mold resin film 29A, and then the surface of the mold resin film 29A is polished, and shown in FIG. Thus, the flat end face 28Aa of the electrode post 28A is exposed. The mold resin film 29A becomes the mold resin film 29.

次いで、電極ポスト２８Ａの端面２８Ａａに対してエッチングを行い、同図（Ｇ）に示すように、球面状の凹部２８ａを形成する。電極ポスト２８Ａは電極ポスト２８となる。   Next, the end face 28Aa of the electrode post 28A is etched to form a spherical recess 28a as shown in FIG. The electrode post 28 </ b> A becomes the electrode post 28.

次いで、開口が電極ポスト２８に対応して形成してあるマスクを使用して印刷を行ってクリーム半田を全部の凹部２８ａ内に埋め、リフロー炉を通して、同図（Ｈ）に示すように、全部の凹部２８ａ内に半田部３０を形成する。   Next, printing is performed using a mask in which openings are formed corresponding to the electrode posts 28, so that the cream solder is filled in all the recesses 28a, and then, through a reflow furnace, as shown in FIG. The solder part 30 is formed in the recess 28a.

印刷、リフローに代えて、凹部２８ａの面にメッキを行うことにより、或いは、半田ボールを凹部２８ａ内に置いてリフローすることによっても、半田部３０を形成することが出来る。   Instead of printing and reflow, the solder portion 30 can be formed by plating the surface of the recess 28a or by reflowing by placing a solder ball in the recess 28a.

最後に、同図（Ｈ）に示すように、ウェハ４０をテープ５０上に貼り付け、ウェハ４０をダイシングすることで、個片化され、半導体装置２０が得られる。   Finally, as shown in FIG. 6H, the wafer 40 is bonded onto the tape 50, and the wafer 40 is diced to obtain the semiconductor device 20.

本発明の実施例１になる半導体装置を示す図である。It is a figure which shows the semiconductor device which becomes Example 1 of this invention. 図１の半導体装置が実装基板上に実装された状態を示す図である。FIG. 2 is a diagram showing a state where the semiconductor device of FIG. 1 is mounted on a mounting substrate. 図１の半導体装置の製造工程を示す図である。FIG. 2 is a diagram showing a manufacturing process of the semiconductor device of FIG. 1. 従来の１例の半導体装置を示す図である。It is a figure which shows the conventional semiconductor device of an example. 図４の半導体装置が実装基板上に実装された状態を示す図である。FIG. 5 is a diagram showing a state where the semiconductor device of FIG. 4 is mounted on a mounting substrate.

符号の説明Explanation of symbols

１０ 実装基板
１１ ランド
２０ 半導体装置
２１ 半導体チップ
２８ 電極ポスト
２８ａ 球面状の凹部
２９ モールド樹脂膜
３０ 半田部 DESCRIPTION OF SYMBOLS 10 Mounting substrate 11 Land 20 Semiconductor device 21 Semiconductor chip 28 Electrode post 28a Spherical recessed part 29 Mold resin film 30 Solder part

Claims (4)

下面に集積回路部を有する半導体チップと、該半導体チップの下面を覆う絶縁性の保護膜と、該半導体チップの下面に配置してある外部端子としての半田部とを有し、
該半田部によって、実装基板上に実装される半導体装置において、
前記半田部が、前記保護膜の面から凹んでいる凹部に設けてある構成としたことを特徴とする半導体装置。 A semiconductor chip having an integrated circuit portion on the lower surface, an insulating protective film covering the lower surface of the semiconductor chip, and a solder portion as an external terminal disposed on the lower surface of the semiconductor chip;
In the semiconductor device mounted on the mounting substrate by the solder portion,
2. A semiconductor device according to claim 1, wherein the solder portion is provided in a recess that is recessed from the surface of the protective film. 下面に集積回路部を有する半導体チップと、該半導体チップの下面に並んでおり、前記集積回路部と電気的に接続されて立っている複数の導電性のポストと、該半導体チップの下面を覆っている絶縁性の保護膜と、各ポストの端面上に形成してある外部端子としての半田部とを有し、
該半田部によって、実装基板上に実装される半導体装置において、
前記ポストは、その端面が前記保護膜の面より凹んでいる凹部を有する構成であり、
前記半田部が、この凹部に設けてある構成としたことを特徴とする半導体装置。 A semiconductor chip having an integrated circuit portion on a lower surface; a plurality of conductive posts arranged on the lower surface of the semiconductor chip and electrically connected to the integrated circuit portion; and a lower surface of the semiconductor chip. Having an insulating protective film and a solder portion as an external terminal formed on the end face of each post,
In the semiconductor device mounted on the mounting substrate by the solder portion,
The post is configured to have a recess whose end surface is recessed from the surface of the protective film,
A semiconductor device characterized in that the solder portion is provided in the recess. 請求項２に記載の半導体装置において、
前記凹部は、
前記保護膜を前記ポストの端面が露出するように形成した後に、エッチングを行って形成したものであることを特徴とする半導体装置。 The semiconductor device according to claim 2,
The recess is
A semiconductor device, wherein the protective film is formed by etching after forming the end face of the post to be exposed. 請求項１又は請求項２に記載の半導体装置が、上記凹部内に、前記実装基板上のランドが相対的に入り込んだ状態となって前記半田部が前記ランドと接合されて、且つ前記保護膜が前記実装基板の上面に当接した状態で、前記実装基板上に実装してある構成としたことを特徴とする半導体装置の実装構造。   3. The semiconductor device according to claim 1, wherein the land on the mounting substrate relatively enters the recess, the solder portion is joined to the land, and the protective film is formed. A mounting structure of a semiconductor device, wherein the mounting structure is mounted on the mounting substrate in a state of being in contact with the upper surface of the mounting substrate.
JP2005086557A 2005-03-24 2005-03-24 Semiconductor device Pending JP2006269804A (en)

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JP2008277569A (en) * 2007-04-27 2008-11-13 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
WO2021133165A1 (en) * 2019-12-23 2021-07-01 Qdos Flexcircuits Sdn Bhd An integrated circuit substrate having a recess for receiving a solder fillet

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WO2021133165A1 (en) * 2019-12-23 2021-07-01 Qdos Flexcircuits Sdn Bhd An integrated circuit substrate having a recess for receiving a solder fillet

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