KR101547207B1 - Electrical connecting structure and method of semiconductor chip - Google Patents

Electrical connecting structure and method of semiconductor chip Download PDF

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Publication number
KR101547207B1
KR101547207B1 KR1020130150978A KR20130150978A KR101547207B1 KR 101547207 B1 KR101547207 B1 KR 101547207B1 KR 1020130150978 A KR1020130150978 A KR 1020130150978A KR 20130150978 A KR20130150978 A KR 20130150978A KR 101547207 B1 KR101547207 B1 KR 101547207B1
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South Korea
Prior art keywords
semiconductor chip
wiring board
electrode pads
holes
semiconductor
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KR1020130150978A
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Korean (ko)
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KR20150065544A (en
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심기준
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심기준
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

The present invention provides an electrical connection structure and a method of a semiconductor chip capable of realizing stable bonding between a semiconductor chip and a wiring board. An electrical connection structure of a semiconductor chip according to the present invention includes a semiconductor chip, a wiring board, and a plurality of metal plugs. The semiconductor chip has electrode pads formed on one surface thereof. The wiring board has through holes corresponding to the electrode pads of the semiconductor chip, and the electrode pads are stacked on the semiconductor chip through the through holes. A plurality of metal plugs are filled through the through holes to electrically connect the electrode pads and the wiring board. The metal plug may be formed by plating or vacuum deposition.

Description

TECHNICAL FIELD [0001] The present invention relates to an electrical connecting structure and a semiconductor chip,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to an electrical connection structure and a method of a semiconductor chip that realize stable bonding between a semiconductor chip and a wiring substrate.

A semiconductor chip manufactured through a semiconductor wafer manufacturing process uses a wiring board as a means for mediating electrical connection with a mother board. The semiconductor chips are mounted on the wiring board and then connected by various electrical connection methods. For example, wire bonding, flip chip bonding using a bump, bonding using an anisotropic conductive film (ACF), or the like may be used as an electrical connection method.

The wire bonding requires a loop of a certain height of the bonding wire connecting the semiconductor chip and the wiring substrate. Therefore, there is a problem that the size of the semiconductor device becomes large, and thus the semiconductor device becomes less responsive to the thinning and shortening of the semiconductor device.

Flip chip bonding using a bump and bonding using an anisotropic conductive film are advantageous in that the semiconductor device can be made thinner and thinner than a wire bonding method. However, since the bonding interface is formed between the semiconductor chip and the wiring substrate by the bump or the anisotropic conductive film, a problem occurs at the bonding interface due to thermal or mechanical stress applied to the bonding interface during driving or handling of the semiconductor device I am concerned. As a result, there is a limit in realizing a stable bonding between the semiconductor chip and the wiring board. That is, since flip chip bonding keeps the semiconductor chip in contact with the wiring substrate and is not in a welded state, the contact state becomes unstable due to the difference in thermal expansion coefficient between the semiconductor chip and the wiring substrate as the temperature rises and falls. It can act as a factor for hindering stable electrical connection between the semiconductor chip and the wiring board.

Korean Patent No. 10-0884295 (Feb.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an electrical connection structure and method of a semiconductor chip capable of realizing stable bonding between a semiconductor chip and a wiring board.

In order to achieve the above object, the present invention provides an electrical connection structure of a semiconductor chip including a semiconductor chip, a wiring board, and a plurality of metal plugs. Electrode pads are formed on one surface of the semiconductor chip. The wiring board has through holes corresponding to the electrode pads of the semiconductor chip, and the electrode pads are stacked on the semiconductor chip through the through holes. The plurality of metal plugs are filled through the through holes to electrically connect the electrode pads and the wiring board.

In the electrical connection structure of the semiconductor chip according to the present invention, the metal plug may be electrically connected to a wiring pattern formed on a surface opposite to one surface of the wiring board on which the semiconductor chip is stacked.

In the electrical connection structure of the semiconductor chip according to the present invention, the metal plug and the wiring pattern may be integrally formed on the wiring board.

In the electrical connection structure of the semiconductor chip according to the present invention, the metal plug may be formed by plating or vacuum deposition.

In the electrical connection structure of the semiconductor chip according to the present invention, a first pocket for accommodating the semiconductor chip may be formed on the wiring board.

The electrical connection structure of the semiconductor chip according to the present invention may further include a support substrate attached to a surface opposite to one surface of the semiconductor chip.

In the electrical connection structure of the semiconductor chip according to the present invention, the supporting substrate may be provided with a second pocket in which the semiconductor chip can be housed.

In the electrical connection structure of the semiconductor chip according to the present invention, the support substrate may be made of metal, plastic or ceramic material.

The electrical connection structure of the semiconductor chip according to the present invention may further include a protective substrate interposed between the semiconductor chip and the wiring substrate and having an exposure hole exposing the electrode pad of the semiconductor chip.

In the electrical connection structure of the semiconductor chip according to the present invention, the protective substrate may be formed with a third pocket in which the semiconductor chip can be housed.

In the electrical connection structure of the semiconductor chip according to the present invention, the protective substrate may be made of an insulating plastic material.

In the electrical connection structure of the semiconductor chip according to the present invention, the wiring board may include a printed circuit board, a lead frame, or a ceramic substrate.

The electrical connection structure of the semiconductor chip according to the present invention may further include a sealing member for sealing the surface of the wiring board on which the semiconductor chip is mounted.

The present invention also provides an electrical connection structure of a semiconductor chip including a plurality of semiconductor chips, a wiring board, and a plurality of metal plugs. The plurality of semiconductor chips

Electrode pads are formed on one surface. The wiring board has through holes formed corresponding to the electrode pads of the plurality of semiconductor chips, and the electrode pads are stacked on the plurality of semiconductor chips through the through holes. The plurality of metal plugs are filled through the through holes to electrically connect the electrode pads of the plurality of semiconductor chips to the wiring board.

In the electrical connection structure of the semiconductor chip according to the present invention, the plurality of semiconductor chips may be a wafer formed in a lump.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor chip having electrode pads on one surface thereof; forming a wiring board having through holes corresponding to electrode pads of the semiconductor chip, And forming a metal plug filling the through holes to electrically connect the electrode pads and the wiring board to each other.

The method for electrically connecting a semiconductor chip according to the present invention may further include attaching a support substrate to a surface of the semiconductor chip opposite to a surface on which the electrode pads are formed, which is performed before the step of stacking.

A method of electrically connecting a semiconductor chip according to the present invention is characterized in that a protective substrate, which is formed before the stacking step and in which the exposure pits are formed corresponding to the electrode pads of the semiconductor chip, And stacking the semiconductor chip on the semiconductor chip. At this time, the protective substrate may be laminated so that the exposed holes of the protective substrate and the through holes of the wiring substrate are communicated with each other.

In the step of forming the metal plug, the metal plug is electrically connected to a wiring pattern formed on a surface opposite to one surface of the wiring board on which the semiconductor chip is stacked.

In the method of electrically connecting a semiconductor chip according to the present invention, in the step of forming the metal plug, the metal plug may be formed by plating or vacuum deposition.

According to the present invention, after a semiconductor chip is disposed on one surface of a wiring board having through holes corresponding to electrode pads of the semiconductor chip, the semiconductor chip and the wiring substrate are electrically connected to each other while filling the through holes through plating or vacuum deposition. It is possible to realize stable bonding between the semiconductor chip and the wiring board. That is, the through holes of the wiring board are filled by plating or vacuum deposition, so that the electrical connection between the electrode pads of the semiconductor chip and the wiring board is collectively performed, so that stable bonding between the semiconductor chip and the wiring board can be realized.

Since the connection between the semiconductor chip and the wiring board is performed collectively through the process of forming the metal plug on the wiring board, there is an advantage that the manufacturing process of the semiconductor device including the electrical connection structure of the semiconductor chip can be simplified. In particular, since the step of forming the wiring pattern to be formed on the upper surface of the wiring board can be collectively performed in the process of forming the metal plug, there is an advantage that the manufacturing process of the semiconductor device including the electrical connection structure of the semiconductor chip can be simplified .

1 is a cross-sectional view illustrating an electrical connection structure of a semiconductor chip according to a first embodiment of the present invention.
FIGS. 2 to 5 are views showing steps of an electrical connection method of the semiconductor chip of FIG.
FIGS. 6 and 7 are views showing respective steps of a method of manufacturing a semiconductor device having an electrical connection structure of the semiconductor chip of FIG.
8 and 9 are views showing an electrical connection structure of a semiconductor chip according to a second embodiment of the present invention.
10 and 11 are views showing an electrical connection structure of a semiconductor chip according to a third embodiment of the present invention.
12 and 13 are views showing an electrical connection structure of a semiconductor chip according to a fourth embodiment of the present invention.

In the following description, only parts necessary for understanding embodiments of the present invention will be described, and descriptions of other parts will be omitted to the extent that they do not disturb the gist of the present invention.

The terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary meanings and the inventor is not limited to the meaning of the terms in order to describe his invention in the best way. It should be interpreted as meaning and concept consistent with the technical idea of the present invention. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely preferred embodiments of the present invention, and are not intended to represent all of the technical ideas of the present invention, so that various equivalents And variations are possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

1 is a cross-sectional view illustrating an electrical connection structure of a semiconductor chip according to a first embodiment of the present invention.

1, an electrical connection structure 90 of a semiconductor chip according to the first embodiment includes a semiconductor chip 11, a wiring board 40, and a metal plug 50. The semiconductor chip 11 has electrode pads 13 formed on one surface thereof. The wiring board 40 is formed with through holes 41 corresponding to the electrode pads 13 of the semiconductor chip 11 and the semiconductor pads 13 are exposed through the through holes 41 11). The metal plug 50 is filled through the through hole 41 to electrically connect the electrode pads 13 and the wiring board 40 to each other. In addition, the electrical connection structure 90 of the semiconductor chip according to the first embodiment may further include a support substrate 20 and a protection substrate 30.

At this time, the supporting substrate 20 is attached to the surface opposite to the one surface of the semiconductor chip 11 to support the semiconductor chip 11. The support substrate 20 is also used for facilitating the handling of the semiconductor chip 11 during the manufacturing process of the semiconductor device. As the material of the support substrate 20, plastic, ceramics or metal materials can be used. When the support substrate 20 is made of a metal material, it can function as a heat sink for discharging the heat generated from the semiconductor chip 11 to the outside.

The semiconductor chip 11 is attached to the upper portion of the support substrate 20. Such a semiconductor chip 11 can be manufactured through a wafer manufacturing process. At this time, the semiconductor chip 11 is a chip having a plurality of electrode pads 13, which may be an integrated circuit chip or an RFID chip. The semiconductor chip 11 has electrode pads 13 formed on both sides of one surface thereof. In this embodiment, an example in which a plurality of semiconductor chips 11 are attached on a support substrate 20 is disclosed.

The protective substrate 30 is formed to cover the semiconductor chip 11 attached to the upper portion of the supporting substrate 20 and protects the semiconductor chip 11 during the manufacturing process of the semiconductor device. An exposure hole 31 is formed in the protective substrate 30 so that the electrode pad 13 of the semiconductor chip 11 is exposed. The exposure holes 31 may be formed to a size such that most or all of the electrode pads 13 are exposed. As the material of the protection substrate 30, a flexible plastic material can be used so that the semiconductor chip 11 can be covered.

The wiring board 40 is stacked so as to cover the semiconductor chip 11 attached on the supporting substrate 20. [ As the wiring board 40, a printed circuit board, a lead frame, or a ceramic board can be used. As the printed circuit board, a flexible or rigid printed circuit board can be used. A wiring pattern 43 electrically connected to the electrode pads 13 of the semiconductor chip 11 is formed on the wiring board 40. The wiring pattern 43 is formed around the through holes 41 in the upper portion of the wiring board 40 and is electrically connected to the metal plug 50 formed in the through hole 41.

The metal plug 50 electrically connects the electrode pad 13 of the semiconductor chip 11 and the wiring pattern 43 of the wiring board 40. The metal plug 50 may be formed by plating or vacuum deposition. Electroless plating or electroless plating may be used as the plating method. As the material of the metal plug 50, a material having good electrical conductivity, such as gold, copper, aluminum, nickel, or titanium, may be used, but is not limited thereto.

The metal plug 50 may be formed in a separate manufacturing process from the wiring pattern 43 formed on the upper surface of the wiring board 40 or integrally formed in the process of forming the metal plug 50.

On the other hand, in the first embodiment, an example of using the protective substrate 30 is disclosed, but the protective substrate 30 may not be used.

An electrical connection method for implementing the electrical connection structure 90 of the semiconductor chip according to the first embodiment will now be described with reference to FIGS. 1 to 5. FIG. 2 to 5 are views showing respective steps according to an electrical connection method of the semiconductor chip 11 of FIG.

First, as shown in FIG. 2, a support substrate 20 is prepared.

Next, as shown in FIG. A plurality of semiconductor chips (11) are attached to the support substrate (20). At this time, the semiconductor chip 11 may be provided on the support substrate 20 on the wafer divided by the plurality of semiconductor chips 11. [ That is, on the support substrate 20 through a conventional method of the semiconductor chip 11. [ The semiconductor chip 11 is attached so that the electrode pads 13 formed on one surface thereof are exposed to the upper portion of the supporting substrate 20. [

4, the protective substrate 30 is attached to the semiconductor chip 11 so as to cover the semiconductor chip 11 attached to the upper portion of the supporting substrate 20. As shown in FIG. The protection substrate 30 may be attached only to the semiconductor chip 11 or cover the entire upper surface of the supporting substrate 20 and the semiconductor chip 11. At this time, the electrode pads 13 of the semiconductor chip 11 are exposed to the outside through the exposure holes 31 of the protection substrate 30.

Then, as shown in FIG. 5, the wiring board 40 is laminated on one surface of the semiconductor chip 11 covered with the protective substrate 30. Next, as shown in FIG. The wiring board 40 is stacked on one surface of the semiconductor chip 11 so that the electrode pads 13 of the semiconductor chip 11 are exposed through the through holes 41. [ The wiring board 40 is illustrated as a strip-shaped wiring board 40 capable of covering the entire plurality of semiconductor chips 11 located below the wiring board 40. However, Substrate 40 may be used.

A pressing member or an adhesive member capable of stably fixing the wiring board 40 laminated on the protective substrate 30 can be used. For example, when an adhesive member is used, it may be interposed between the protective substrate 30 and the wiring substrate 40. As the adhesive member, a liquid or tape adhesive member may be used.

Then, as shown in FIG. 1, a metal plug 50 is formed through plating or vacuum deposition. The metal plug 50 is filled through the through hole 41 to electrically connect the electrode pads 13 and the wiring pattern 43 of the wiring board 40. At this time, the metal plug 50 is formed by plating or vacuum deposition.

The metal plug 50 is formed by plating or vacuum evaporation to fill the through hole 41 of the wiring substrate 40 starting from the electrode pad 13 of the semiconductor chip 11, To the wiring pattern 43 formed on the upper surface of the semiconductor device.

As described above, according to the first embodiment, after the semiconductor chip 11 is disposed on one side of the wiring board 40 having the through holes 41 corresponding to the electrode pads 13 of the semiconductor chip 11, And the through hole 41 are filled through plating or vacuum deposition to form the metal plug 50 to electrically connect the semiconductor chip 11 and the wiring board 40. This allows the semiconductor chip 11 and the wiring board 40 can be realized. Since the electrical connection between the electrode pads 13 of the semiconductor chip 11 and the wiring board 40 is collectively performed by filling the through holes 41 of the wiring board 40 through plating or vacuum deposition, Stable bonding between the semiconductor chip 11 and the wiring board 40 can be realized.

Since the connection between the semiconductor chip 11 and the wiring board 40 is performed collectively through the process of forming the metal plug 50 on the wiring board 40, The manufacturing process of the semiconductor device including the semiconductor device can be simplified.

Since the step of forming the wiring pattern 43 to be formed on the upper surface of the wiring board 40 can be collectively performed in the process of forming the metal plug 50, The manufacturing process of the semiconductor device can be simplified. In this case, a metal layer may be formed on the entire upper surface of the wiring board 40 in the step of forming the metal plug 50. The metal layer may be formed of the wiring pattern 43 through a photolithography process. The metal plug 50 and the wiring pattern 43 may be formed on the upper surface of the wiring board 40 after forming the mask film including the through holes 41 and correspondingly to the regions formed by the wiring patterns 43, Can be collectively formed. Thereafter, the mask film is removed from the upper surface of the wiring board 40, whereby the metal plug 50 and the wiring pattern 43 can be formed. As the mask film, a photosensitive film or a plastic film may be used.

The semiconductor device 100 can be manufactured as shown in FIGS. 1 to 7 by using the electrical connection structure 90 of the semiconductor chip according to the first embodiment. Here, FIGS. 6 and 7 are views showing respective steps of the method for manufacturing the semiconductor device 100 having the electrical connection structure 90 of the semiconductor chip of FIG.

In the method of manufacturing the semiconductor device 100 according to the first embodiment, the electrical connection structure 90 of the semiconductor chip according to FIGS. 1 to 5 may be formed in the same manner.

Next, as shown in Fig. 6, the sealing member 60 may be inserted to protect the electrical connection structure (90 in Fig. 1) of the semiconductor chip according to the first embodiment. The seal member 60 is injected between the support substrate 20 and the wiring substrate 40 in the form of a liquid to fill the space between the support substrate 20 and the wiring substrate 40, It is possible to increase the strength of the semiconductor element to be manufactured (100 in Fig.

Then, as shown in Fig. 7, the individual semiconductor element 100 can be obtained by cutting with the cutting member 70. Fig. At this time, in the cutting process using the cutting member 70, the area between the semiconductor chips 11 is cut to obtain an individual semiconductor device 100. [ In the semiconductor device 100, the wiring pattern 43 exposed to the upper portion of the wiring board 40 can be directly used as an external connection terminal or used as a pad to which an external connection terminal can be connected.

The semiconductor device 100 according to the first embodiment may have a chip scale package (CSP) shape, but is not limited thereto.

Second Embodiment

On the other hand, in the first embodiment, the example in which the semiconductor chip 11 is attached to the upper part of the plate-shaped supporting substrate 20 is described, but the present invention is not limited thereto. For example, as shown in Figs. 8 and 9, pockets 23 can be formed on the support substrate 20, and the semiconductor chips 11 can be housed in the pockets 23. Fig. 8 and 9 are views showing the electrical connection structure 190 of the semiconductor chip according to the second embodiment of the present invention.

8 and 9, the electrical connection structure 190 of the semiconductor chip according to the second embodiment includes a support substrate 20, a semiconductor chip 11, a protection substrate 30, a wiring substrate 40, Is the same as the first embodiment in that a plug 50 is provided. However, the second embodiment differs from the first embodiment in that the pockets 23 for accommodating the semiconductor chips 11 are formed on the support substrate 20.

The support substrate 20 is provided with a pocket 23 on which a semiconductor chip 11 can be stored. The semiconductor chip 11 is housed in the pocket 23.

The semiconductor chip 11 is housed in the pockets 23 of the supporting substrate 20 so that the electrode pads 13 formed on one surface thereof are exposed to the outside.

The protective substrate 30 is formed so as to cover the semiconductor chip 11 attached to the upper portion of the supporting substrate 20. The wiring board 40 is stacked so as to cover the semiconductor chip 11 attached on the supporting substrate 20. [ The metal plug 50 electrically connects the electrode pad 13 of the semiconductor chip 11 and the wiring pattern 43 of the wiring board 40.

At this time, in the second embodiment, the example in which the semiconductor chip 11 is completely housed in the pocket 23 formed in the support substrate 20 is described, but the present invention is not limited thereto. The pockets 23 may be formed in the supporting substrate 20 at a depth such that a part of the semiconductor chip 11 can protrude to the upper portion of the supporting substrate 20, for example.

In the second embodiment, the semiconductor chip 11 is completely housed in the pocket 23 formed in the support substrate 20, and the upper surface of the support substrate 20 and one surface of the semiconductor chip 11 are arranged The sealing process using the sealing member 60 can be omitted in manufacturing the semiconductor device using the electrical connection structure 190 of the semiconductor chip according to the second embodiment.

The semiconductor device using the electrical connection structure 190 of the semiconductor chip according to the second embodiment can be obtained by cutting the region between the semiconductor chips 11 with a cutting member in Fig.

The semiconductor device according to the second embodiment may have a chip scale package (CSP) shape, but is not limited thereto.

Third Embodiment

On the other hand, in the second embodiment, the example in which the pockets 23 are formed in the support substrate 20 is described, but the present invention is not limited thereto. For example, as shown in Figs. 10 and 11, the pockets 45 may be formed in the wiring board 40. Fig. 10 and 11 are views showing an electrical connection structure 290 of the semiconductor chip according to the third embodiment of the present invention.

10 and 11, the electrical connection structure 290 of the semiconductor chip according to the third embodiment includes a semiconductor chip 11, a wiring board 40, and a metal plug 50.

The wiring board 40 has a pocket 45 in which a semiconductor chip 11 can be received. The semiconductor chip 11 is accommodated in the pocket 45. A through hole 41 corresponding to the electrode pad 13 of the semiconductor chip 11 is formed on the bottom surface of the pocket 45.

The metal plug 50 electrically connects the electrode pad 13 of the semiconductor chip 11 and the wiring pattern 43 of the wiring board 40.

Since the electrical connection structure 290 of the semiconductor chip according to the third embodiment stores the semiconductor chip 11 on one side and the side surface of the semiconductor chip 11 in the pockets 45 of the wiring substrate 40, The protective substrate 30 can be omitted.

As described above, the example of the electrical connection structure 290 of the semiconductor chip according to the third embodiment does not include the support substrate 20 and the protection substrate 30, but the present invention is not limited thereto. For example, the electrical connection structure 290 of the semiconductor chip according to the third embodiment may further include the support substrate 20 or the protection substrate 30.

The semiconductor device using the electrical connection structure 290 of the semiconductor chip according to the third embodiment can be obtained by cutting the region between the semiconductor chips 11 with the cutting member in Fig.

The semiconductor device according to the third embodiment may have a chip scale package (CSP) shape, but is not limited thereto.

Fourth Embodiment

On the other hand, in the first to third embodiments, the example in which the electrical connection structure (90, 190, 290) of the semiconductor chip is implemented using the discrete semiconductor chip 11 separated on the wafer is described, but the invention is not limited thereto. 12 and 13, an electrical connection structure 390 of a semiconductor chip can be implemented using a wafer 10 having a plurality of semiconductor chips 11 formed thereon. 12 and 13 are views showing the electrical connection structure 390 of the semiconductor chip according to the fourth embodiment of the present invention.

12 and 13, the electrical connection structure 390 of the semiconductor chip according to the fourth embodiment includes a support substrate 20, a wafer 10, a wiring board 40, and a metal plug 50 .

A support substrate 20 is attached to the lower surface of the wafer 10. The wafer 10 has a structure in which a plurality of semiconductor chips 11 are formed in a lattice pattern in a row and a row, and the plurality of semiconductor chips 11 are divided by a cut region 15. The support substrate 20 is a member for fixing the wafer 10 and is made of a plastic dicing tape used for supporting the wafer 10 when the wafer 10 is separated into individual semiconductor chips 11 dicing tape may be used.

The wiring board 40 is stacked so as to cover the wafer 10 attached on the supporting substrate 20. [ The wiring board 40 has through holes 41 corresponding to the electrode pads 13 of the semiconductor chip 11. The wiring pattern 43 formed on the upper surface of the wiring board 40 is formed inside the cut region 15. [

The metal plug 50 electrically connects the electrode pad 13 of the semiconductor chip 11 and the wiring pattern 43 of the wiring board 40. The metal plug 50 is filled through the through hole 41 to electrically connect the electrode pads 13 and the wiring board 40 to each other.

The electrical connection structure 390 of the semiconductor chip according to the fourth embodiment has a structure in which the semiconductor chips 11 are collectively formed on the wafer 10 so that the electrical connection structure 390 between the semiconductor chip 11 and the wiring board 40 The protective substrate 30 interposed therebetween can be omitted.

As described above, the example of the electrical connection structure 390 of the semiconductor chip according to the fourth embodiment does not include the protection substrate 30, but the invention is not limited thereto. That is, the electrical connection structure 390 of the semiconductor chip according to the fourth embodiment may further include the protection substrate 30.

The semiconductor device using the electrical connection structure 390 of the semiconductor chip according to the fourth embodiment can be obtained by cutting the cut region 15 between the semiconductor chips 11 in FIG. 9 with a cutting member. After the wafer 10 is cut into discrete semiconductor elements, the semiconductor element portions are separated on the supporting substrate 20 on the supporting substrate 20. At this time, the supporting substrate 20 may remain in the form attached to the semiconductor chip 11 of the semiconductor element or may be removed.

The semiconductor device according to the fourth embodiment has a wafer level chip scale package (CSP) shape.

It should be noted that the embodiments disclosed in the present specification and drawings are only illustrative of specific examples for the purpose of understanding, and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

10: wafer
11: Semiconductor chip
13: Electrode pad
15: Cutting area
20: Support substrate
23: Pocket
30: Protective substrate
31: Exposure hole
40: wiring board
41: Through hole
43: wiring pattern
45: Pocket
50: metal plug
60: sealing member
70: cutting member
90,190,290,390: Electrical connection structure of semiconductor chip
100: semiconductor element

Claims (20)

A semiconductor chip having electrode pads formed on one surface thereof;
Wherein the semiconductor chip has through holes corresponding to the electrode pads of the semiconductor chip, one surface of which is laminated on the semiconductor chip so as to expose the electrode pads through the through holes, and a wiring pattern is formed on the surface opposite to the one surface A wiring board;
A plurality of metal plugs which are filled through the through holes and electrically connect the wiring patterns of the wiring pads and the electrode pads, respectively;
And an electrical connection structure of the semiconductor chip. delete The method according to claim 1,
Wherein the metal plug and the wiring pattern are integrally formed on the wiring board. The method according to claim 1,
Wherein the metal plug is formed by plating or vacuum deposition. The method according to claim 1,
Wherein the wiring board is provided with a first pocket in which the semiconductor chip can be housed. The method according to claim 1,
A support substrate attached to a surface opposite to one surface of the semiconductor chip;
And electrically connecting the semiconductor chip to the semiconductor chip. The method according to claim 6,
Wherein the supporting substrate is provided with a second pocket for accommodating the semiconductor chip. The method according to claim 6,
Wherein the supporting substrate is made of metal, plastic or ceramic material. The method according to claim 1,
A protective substrate interposed between the semiconductor chip and the wiring board and having an exposure hole exposing an electrode pad of the semiconductor chip;
And electrically connecting the semiconductor chip to the semiconductor chip. 10. The method of claim 9,
Wherein the protective substrate is provided with a third pocket in which the semiconductor chip can be housed. 10. The method of claim 9,
Wherein the protective substrate is made of an insulating plastic material. The method according to claim 1,
Wherein the wiring board includes a printed circuit board, a lead frame, or a ceramic substrate. The method according to claim 1,
A sealing member for sealing the surface of the wiring board on which the semiconductor chip is mounted;
And an electrical connection structure of the semiconductor chip. A plurality of semiconductor chips having electrode pads on one surface thereof;
Wherein the semiconductor chips are stacked on the plurality of semiconductor chips so as to expose the electrode pads through the through holes and one surface of the semiconductor pads is stacked on the surface opposite to the one surface, A wiring board on which a pattern is formed;
A plurality of metal plugs filled through the through holes and electrically connecting the electrode pads of the plurality of semiconductor chips to the wiring pattern of the wiring board;
And an electrical connection structure of the semiconductor chip. 15. The method of claim 14,
Wherein the plurality of semiconductor chips are collectively formed as a wafer. Preparing a semiconductor chip having electrode pads on one surface thereof;
Stacking a wiring board having through holes corresponding to electrode pads of the semiconductor chip on the semiconductor chip such that electrode pads are exposed through the through holes;
Forming a metal plug electrically connected to a wiring pattern formed on a surface opposite to one surface of the wiring board on which the semiconductor chips are stacked by electrically connecting the electrode pads and the wiring board by filling the through holes, ;
And electrically connecting the semiconductor chip to the semiconductor chip. 17. The method of claim 16, further comprising:
Attaching a supporting substrate to a surface of the semiconductor chip opposite to a surface on which electrode pads are formed;
And electrically connecting the semiconductor chip to the semiconductor chip. 17. The method of claim 16, further comprising:
And stacking the protection substrate on the semiconductor chip with the electrode pads exposed through the exposure holes, wherein the protection substrate is formed with exposure holes corresponding to the electrode pads of the semiconductor chip,
Wherein the wiring board is laminated on the protective substrate so that the exposed holes of the protective substrate and the through holes of the wiring board are communicated with each other. 17. The method according to claim 16, wherein in the step of forming the metal plug,
Wherein the metal plug and the wiring pattern are integrally formed on the wiring board. 17. The method according to claim 16, wherein in the step of forming the metal plug,
Wherein the metal plug is formed by plating or vacuum deposition.
KR1020130150978A 2013-12-05 2013-12-05 Electrical connecting structure and method of semiconductor chip KR101547207B1 (en)

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