JP3882648B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as an IGBT having a very small thickness, which is joined to an insulating substrate on which a circuit pattern is formed by solder or the like.
[0002]
[Prior art]
In a semiconductor device such as an IGBT module, as a technique for improving the trade-off between on-voltage and switching loss, the thickness of the IGBT chip may be reduced.
In recent years, the thickness of the IGBT chip has been considered to be 100 μm to 150 μm for a withstand voltage class of 1000 V or more, and about 50 μm to 80 μm for a withstand voltage class of about 600 V.
[0003]
FIG. 10 is a cross-sectional view of a main part of a conventional semiconductor device. This semiconductor device is a power semiconductor device such as an IGBT module. In this semiconductor device, a heat sink 51, a copper-clad insulating substrate 52 (circuit pattern is formed), and an IGBT chip 53 are joined by solders 57 and 58, and this integrated structure is bonded to a resin-molded case 54. This is the structure.
[0004]
A gel 59 such as silicone gel is sealed in the case 54 for the purpose of protecting the semiconductor chip 53, the wires 56, and the copper-clad insulating substrate 52 from moisture, moisture, and dust. The front surface of the IGBT chip 53 is wire-bonded, and the back surface of the IGBT chip 53 is joined to a circuit pattern (not shown) on the copper-clad insulating substrate 52 with solder 58 to make electrical connection. In the figure, 55 is an external lead-out conductor.
[0005]
11A and 11B are configuration diagrams of a conventional IGBT chip, where FIG. 11A is a plan view of the main part, and FIG. 11B is a cross-sectional view of the main part taken along line YY in FIG. .
The front surface side of the IGBT chip 53 is composed of a gate electrode 62 and an emitter electrode 61, and a junction termination withstand voltage structure 65 covered with a protective film (not shown), and a collector electrode 63 is formed on the back surface side. A large number of cells described in FIG. 12 are formed in the semiconductor substrate 100.
[0006]
FIG. 12 is a cross-sectional view of the main part of the cell formed on the IGBT chip, cut along line XX in FIG.
The IGBT chip 53 has a large number of cells formed on the semiconductor substrate 100. In this cell structure, a p-well region 72 is formed in a surface layer of a semiconductor substrate 100 (for example, silicon), an n-emitter region 73 is formed in the surface layer of the p-well region 72, and the n-emitter region 73 and the semiconductor substrate 100 are formed. A polysilicon gate internal electrode 75 is formed on the p-well region 72 sandwiched between and the semiconductor substrate 100 sandwiched between the p-well regions 72 via a gate insulating film 74. The gate internal electrode 75 and the gate electrode 62 in FIG. 11 are electrically connected.
[0007]
An interlayer insulating film 76 is formed on the gate internal electrode 75, and an emitter electrode 61 is formed on the n emitter region 73. A p collector region 77 is formed on the front surface layer of the semiconductor substrate 100, and a collector electrode 63 is formed thereon. The collector electrode 63 has a multilayer structure of an Al film 81, a Ti film 82, a Ni film 83, and an Au film 84 in order to improve the solder joint with the copper-clad insulating substrate 52 of FIG.
[0008]
The semiconductor substrate 100 sandwiched between the p well region 72 and the p collector region 77 is the n ⁻ drift layer 71.
The thickness of the conventional IGBT chip 53 is about 350 μm, the gate electrode 62 and the emitter electrode 61 are bonded to a wire 56 such as an aluminum wire, and the collector electrode 63 is bonded to the copper-bonded insulating substrate 52 and the solder 58. It was. In this case, since the IGBT chip 53 was sufficiently thick as 350 μm, the amount of warpage of the IGBT chip 11 before mounting was as small as several μm.
[0009]
[Problems to be solved by the invention]
Recently, however, the thickness reduction of the IGBT chip 53 has been studied for the purpose of improving the electrical characteristics of the IGBT chip 53. When the IGBT chip 53 is thinned, when the collector electrode 63 is formed on the back surface of the semiconductor substrate 100, the surface electrode side (emitter electrode side) of the IGBT chip 53 is formed as shown in FIG. It becomes warped greatly in a convex shape.
[0010]
FIG. 14 is a diagram showing the amount of warpage when the thickness of a conventional IGBT chip is reduced. The size of the IGBT chip is 10 mm □, and the thickness is 50 μm to 300 μm. In particular, when the thickness is smaller than 150 μm, the amount of warpage increases rapidly, and the rate of increase in the amount of warpage increases as the thickness decreases, and when the thickness is about 50 μm, the amount of warpage reaches 200 μm.
[0011]
When the amount of warping increases in this way, when the IGBT chip 53 is joined to the copper-clad insulating substrate 52 with the solder 58, the solder layer below the center of the IGBT chip 53 is thick (in the worst case, a void is wound). The bonding strength of the bonding wire is weak, and in actual use (switching), the thermal resistance is deteriorated, the bonding temperature is increased greatly, and the IGBT module has a low power cycle resistance.
[0012]
An object of the present invention is to solve the above-described problems and provide a semiconductor device in which the amount of warpage due to the bimetal effect of a thinned semiconductor chip is suppressed and a method for manufacturing the same.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the thickness of a semiconductor substrate that has a front surface electrode formed on the front surface side of the semiconductor chip and a back surface electrode formed on the back surface side of the semiconductor chip, and that constitutes the semiconductor chip is 150 μm or less. In the semiconductor device, an insulating thick film of 5 μm or more and 50 μm or less is selectively formed on the surface of the semiconductor chip.
[0014]
The insulating thick film may be formed on the outer peripheral portion on the surface side of the semiconductor chip.
The insulating thick film may be selectively formed on the surface electrode.
The insulating thick film may be formed in a band shape on the surface electrode.
Further, in a semiconductor device having a front surface electrode formed on a front surface side of a semiconductor chip and a back surface electrode formed on a rear surface side of the semiconductor chip, the thickness of a semiconductor substrate constituting the semiconductor chip is 150 μm or less. An insulating thick film formed to be 10 μm or more and 50 μm or less on the entire surface of the chip and electrically connected to the surface electrode through an opening formed in the insulating thick film.
[0015]
The metal film may be selectively formed, and the insulating thick film may be formed of polyimide or silicon nitride.
Also, a step of attaching the back side of a wafer having a thickness of 150 μm or less on which a large number of element units are formed to a support substrate, and covering the entire surface side of the wafer with an insulating thick film to a thickness of 5 μm to 50 μm The manufacturing method includes a step, a step of selectively removing the insulating thick film, and a step of dicing the wafer to separate each element unit.
[0016]
Also, a step of attaching the back side of a wafer having a thickness of 150 μm or less on which a large number of element units each having a front electrode and a back electrode of the first layer are formed to a supporting substrate, and an insulating thickness on the entire front side of the wafer Covering the film with a thickness of 5 μm to 50 μm, selectively removing the insulating thick film on the first surface electrode of the element unit, and on the insulating thick film immediately above the surface electrode And a step of forming a second surface electrode and a step of dicing the wafer to separate each element unit.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
1A and 1B show a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of the main part, and FIG. 1B is a cross-sectional view of the main part taken along line YY in FIG. FIG. Here, an IGBT chip constituting a semiconductor device is shown. The internal structure of the semiconductor substrate 100 is the same as FIG. The emitter electrode 2, collector electrode 4, gate electrode 3, and junction termination withstand voltage structure 5 in FIG. 1 correspond to the emitter electrode 61, collector electrode 63, gate electrode 62, and junction termination withstand voltage structure 65 in FIG.
[0018]
A polyimide frame 6, which is an insulating thick film, is formed on the junction termination withstand voltage structure 5 portion of the IGBT chip 1 having the gate electrode 3 and the emitter electrode 2. A collector electrode 4, which is a back electrode, is formed on the back side of the IGBT chip 1. The thickness of the IGBT chip 1 (the thickness of the semiconductor substrate 100) is 150 μm or less, the thickness of the polyimide frame 6 is 5 μm to 50 μm, and the width of the frame 6 is 0.5 mm. By setting the thickness of the polyimide frame 6 within this range, it is possible to suppress warping in a convex shape toward the emitter electrode 2 side of the IGBT chip 1. The insulating thick film may be silicon nitride. In this case, the thickness of the silicon nitride film is preferably about 5 μm to 8 μm. The reason why the thickness of the IGBT chip 1 is set to 150 μm or less as described above is that the amount of warpage increases rapidly as shown in FIG. The lower limit depends on the element breakdown voltage, but is about 50 μm if the 600V class breakdown voltage is maintained.
[0019]
FIG. 2 is a manufacturing method of the semiconductor device of FIG. 1, and FIG. 2A to FIG.
A wafer 200 having a thickness of 50 μm to 150 μm in which a plurality of element units to be the IGBT chip 1 are formed is set on the hot plate 21 (or a constant temperature layer), and a temperature at which the wafer 200 does not warp (an annealing temperature of the back electrode film is 300 ° C. Temperature). A surface electrode 11 of a gate electrode and an emitter electrode is formed on the surface side of the element unit, and a back electrode 12 of a collector electrode is formed on the back surface side (FIG. 5A).
[0020]
Next, a glass substrate 22 having the same linear expansion coefficient as that of silicon is bonded to the back surface of the wafer 200 with a UV tape 23 (a tape that can be peeled off when irradiated with ultraviolet rays). By bonding the wafer 200 to the glass substrate 22, the wafer 200 on which the emitter electrode 2 side of the IGBT chip 1 is warped in a convex shape becomes flat, and even if the temperature of the glass substrate 22 is lowered, the wafer 200 does not warp (same as above). (B).
[0021]
Next, polyimide 13 which is an insulating thick film is coated on the wafer 200 adhered on the glass substrate 22 which has been returned to room temperature ((c) in the figure).
Next, the polyimide 13 coated on the surface of the wafer 200 is cured, and then the polyimide 13 on the outer peripheral portion of the IGBT chip 1 on which the junction termination withstand voltage structure 5 (a nitride film or the like is formed as a protective film) is formed. The polyimide frame 6 is formed by removing polyimide at other locations. The polyimide frame 6 formed on the outer periphery of the IGBT chip 1 functions to suppress warping of the IGBT chip 1. When the frame 6 is thickened, the effect of suppressing warpage is increased. If the thickness of the frame 6 is less than 5 μm, the effect of suppressing warpage is small and impractical. Moreover, since it will twist in IGBT chip | tip 1 when it exceeds 50 micrometers, the thickness of the frame 6 has the preferable range of 5 micrometers-50 micrometers. (Fig. (D))
Next, the wafer 200 is cut by a cutting line 31 by dicing and separated into element units (FIG. 5E), and the element units are removed from the glass substrate 22 to form the IGBT chip 1 (FIG. 5F). )).
[0022]
The polyimide frame 6 formed on the outer peripheral portion of the IGBT chip 1 suppresses the warp of the IGBT chip 1 as described above.
Further, instead of polyimide, a protective film (not shown) formed on the junction termination breakdown voltage structure 5 of the IGBT chip 1 may be used. Usually, this protective film is formed of a silicon nitride film. However, even if the frame 6 is formed by forming this film only on the outer peripheral portion of the IGBT chip 1 by sputtering or vapor deposition a plurality of times and increasing the film thickness. Good. In this case, the film thickness is preferably about 5 μm to 8 μm. Furthermore, the polyimide which is the frame 6 described above may be used as a protective film.
[0023]
FIG. 3 is a diagram showing the relationship between the warpage of the IGBT chip and the film thickness of the polyimide. The size of the IGBT chip is 10 mm □, the thickness is 60 μm, and the width of the polyimide frame around the chip is 0.5 mm. The annealing temperature of the back electrode (collector electrode 4) of the IGBT chip is 325 ° C., and the temperature difference from room temperature is 300 ° C. The measurement temperature of the amount of warpage is 25 ° C.
[0024]
When the polyimide film thickness (frame thickness) is increased, the amount of warpage is suppressed to be small. In order to make the amount of warpage 150 μm or less, the thickness of the polyimide is preferably 7 μm or more. Further, when a silicon nitride film is used instead of polyimide, the film thickness is preferably 5 μm or more. Therefore, the thickness of the insulating thick film (polyimide film, silicon nitride film), that is, the thickness of the frame 6 is preferably 5 μm or more. In the case of polyimide, the thickness is preferably 10 μm or more.
[0025]
When the polyimide film thickness exceeds 60 μm, the warpage decreases, but as shown in FIG. 4 to be described later, the twisting phenomenon occurs at the corner portion of the IGBT chip, so that the IGBT chip is easily cracked during bonding. Become. Therefore, the film thickness of polyimide is desirably 50 μm or less.
FIG. 4 is a diagram showing the result of analysis by simulating thermal deformation of an IGBT chip by a finite element method (FEM) with contour lines. This analysis model (using a shell element) simulating an IGBT chip was performed as a ¼ model, which was divided into two parts in the vertical and horizontal directions using the symmetry of the IGBT chip. The center of the IGBT chip is the portion where the warp is maximum in the figure.
[0026]
The size of the IGBT chip is 10 mm □, the thickness is 60 μm, and the temperature difference in the process is calculated as ΔT = −300 ° C. (25 ° C.-325 ° C.), and the width of the polyimide frame 6 is 0. The thickness of the polyimide frame is shown by three contour maps of 20 μm (FIG. (A)), 40 μm (FIG. (B)) and 80 μm (FIG. (C)). In the case of 20 μm ((a) in the figure), the warp is 123 μm, in the case of 40 μm ((b) in the figure), the warp is 77 μm and in the case of 80 μm ((c) in the same figure), the warp is 40 μm. Further, when the thickness is 80 μm, the corner portion is twisted. Although not shown in the figure, this twist occurs when the thickness exceeds 50 μm. Therefore, as described above, the thickness of the frame is preferably 50 μm or less.
[0027]
FIGS. 5A and 5B are plan views of the main part of the semiconductor device according to the second embodiment of the present invention. FIG. 5A shows a case where one beam is used, and FIG. 5B shows a case where the beam is formed in a cross shape. In addition to the frame 6 in FIG. 1, the beams 7 and 8 are formed of band-shaped polyimide so as to connect the edge portions of the IGBT chip 1 facing the IGBT chip 1, thereby further reducing the amount of warpage of the IGBT chip 1 than in FIG. It becomes possible to do. The method for forming the beams 7 and 8 can be the same as that in the first embodiment. The gate electrode 3 and the emitter electrode 2 at a portion where the polyimide beams 7 and 8 are not formed (an opening portion of the polyimide film) serve as a bonding pad, and the bonding wire 56 shown in FIG. 10 is connected.
[0028]
FIG. 6 is a plan view of the main part of the semiconductor device according to the third embodiment of the present invention. In addition to the frame 6 in FIG. 1, it is possible to further reduce the amount of warping of the IGBT chip 1 by forming the beam 9 with a strip-shaped polyimide so as to connect opposite corner portions of the IGBT chip 1. The beam 9 can be formed by the same method as in the first embodiment.
FIG. 7 is a fragmentary plan view of the semiconductor device according to the third embodiment of the present invention. In addition to the frame 6 in FIG. 1, the warpage amount of the IGBT chip 1 can be further reduced by forming the beam 10 with a band-shaped polyimide radially from the center of the surface of the IGBT chip 1. The beam 10 can be formed by the same method as in the first embodiment.
[0029]
As described above, by forming the beams 7 to 10 with the polyimide on the surface side of the IGBT chip 1 and with the frame 6 on the outer peripheral portion and with the strip-like polyimide so as to connect the opposing edge portion or corner portion, the bimetal effect is achieved. The amount of warpage of the IGBT chip 1 can be reduced, defects in the assembly process can be suppressed, and a high-quality semiconductor device can be provided.
8A and 8B show a semiconductor device according to a fifth embodiment of the present invention. FIG. 8A is a plan view of the main part, and FIG. 8B is a cross-sectional view of the main part taken along line YY in FIG. FIG. Here, an IGBT chip constituting a semiconductor device is shown.
[0030]
A first-layer gate electrode (formed immediately below the second-layer gate electrode 43) is formed as an insulating thick film over the entire surface side of the IGBT chip 1 on which the first-layer emitter electrode 2 is formed on the surface side. The polyimide 41 is covered. Contact holes 44 are respectively opened in the polyimide 41 on the first-layer gate electrode and the first-layer emitter electrode 2, and the first-layer gate electrode and the first-layer emitter electrode 2 correspond to the polyimide 41. As described above, the second-layer gate electrode 43 and the second-layer emitter electrode 42 are formed of a metal film. The second-layer gate electrode 43 and the first-layer gate electrode, the second-layer emitter electrode 42 and the first-layer emitter electrode 2 are electrically connected through the contact hole 44.
[0031]
Thus, by covering the entire surface with polyimide 41 and forming a metal film thereon, the effect of suppressing the warpage of the wafer is further increased than in the above-described embodiment. Also in this case, the thickness of the polyimide is in the range of 5 μm to 10 μm, and the thickness of the second-layer gate electrode 43 and the second-layer emitter electrode 42 is 0.1 μm, for example, when formed of a Ni film. The amount of warpage can be almost eliminated.
[0032]
The insulating thick film may be a silicon nitride film instead of polyimide. In this case, the thickness of the silicon nitride film is preferably about 5 μm to 8 μm.
FIG. 9 shows a method of manufacturing the semiconductor device of FIG. 8, and FIGS. 9A to 9E are cross-sectional views of the main part manufacturing process shown in the order of steps. Since the manufacturing process is the same as that up to FIG. 2C, only the subsequent processes are described.
[0033]
The polyimide 41 coated on the entire surface of the wafer 200 is cured ((a) in the figure).
Next, a contact hole 44 is opened in the polyimide 41 on the surface electrode 11 of the first layer ((b) in the figure).
Next, the second surface electrode 42 is formed on the polyimide on the first surface electrode 11 (FIG. 2C).
[0034]
Next, the wafer 200 is diced along a cutting line 31 (FIG. (D)), separated into element units, and each element unit is removed from the glass substrate 22 to form the IGBT chip 1 (FIG. (E)). .
[0035]
【The invention's effect】
According to this invention, the warp of the semiconductor chip due to the bimetal effect can be suppressed by forming the frame with the insulating thick film on the outer peripheral portion on the surface side (emitter electrode side) of the semiconductor chip.
Furthermore, the warp of the semiconductor chip due to the bimetal effect can be suppressed by forming the beam so as to connect the frames.
[0036]
Further, the warp of the semiconductor chip can be further suppressed by covering the surface side of the semiconductor chip with an insulating thick film and a metal film.
In this way, by suppressing the warpage of the semiconductor chip, it is possible to suppress the bonding failure when the semiconductor chip is bonded to the circuit pattern and the chip failure during wire bonding.
[0037]
As a result, it is possible to stabilize the bonding state of the semiconductor chip with the conductive film-bonded insulating substrate having a pattern formed of a metal such as copper, and provide a highly reliable semiconductor device and a method for manufacturing the same.
[Brief description of the drawings]
1A is a plan view of a main part of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view of the main part taken along line YY of FIG. (A) to (f) are main part process cross-sectional views shown in the order of steps in the method of manufacturing a semiconductor device of FIG. 3 [FIG. 3] A diagram showing the relationship between the warpage of the IGBT chip and the film thickness of the polyimide [FIG. FIG. 5 is a plan view of a principal part of a semiconductor device according to a second embodiment of the present invention, in which a result of an analysis simulating thermal deformation of an IGBT chip by the FEM method (FEM) is shown. FIG. FIG. 6 is a plan view of the main part of the semiconductor device according to the third embodiment of the present invention. FIG. 7 is a plan view of the semiconductor device according to the third embodiment of the present invention. FIG. 8 is a plan view of a semiconductor device according to a fifth embodiment of the present invention, (a) is a plan view of the main part, and (b) is cut along line YY in (a). FIG. 9 is a method for manufacturing the semiconductor device of FIG. 8, wherein (a) to (e) are cross-sectional views of the main part manufacturing process shown in the order of the processes. FIG. 11A and 11B are configuration diagrams of a conventional IGBT chip, where FIG. 12A is a plan view of the main part, and FIG. 11B is a cross-sectional view of the main part taken along line YY of FIG. FIG. 13 is a cross-sectional view of the principal part of a cell formed on an IGBT chip cut by X-ray. FIG. 13 is a view showing a warp state of the IGBT chip. FIG. 14 is a view showing a warp amount when the thickness of the conventional IGBT chip is reduced. [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 IGBT chip | tip 2 Emitter electrode 3 Gate electrode 4 Collector electrode 5 Junction termination pressure | voltage resistant structure 6 Frame 7-10 Beam 11 Front surface electrode 12 Back surface electrode 13, 41 Polyimide 21 Hotplate 22 Glass substrate 23 UV tape 42 Second layer emitter electrode 43 Second layer gate electrode 44 Contact hole 100 Semiconductor substrate 200 Wafer

Claims (9)

In a semiconductor device having a front surface electrode formed on a front surface side of a semiconductor chip and a back surface electrode formed on a rear surface side of the semiconductor chip, wherein a semiconductor substrate constituting the semiconductor chip has a thickness of 150 μm or less.
A semiconductor device, wherein an insulating thick film of 5 μm or more and 50 μm or less is selectively formed on a surface of a semiconductor chip. The semiconductor device according to claim 1, wherein the insulating thick film is formed on an outer peripheral portion on a surface side of a semiconductor chip. The semiconductor device according to claim 1, wherein the insulating thick film is selectively formed on a surface electrode. The semiconductor device according to claim 3, wherein the insulating thick film is formed in a band shape on the surface electrode. In a semiconductor device having a front surface electrode formed on a front surface side of a semiconductor chip and a back surface electrode formed on a rear surface side of the semiconductor chip, wherein a semiconductor substrate constituting the semiconductor chip has a thickness of 150 μm or less.
An insulating thick film formed on the entire surface of the semiconductor chip to have a thickness of 5 μm or more and 50 μm or less, and a metal film electrically connected to the surface electrode through an opening formed in the insulating thick film. A featured semiconductor device. 6. The semiconductor device according to claim 5, wherein the metal film is a selectively formed metal film. The semiconductor device according to claim 1, wherein the insulating thick film is made of polyimide or silicon nitride. A step of attaching a back side of a wafer having a thickness of 150 μm or less on which a large number of element units are formed to a support substrate; a step of covering an entire surface of the wafer with an insulating thick film to a thickness of 5 μm to 50 μm; A method of manufacturing a semiconductor device, comprising: a step of selectively removing the insulating thick film; and a step of dicing the wafer to separate each element unit. A step of attaching the back side of a wafer having a thickness of 150 μm or less on which a large number of element units each having a front electrode and a back electrode of the first layer are formed to a support substrate; and an insulating thick film over the entire front side of the wafer A step of covering 5 μm to 50 μm, a step of selectively removing the insulating thick film on the first surface electrode of the element unit, and 2 on the insulating thick film immediately above the surface electrode. A method of manufacturing a semiconductor device, comprising: forming a surface electrode of a layer; and a step of dicing the wafer to separate each element unit.

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