JPH0758112A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0758112A
JPH0758112A JP20631693A JP20631693A JPH0758112A JP H0758112 A JPH0758112 A JP H0758112A JP 20631693 A JP20631693 A JP 20631693A JP 20631693 A JP20631693 A JP 20631693A JP H0758112 A JPH0758112 A JP H0758112A
Authority
JP
Japan
Prior art keywords
electrode
bump electrode
semiconductor substrate
bump
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20631693A
Other languages
Japanese (ja)
Inventor
Daisuke Kitawaki
大輔 北脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP20631693A priority Critical patent/JPH0758112A/en
Publication of JPH0758112A publication Critical patent/JPH0758112A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To form a bump electrode for reducing the occurrence of thermal stresses by forming a bump electrode on an electrode pad by dividing it into a plurality of segments. CONSTITUTION:A metal layer is vapor-deposited on an insulation film 3 where an opening 2 is formed, the metal layer is etching-removed leaving the region covering the opening 2 by using a resist film thereby forming an electrode pad 4. Next, a resist film 7 having the opening which divides the electrode pad 4 into four pieces is pattern-formed, and a bump electrode is grown by plating at four places on the electrode pad 4, and a bump electrode 5 divided into four is formed. And after removing the resist film 7, a rear electrode 6 is formed by spattering on the lower surface of a semiconductor substrate 1. By doing this, thermal stresses acting to the portion between the semiconductor substrate and bump electrode can be relaxed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、よ
り詳細にはバンプ電極を有する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having bump electrodes.

【0002】[0002]

【従来の技術】従来、この種の半導体装置、例えば図5
に示すようなダイオード素子21は、素子が形成された
半導体基板22上に酸化シリコン等の絶縁膜23が電極
を形成すべき領域を開口部として形成され、上記開口部
を覆うように銀、金、チタン等の金属層からなる電極パ
ッド24が形成され、上記電極パッド24上に銀、半田
等からなるバンプ電極25が形成され、一方、上記半導
体基板22の下面に銀、金、ニッケル等からなる裏面電
極26が形成されると言った構造を有する。
2. Description of the Related Art Conventionally, a semiconductor device of this type, for example, FIG.
In the diode element 21 as shown in FIG. 3, an insulating film 23 of silicon oxide or the like is formed as an opening on a semiconductor substrate 22 on which the element is formed and an opening is formed. , The electrode pad 24 made of a metal layer such as titanium is formed, and the bump electrode 25 made of silver, solder or the like is formed on the electrode pad 24, while the lower surface of the semiconductor substrate 22 is made of silver, gold, nickel or the like. The back electrode 26 is formed.

【0003】上記のようなダイオード素子21は例え
ば、図6に示すように、一対の外部引き出し用のリード
端子27a,27bに半田層28a,28bを介して狭
持され、これを上記リード端子27a,27bの外方端
部を除いて樹脂モールドされて組み立てられる。即ち、
ダイオード素子21のバンプ電極25及び裏面電極26
は、それぞれ上記半田層28a及び28bを介して上記
リード端子27a及び27bに接続されている。
For example, as shown in FIG. 6, the diode element 21 as described above is sandwiched between a pair of lead terminals 27a and 27b for external extraction via solder layers 28a and 28b, and the lead terminals 27a and 27b. , 27b except the outer ends thereof, which are resin-molded and assembled. That is,
The bump electrode 25 and the back surface electrode 26 of the diode element 21.
Are connected to the lead terminals 27a and 27b via the solder layers 28a and 28b, respectively.

【0004】上記ダイオード素子21をリード端子27
a,27bに接続する方法としては、一般に、先ずリー
ド端子27bの所定位置に半田ペーストを塗布し、該半
田ペースト上にダイオード素子21をその裏面電極26
を向けてダイボンディングし、そして上記リード端子2
7aの所定位置に半田ペーストを塗布し、これを上記半
導体基板21の上面から重ね合わせ上記半田ペーストと
上記バンプ電極25とを重ね合わせてた後、キュアして
半田ペーストを固着することにより行われる。
The diode element 21 is connected to the lead terminal 27.
As a method of connecting to the a and 27b, generally, a solder paste is first applied to a predetermined position of the lead terminal 27b, and the diode element 21 is placed on the solder paste and the back electrode 26 thereof.
Die-bonding, and then the lead terminal 2
This is performed by applying a solder paste to a predetermined position of 7a, stacking it from the upper surface of the semiconductor substrate 21 and stacking the solder paste and the bump electrode 25, and then curing and fixing the solder paste. .

【0005】[0005]

【発明が解決しようとする課題】しかしながら、半導体
基板22に対する上記バンプ電極25及び電極パッド2
4の電極層の形成面積(接触面積)が大きくなるのと略
比例して、電極層と半導体基板22との熱膨張率の違い
による熱応力が増大することとなる。実際は電極パッド
24の層厚は非常に薄くしかもバンプ電極25の厚さに
比べて遙かに薄いために事実上上記バンプ電極25の形
成面積が大きくなるのと略比例して、温度サイクル試験
や高温下での使用等において、ダイオード素子21に過
度に熱ストレスがかかった場合、上記バンプ電極25と
上記半導体基板22との熱膨張率の違いにより熱応力が
生じ、上記バンプ電極25と半導体基板22との接触界
面においてバンプ電極25の形成位置のズレやクラック
が生じる危険性が高くなるという問題がある。
However, the bump electrode 25 and the electrode pad 2 for the semiconductor substrate 22 are not provided.
In proportion to the increase in the formation area (contact area) of the electrode layer of No. 4, the thermal stress due to the difference in the coefficient of thermal expansion between the electrode layer and the semiconductor substrate 22 increases. Actually, the layer thickness of the electrode pad 24 is very thin and much smaller than the thickness of the bump electrode 25, so that the formation area of the bump electrode 25 is substantially increased in proportion to the temperature cycle test and When the diode element 21 is subjected to excessive thermal stress during use at high temperatures, thermal stress is generated due to the difference in coefficient of thermal expansion between the bump electrode 25 and the semiconductor substrate 22, and the bump electrode 25 and the semiconductor substrate 22. There is a problem that there is a high risk that a position where the bump electrode 25 is formed or a crack is generated at the contact interface with 22.

【0006】一方、上記のようにバンプ電極25を半田
層28aを介してリード端子27aに接続する場合、上
記バンプ電極25と上記半田ペーストとの接触時、半田
ペーストのキュア時等の組立工程において、次のような
問題が生じるのである。上記ダイオード素子21の上記
バンプ電極25の周縁に露出している絶縁膜23上に
は、例えば上記電極パッド24の形成時に電極パッド2
4の材質である金属が付着したり、複数個のダイオード
素子21が形成された半導体ウエハーを個々のダイオー
ド素子21にダイシングにより分割する時に上記裏面電
極26の切り屑が付着する等して、金属系の異物が付着
する危険性がある。上記絶縁膜23上に上記金属系の異
物が存在すると、上記ダイオード素子21のバンプ電極
25を半田ペーストを用いてリード端子27aに接続す
る時、不要な部分である上記絶縁膜23上の上記異物に
半田が付着してこれがダイオード素子21側面にまで及
ぶとショート不良を招来させる危険性があるのである。
On the other hand, when the bump electrode 25 is connected to the lead terminal 27a through the solder layer 28a as described above, in the assembly process such as contact between the bump electrode 25 and the solder paste, curing of the solder paste, etc. However, the following problems occur. On the insulating film 23 exposed on the periphery of the bump electrode 25 of the diode element 21, for example, the electrode pad 2 is formed when the electrode pad 24 is formed.
The metal as the material of No. 4 adheres, or the chips of the back surface electrode 26 adhere when dividing the semiconductor wafer having a plurality of diode elements 21 into individual diode elements 21 by dicing. There is a risk of foreign matter from the system. When the metal-based foreign matter is present on the insulating film 23, the foreign matter on the insulating film 23, which is an unnecessary portion, is connected when the bump electrode 25 of the diode element 21 is connected to the lead terminal 27a by using a solder paste. If the solder adheres to the side surface of the diode element 21 and a short circuit occurs, there is a risk of causing a short circuit defect.

【0007】そこで、上記問題を軽減するために、上記
バンプ電極25を高く形成して上記絶縁膜23と上記半
田層28aとの距離を長くし、半田が上記絶縁膜23に
付着するのを低減することが考えられる。
Therefore, in order to reduce the above problem, the bump electrode 25 is formed high to increase the distance between the insulating film 23 and the solder layer 28a to reduce the adhesion of solder to the insulating film 23. It is possible to do it.

【0008】しかしながら、バンプ電極25を高く形成
すると、上述したようなバンプ電極25と半導体基板2
2との熱膨張率の違いにより発生する熱応力が更に大き
くなり、バンプ電極25と半導体基板22との接触界面
においてバンプ電極の形成位置のズレやクラックが生じ
る危険性が一層高くなり、上記異物の問題を解消する程
度にまでバンプ電極25を高くすることができないので
ある。
However, when the bump electrode 25 is formed high, the bump electrode 25 and the semiconductor substrate 2 as described above are formed.
The thermal stress generated due to the difference in the coefficient of thermal expansion from that of No. 2 is further increased, and the risk of the displacement or crack of the bump electrode formation position at the contact interface between the bump electrode 25 and the semiconductor substrate 22 is further increased. The bump electrode 25 cannot be made high enough to solve the above problem.

【0009】本発明は、半導体基板上に熱応力の発生を
軽減できるバンプ電極の形成技術を提供することを目的
とする。
An object of the present invention is to provide a bump electrode forming technique capable of reducing the occurrence of thermal stress on a semiconductor substrate.

【0010】[0010]

【課題を解決するための手段】本発明者は、上記目的を
達成すべく鋭意研究を重ねた結果、半導体装置における
バンプ電極を、半導体基板上に形成された単一の電極パ
ッド上に複数に分割して形成するときは、電極層と半導
体基板間に作用する熱応力を効果的に緩和でき、温度サ
イクル試験や動作時に上記熱応力による不良を一段と低
減できることを見出した。
As a result of intensive studies to achieve the above object, the present inventor has made a plurality of bump electrodes in a semiconductor device on a single electrode pad formed on a semiconductor substrate. It was found that the thermal stress acting between the electrode layer and the semiconductor substrate can be effectively relaxed when the electrodes are divided and formed, and the defects due to the thermal stress can be further reduced during the temperature cycle test or the operation.

【0011】即ち、本発明は、半導体基板上に形成され
た電極パッド上にバンプ電極を有する半導体装置におい
て、上記電極パッド上のバンプ電極が複数個に分割され
形成されていることを特徴とする半導体装置に係るもの
である。
That is, according to the present invention, in a semiconductor device having a bump electrode on an electrode pad formed on a semiconductor substrate, the bump electrode on the electrode pad is divided into a plurality of parts. The present invention relates to a semiconductor device.

【0012】[0012]

【作用】複数個に分割して形成したバンプ電極を一つの
電極として用いるので、上記複数個に分割されたバンプ
電極の個々の半導体基板との接触面積は小さくなる。従
って、電極として外部端子、配線等との接続に十分な面
積を保持しつつ、熱ストレスがかかったときにバンプ電
極と半導体基板間に作用する熱応力は上記複数個のバン
プ電極に分散され、その結果、個々のバンプ電極に作用
する熱応力は該個々のバンプ電極が吸収できる程度に小
さくできる。
Since the bump electrode formed by dividing into a plurality of pieces is used as one electrode, the contact area of the bump electrode divided into a plurality of pieces with each semiconductor substrate becomes small. Therefore, while maintaining an area sufficient for connection with an external terminal, wiring, etc. as an electrode, the thermal stress acting between the bump electrode and the semiconductor substrate when a thermal stress is applied is dispersed to the plurality of bump electrodes, As a result, the thermal stress acting on each bump electrode can be made small enough to be absorbed by each bump electrode.

【0013】[0013]

【実施例】以下実施例を示し、本発明の特徴とするとこ
ろをより詳細に説明する。
EXAMPLES The features of the present invention will be described in more detail below with reference to examples.

【0014】図1及び図2にダイオード素子におけるバ
ンプ電極を4つに分割して形成したときの実施例を示
す。これら図に示すように、本実施例のダイオード素子
は、素子が形成された半導体基板1と、該半導体基板1
上に形成されバンプ電極を形成すべき領域に対応する開
口部2を有する酸化シリコン等の絶縁膜3と、上記絶縁
膜3の開口部2を覆うように形成されたバンプ電極の下
地となる銀、金、チタン、ニッケル等の金属層からなる
電極パッド4と、該電極パッド4上に4つに分割形成さ
れたバンプ電極5と、上記半導体基板1の下面に形成さ
れた銀、金、ニッケル等の金属からなる裏面電極6とを
有する。
FIGS. 1 and 2 show an embodiment in which the bump electrode in the diode element is divided into four and formed. As shown in these figures, the diode element of the present embodiment includes a semiconductor substrate 1 on which the element is formed, and the semiconductor substrate 1
An insulating film 3 made of silicon oxide or the like having an opening 2 corresponding to a region where a bump electrode is to be formed, and silver as a base of the bump electrode formed so as to cover the opening 2 of the insulating film 3. Electrode pads 4 made of a metal layer of gold, titanium, nickel, etc., four bump electrodes 5 formed on the electrode pads 4, and silver, gold, nickel formed on the lower surface of the semiconductor substrate 1. And a back electrode 6 made of a metal such as.

【0015】上記ダイオード素子は、例えば次のように
して製造することができる。図3(a)に示すように、
半導体基板1上に熱酸化或いはCVD法により絶縁膜3
を形成し、該絶縁膜3上に所定のパターンのレジスト膜
を形成し、上記絶縁膜3をエッチングして開口部2を形
成し、上記レジスト膜を除去する。
The above diode element can be manufactured, for example, as follows. As shown in FIG.
An insulating film 3 is formed on the semiconductor substrate 1 by thermal oxidation or a CVD method.
Is formed, a resist film having a predetermined pattern is formed on the insulating film 3, the insulating film 3 is etched to form the opening 2, and the resist film is removed.

【0016】次に、図3(b)に示すように、上記開口
部2が形成された絶縁膜3上に金属層を蒸着し、該金属
層を、レジスト膜を用いて上記開口部2を覆う領域を残
してエッチング除去して電極パッド4を形成する。
Next, as shown in FIG. 3B, a metal layer is vapor-deposited on the insulating film 3 in which the opening 2 is formed, and the opening 2 is formed by using the metal layer with a resist film. The electrode pad 4 is formed by etching away the region to cover.

【0017】次に、図3(c)に示すように、上記電極
パッド4を4分割する開口部を有するレジスト膜7(図
4参照)をパターン形成し、図3(d)に示すように、
上記電極パッド4上の4箇所にバンプ電極をメッキ成長
させて4つに分割したバンプ電極5を形成する。そし
て、上記レジスト膜7除去後、上記半導体基板1の下面
に裏面電極6をスパッタリング等により形成する。
Next, as shown in FIG. 3 (c), a resist film 7 (see FIG. 4) having an opening for dividing the electrode pad 4 into four is patterned, and as shown in FIG. 3 (d). ,
Bump electrodes are plated and grown at four locations on the electrode pad 4 to form four divided bump electrodes 5. Then, after removing the resist film 7, the back surface electrode 6 is formed on the lower surface of the semiconductor substrate 1 by sputtering or the like.

【0018】上記実施例では、バンプ電極を4つに分割
して形成したが、バンプ電極の分割数はバンプ電極の形
成面積及び形成高さにより適宜選択すればよい。また、
上記では、ダイオード素子に適用した場合について説明
したが、本発明はこれに限らず、IC、ハイブリッドI
C、トランジスタ等の半導体装置全般に亘って適用する
ことができる。
In the above embodiment, the bump electrode is divided into four, but the number of divisions of the bump electrode may be appropriately selected depending on the area and height of the bump electrode. Also,
Although the case where the present invention is applied to a diode element has been described above, the present invention is not limited to this, and an IC, a hybrid I
It can be applied to all semiconductor devices such as C and transistors.

【0019】[0019]

【発明の効果】本発明によれば、半導体基板とバンプ電
極間に作用する熱応力を緩和できるので、半導体装置に
熱ストレスが及んだ場合に、バンプ電極と半導体基板間
にバンプ電極の形成位置のズレやクラックが生じること
を極めて低減できる。
According to the present invention, since the thermal stress acting between the semiconductor substrate and the bump electrode can be relaxed, when the semiconductor device is subjected to the thermal stress, the bump electrode is formed between the bump electrode and the semiconductor substrate. It is possible to extremely reduce the occurrence of misalignment and cracks.

【0020】また、分割された個々のバンプ電極の半導
体基板との接触面積を小さくでき、熱応力を分散できる
ので、バンプ電極の高さを従来よりも高く形成すること
ができる。
Further, since the contact area of each divided bump electrode with the semiconductor substrate can be reduced and the thermal stress can be dispersed, the height of the bump electrode can be made higher than in the prior art.

【0021】更に、バンプ電極を分割形成しているの
で、該バンプ電極を半田等を用いて外部端子等に接続す
る場合、バンプ電極間に半田等が流れ込み接続強度が向
上し、安定な接続を行うことができる。
Furthermore, since the bump electrodes are formed separately, when connecting the bump electrodes to an external terminal or the like by using solder or the like, solder or the like flows between the bump electrodes to improve the connection strength and to ensure a stable connection. It can be carried out.

【0022】このように、本発明の半導体装置は、バン
プ電極を高くして熱ストレスに耐え得る、構造的に極め
て耐熱性に優れたものである。
As described above, the semiconductor device of the present invention is structurally extremely excellent in heat resistance and capable of withstanding the thermal stress by raising the bump electrode.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例のダイオード素子を示す断面図である。FIG. 1 is a cross-sectional view showing a diode element of an example.

【図2】図1の上面図である。FIG. 2 is a top view of FIG.

【図3】図1のダイオード素子の製造工程を説明する断
面図である。
FIG. 3 is a cross-sectional view illustrating a manufacturing process of the diode element of FIG.

【図4】実施例で用いるバンプ電極形成用レジストパタ
ーンの平面図である。
FIG. 4 is a plan view of a bump electrode forming resist pattern used in an example.

【図5】従来のダイオード素子の断面図である。FIG. 5 is a cross-sectional view of a conventional diode element.

【図6】従来のダイオード素子をリード端子に接続した
状態を示す断面図である。
FIG. 6 is a cross-sectional view showing a state in which a conventional diode element is connected to a lead terminal.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 開口部 3 絶縁膜 4 電極パッド 5 バンプ電極 6 裏面電極 7 レジスト膜 1 Semiconductor Substrate 2 Opening 3 Insulating Film 4 Electrode Pad 5 Bump Electrode 6 Backside Electrode 7 Resist Film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成された電極パッド上
にバンプ電極を有する半導体装置において、上記電極パ
ッド上のバンプ電極が複数個に分割され形成されている
ことを特徴とする半導体装置。
1. A semiconductor device having a bump electrode on an electrode pad formed on a semiconductor substrate, wherein the bump electrode on the electrode pad is divided into a plurality of parts and formed.
JP20631693A 1993-08-20 1993-08-20 Semiconductor device Pending JPH0758112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20631693A JPH0758112A (en) 1993-08-20 1993-08-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20631693A JPH0758112A (en) 1993-08-20 1993-08-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0758112A true JPH0758112A (en) 1995-03-03

Family

ID=16521285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20631693A Pending JPH0758112A (en) 1993-08-20 1993-08-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0758112A (en)

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US6111628A (en) * 1997-03-06 2000-08-29 Sharp Kabushiki Kaisha Liquid crystal display device including plural bump electrodes
US6525422B1 (en) 1997-01-20 2003-02-25 Sharp Kabushiki Kaisha Semiconductor device including bump electrodes
JP2005265750A (en) * 2004-03-22 2005-09-29 Elpida Memory Inc Probe card
JP2006098637A (en) * 2004-09-29 2006-04-13 Seiko Epson Corp Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus
JP2010278139A (en) * 2009-05-27 2010-12-09 Panasonic Corp Semiconductor device and method for manufacturing the same
JP2014212265A (en) * 2013-04-19 2014-11-13 新電元工業株式会社 Semiconductor device and method of manufacturing the same
JP2018195664A (en) * 2017-05-16 2018-12-06 富士通株式会社 Semiconductor device and method of manufacturing the same

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US6525422B1 (en) 1997-01-20 2003-02-25 Sharp Kabushiki Kaisha Semiconductor device including bump electrodes
US6933607B2 (en) 1997-01-20 2005-08-23 Sharp Kabushiki Kaisha Semiconductor device with bumps on electrode pads oriented in given direction
US7005741B2 (en) 1997-01-20 2006-02-28 Sharp Kabushiki Kaisha Liquid crystal display device and/or circuit substrate including bump electrodes and electrode pads
US6111628A (en) * 1997-03-06 2000-08-29 Sharp Kabushiki Kaisha Liquid crystal display device including plural bump electrodes
JP2005265750A (en) * 2004-03-22 2005-09-29 Elpida Memory Inc Probe card
JP2006098637A (en) * 2004-09-29 2006-04-13 Seiko Epson Corp Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus
JP4539268B2 (en) * 2004-09-29 2010-09-08 セイコーエプソン株式会社 Mounting structure
JP2010278139A (en) * 2009-05-27 2010-12-09 Panasonic Corp Semiconductor device and method for manufacturing the same
JP2014212265A (en) * 2013-04-19 2014-11-13 新電元工業株式会社 Semiconductor device and method of manufacturing the same
JP2018195664A (en) * 2017-05-16 2018-12-06 富士通株式会社 Semiconductor device and method of manufacturing the same

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