JP3196821B2 - Resin-sealed circuit device - Google Patents
Resin-sealed circuit deviceInfo
- Publication number
- JP3196821B2 JP3196821B2 JP01790597A JP1790597A JP3196821B2 JP 3196821 B2 JP3196821 B2 JP 3196821B2 JP 01790597 A JP01790597 A JP 01790597A JP 1790597 A JP1790597 A JP 1790597A JP 3196821 B2 JP3196821 B2 JP 3196821B2
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- support plate
- protective resin
- semiconductor element
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【０００１】[0001]
【産業上の利用分野】本発明は、放熱性を有する金属支
持板上に半導体素子及び回路基板が固着され、これ等が
樹脂で封止された形式の樹脂封止型回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed type circuit device in which a semiconductor element and a circuit board are fixed on a metal support plate having heat radiation, and these are sealed with a resin.
【０００２】[0002]
【従来の技術】従来の樹脂封止型回路装置（ハイブリッ
ドＩＣ）は、図１に示すように、放熱性を有する金属製
の支持板１と、この支持板１上に導電性接合材としての
半田２で固着されたチップ状の半導体素子３と、支持板
１上に導電性接合材としての半田４で固着された回路基
板５と、この回路基板５上に固着された回路素子として
のフリップチップ６と、回路基板５上の配線導体７と半
導体素子３とを接続するリード細線８と、回路基板５上
の配線導体９と支持板１に非連結の外部リード１０との
間を接続する内部リード細線１１と、半導体素子３を被
覆するように配置されたポリイミド系樹脂から成る第１
の保護樹脂層１２と、回路素子６、配線導体７、９及び
回路基板５の上面を被覆するように配置されたシリコー
ン樹脂から成る第２の保護樹脂層１３と、第１及び第２
の保護樹脂層１２、１３、支持板１、及び外部リード１
０の一部を被覆するように配置されたエポキシ系樹脂か
ら成る樹脂封止体１４とによって構成されている。な
お、半導体素子３は例えばトランジスタであって、ＰＮ
接合を含む半導体基板、この基板の下面及び上面に形成
された金属電極等を含むが、図１ではこれ等の詳細は省
略されている。また、フリップチップ６は板状本体部６
ａとバンプ電極６ｂとを有し、バンプ電極６ｂが回路基
板５の配線導体（図示せず）に半田で固着されている。
また、回路基板５の下面には金属層が設けられている
が、図１では省略されている。また、支持板１から導出
された連結外部リード１ａが設けられ、複数本の非連結
外部リード１０が連結外部リード１ａに平行に配置され
ている。2. Description of the Related Art As shown in FIG. 1, a conventional resin-encapsulated circuit device (hybrid IC) includes a metal support plate 1 having heat radiation and a conductive bonding material on the support plate 1 as a conductive bonding material. A chip-shaped semiconductor element 3 fixed by solder 2, a circuit board 5 fixed on a support plate 1 by solder 4 as a conductive bonding material, and a flip as a circuit element fixed on the circuit board 5 The chip 6, the fine lead wires 8 connecting the wiring conductors 7 on the circuit board 5 and the semiconductor elements 3 and the wiring conductors 9 on the circuit board 5 and the external leads 10 not connected to the support plate 1 are connected. A first lead made of a polyimide resin disposed so as to cover the inner lead thin wire 11 and the semiconductor element 3;
A second protective resin layer 13 made of silicone resin disposed so as to cover the circuit element 6, the wiring conductors 7 and 9, and the upper surface of the circuit board 5;
Protective resin layers 12, 13, support plate 1, and external lead 1
And a resin sealing body 14 made of an epoxy resin disposed so as to cover a part of the “0”. Note that the semiconductor element 3 is, for example, a transistor,
It includes a semiconductor substrate including a junction, metal electrodes formed on the lower and upper surfaces of the substrate, and the like, but these details are omitted in FIG. The flip chip 6 is a plate-shaped main body 6.
a and a bump electrode 6b, and the bump electrode 6b is fixed to a wiring conductor (not shown) of the circuit board 5 by soldering.
Further, a metal layer is provided on the lower surface of the circuit board 5, but is omitted in FIG. A connected external lead 1a led from the support plate 1 is provided, and a plurality of unconnected external leads 10 are arranged in parallel to the connected external lead 1a.
【０００３】[0003]
【発明が解決しようとする課題】ところで、図１の樹脂
封止型回路装置において、図２に拡大図示するように樹
脂封止体１４と第２の保護樹脂層１３との間にすき間１
５が生じ、これにより半導体素子３の樹脂封止体１４に
よる押え付けが弱くなり、温度サイクル試験（低温と高
温との温度サイクルを繰返して回路装置に加える試験）
等によって半田２にクラックが生じることがある。この
理由を更に詳しく説明する。回路基板５はアルミナ（酸
化アルミニウム）を主成分としたセラミック板であり、
その線膨張係数は７ppm オーダである。これに対して、
エポキシ系樹脂から成る樹脂封止体１４の線膨張係数は
１７〜２０ppm と大きい。このため、温度サイクル（高
温から低温への移行時）に伴う熱収縮量は、樹脂封止体
１４の方が回路基板５よりも大きい。従って、温度サイ
クルによって樹脂封止体１４の回路基板５を覆っている
部分にすき間１５が生じ易い。また、樹脂封止体１４の
支持板１に対する密着性は、樹脂封止体１４の第２の保
護樹脂層１３に対する密着性よりも優れている。このた
め、半導体素子３と回路基板５との間に露出した支持板
１の主面に樹脂封止体１４が直接に固着されている場合
には、支持板１と樹脂封止体１４との間のすき間の発生
は抑制される。しかしながら、回路基板５の上面を被覆
する第２の保護樹脂層１３がその硬化時等に支持板１の
上面に垂れることがあり、樹脂封止体１４がこの垂れた
第２の保護樹脂層１３を介して支持板１に固着されるこ
とがある。この場合には、樹脂封止体１４を支持板１に
対して強固に固着することができないので、すき間１５
が生じ易い。すき間１５が生じると、樹脂封止体１４の
支持板１に対する密着性、換言すれば樹脂封止体１４に
よる半導体素子３の押え付けが弱くなり、半田２にクラ
ックが生じる。By the way, in the resin-sealed circuit device shown in FIG. 1, a gap 1 is provided between the resin-sealed body 14 and the second protective resin layer 13 as shown in an enlarged view in FIG.
5 is generated, whereby the pressing of the semiconductor element 3 by the resin sealing body 14 is weakened, and a temperature cycle test (a test in which a temperature cycle of a low temperature and a high temperature is repeatedly applied to a circuit device).
For example, cracks may occur in the solder 2 due to, for example, the above. The reason will be described in more detail. The circuit board 5 is a ceramic plate containing alumina (aluminum oxide) as a main component,
Its coefficient of linear expansion is on the order of 7 ppm. On the contrary,
The linear expansion coefficient of the resin sealing body 14 made of epoxy resin is as large as 17 to 20 ppm. Therefore, the amount of heat shrinkage accompanying the temperature cycle (at the time of transition from high temperature to low temperature) is larger in the resin sealing body 14 than in the circuit board 5. Therefore, a gap 15 is easily generated in a portion of the resin sealing body 14 covering the circuit board 5 due to the temperature cycle. The adhesion of the resin sealing body 14 to the support plate 1 is superior to the adhesion of the resin sealing body 14 to the second protective resin layer 13. For this reason, when the resin sealing body 14 is directly fixed to the main surface of the supporting plate 1 exposed between the semiconductor element 3 and the circuit board 5, the resin sealing body 14 The generation of gaps between them is suppressed. However, the second protective resin layer 13 covering the upper surface of the circuit board 5 may hang down on the upper surface of the support plate 1 during curing or the like. May be fixed to the support plate 1 through the support. In this case, since the resin sealing body 14 cannot be firmly fixed to the support plate 1, the gap 15
Tends to occur. When the gap 15 occurs, the adhesiveness of the resin sealing body 14 to the support plate 1, in other words, the pressing of the semiconductor element 3 by the resin sealing body 14 becomes weak, and cracks occur in the solder 2.
【０００４】そこで、本発明の目的は、半導体素子と支
持板との間の導電性接合材におけるクラックの発生を防
止することができる樹脂封止型回路装置を提供すること
にある。An object of the present invention is to provide a resin-sealed circuit device that can prevent cracks in a conductive bonding material between a semiconductor element and a support plate.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための本発明は、放熱性を有する金属製
の支持板と、前記支持板上に導電性接合材によって固着
された半導体素子と、前記支持板上に固着された回路基
板と、前記回路基板上に固着された回路素子と、前記半
導体素子及び前記半導体素子の周辺の前記支持板の表面
部分を連続的に被覆するように配置されたポリイミド又
はポリエーテルアミド系樹脂から成る第１の保護樹脂層
と、前記回路素子、前記回路基板、前記第１の保護樹脂
層、及び少なくとも前記半導体素子と前記回路基板との
間の前記支持板の表面部分を連続的に被覆するように配
置されたポリイミド又はポリエーテルアミド系樹脂から
成る第２の保護樹脂層と、前記第２の保護樹脂層を被覆
するように配置されたエポキシ系樹脂から成る樹脂封止
体とを備え、前記第１の保護樹脂層が前記第２の保護樹
脂層の体積弾性係数よりも大きい体積弾性係数を有して
いることを特徴とする樹脂封止型回路装置に係わるもの
である。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the above-mentioned object, the present invention provides a heat-dissipating metal support plate and a conductive bonding material fixed on the support plate. a semiconductor element, wherein a circuit board is fixed on the support plate, and the solid deposited circuit elements on the circuit board, continuously covering said surface portion of the support plate around said semiconductor element and said semiconductor element A first protective resin layer made of a polyimide or polyether amide-based resin, and the circuit element, the circuit board, the first protective resin layer, and at least the semiconductor element and the circuit board. A second protective resin layer made of a polyimide or polyether amide resin disposed so as to continuously cover the surface portion of the support plate between the second protective resin layer and the second protective resin layer. Wherein the first protective resin layer has a larger bulk modulus than the bulk modulus of the second protective resin layer. The present invention relates to a sealed circuit device.
【０００６】[0006]
【発明の作用及び効果】本発明における第１の保護樹脂
層と第２の保護樹脂層は、いずれもポリイミド又はポリ
エーテルアミド系樹脂から成るので、両者は強固に密着
する。また、半導体素子は第１の保護樹脂層と第２の保
護樹脂層で２重に被覆されている。また、第１の保護樹
脂層は半導体の周辺部分も被覆している。また、第２の
保護樹脂層は半導体素子の上方のみでなく、回路基板の
上及び半導体素子と回路基板の間の支持板の上を連続的
に被覆している。また、第２の保護樹脂層はポリイミド
又はポリエーテルアミド系樹脂から成るので、樹脂封止
体及び支持板に対する密着性が良く、第２の保護樹脂層
と樹脂封止体及び支持板との間にすき間が生じにくい。
従って、半導体素子を支持板に固着している導電性接合
材に隣接したクラックの発生が抑制され、半導体素子の
押え付けが十分になされ、導電性接合材にクラックが発
生しにくい。また、第１の保護樹脂層の体積弾性係数
（弾性率又は剛性率）は第２の保護樹脂層の体積弾性係
数よりも大きいので、第１の保護樹脂層の半導体素子を
支持板に対して押え付ける作用は大きい。このため、半
導体素子の下の導電性接合材にクラックが発生し難い。
なお、弾性係数をＥ、圧力又は応力をδ、ひずみをεと
すればδ＝Ｅεの関係があるので、弾性係数Ｅが大きい
ということは、変形し難いことを意味する。また、第２
の保護樹脂層は弾性係数が相対的に小さいので、樹脂封
止体と回路基板との線膨張係数の差に起因する応力（基
板及び支持板と樹脂封止体との間にすき間を発生させる
力）を緩和する働きを有し、すき間が抑制される。上述
のようにすき間が防止されると、半導体素子の下の導電
性接合材（例えば半田）にクラックが発生しなくなり、
半導体素子の接続の信頼性が高くなる。Since the first protective resin layer and the second protective resin layer of the present invention are both made of polyimide or polyetheramide resin, they are firmly adhered to each other. Further, the semiconductor element is doubly covered with the first protective resin layer and the second protective resin layer. Further, the first protective resin layer also covers the peripheral portion of the semiconductor. Further, the second protective resin layer continuously covers not only above the semiconductor element but also on the circuit board and on the support plate between the semiconductor element and the circuit board. In addition, since the second protective resin layer is made of a polyimide or polyether amide resin, it has good adhesion to the resin sealing body and the support plate, and the gap between the second protective resin layer and the resin sealing body and the support plate is good. Gap is less likely to occur.
Therefore, generation of cracks adjacent to the conductive bonding material that fixes the semiconductor element to the support plate is suppressed, the semiconductor element is sufficiently pressed, and cracks are less likely to occur in the conductive bonding material. Further, since the bulk modulus (elastic modulus or rigidity) of the first protective resin layer is larger than the bulk modulus of the second protective resin layer, the semiconductor element of the first protective resin layer is moved relative to the support plate. The pressing action is great. For this reason, cracks hardly occur in the conductive bonding material below the semiconductor element.
If the elastic coefficient is E, the pressure or stress is δ, and the strain is ε, there is a relation of δ = Eε. Therefore, a large elastic coefficient E means that it is difficult to deform. Also, the second
Since the protective resin layer has a relatively small elastic coefficient, the stress caused by the difference in linear expansion coefficient between the resin sealing body and the circuit board (causing a gap between the substrate and the support plate and the resin sealing body to occur) Force), and the gap is suppressed. When the gap is prevented as described above, cracks do not occur in the conductive bonding material (for example, solder) below the semiconductor element,
The reliability of connection of the semiconductor element is improved.
【０００７】[0007]
【実施例】次に、図３を参照して本発明の実施例に係わ
る樹脂封止型回路装置即ち混成集積回路装置を説明す
る。但し、図３において図１と実質的に同一の部分には
同一の符号を付してその説明を省略する。図３の樹脂封
止型回路装置も、図１と同様に金属製支持板１、導電性
接合材としての半田２で固着された半導体素子３、半田
４で固着された回路基板５、回路素子としてのフリップ
チップ６、配線導体７、リード細線８、配線導体９、外
部リード１０、リード細線１１、及びエポキシ樹脂から
成る樹脂封止体１４を有し、これ等は図１と同様に構成
及び配置されている。図３の樹脂封止型回路装置が図１
と異なる点は、第１及び第２の保護樹脂層１２ａ、１３
ａの材質及びこの配置である。Next, a resin-sealed circuit device, that is, a hybrid integrated circuit device according to an embodiment of the present invention will be described with reference to FIG. However, in FIG. 3, substantially the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. The resin-sealed circuit device of FIG. 3 also has a metal support plate 1, a semiconductor element 3 fixed with solder 2 as a conductive bonding material, a circuit board 5 fixed with solder 4, and a circuit element as in FIG. 1 has a flip chip 6, a wiring conductor 7, a fine lead 8, a wiring conductor 9, an external lead 10, a fine lead 11, and a resin sealing body 14 made of epoxy resin. Are located. The resin-sealed circuit device of FIG.
Is different from the first and second protective resin layers 12a and 13a.
The material of a and this arrangement.
【０００８】図３の第１の保護樹脂層１２ａは半導体素
子３の上面のみでなく、この周辺の支持板１の上も被覆
している。第２の保護樹脂層１３ａは回路基板５、フリ
ップチップ６、配線導体７、９の上のみでなく、第１の
保護樹脂層１２ａの上及び半導体素子３と回路基板５と
の間の支持板１の上も連続的に被覆し、更にリード細線
８、１１の一部も被覆している。なお、第２の保護樹脂
層１３ａの平面的に見た被覆面積は、支持板１の上面の
総面積の半分以上の約７０％である。The first protective resin layer 12a of FIG. 3 covers not only the upper surface of the semiconductor element 3 but also the peripheral support plate 1. The second protective resin layer 13a is provided not only on the circuit board 5, the flip chip 6, the wiring conductors 7 and 9, but also on the first protective resin layer 12a and between the semiconductor element 3 and the circuit board 5. 1 is continuously covered, and a part of the fine lead wires 8 and 11 is also covered. In addition, the covering area of the second protective resin layer 13a in plan view is about 70% of half or more of the total area of the upper surface of the support plate 1.
【０００９】第１及び第２の保護樹脂層１２ａ、１３ａ
は共にポリイミド又はポリエーテルアミド系樹脂（ポリ
イミド又はポリエーテルアミドと呼ばれる主骨格構造を
有する樹脂）から成るが、体積弾性係数は互いに相違
し、第１の保護樹脂層１２ａの体積弾性係数が第２の保
護樹脂層１３ａの体積弾性係数よりも大きい。この体積
弾性係数の相違は、保護樹脂中に含まれるシロキサン変
成量の相違によって生じている。即ち、シロキサン変成
量は第１の保護樹脂層１２ａに比べて第２の保護樹脂層
１３ａが大きいので、第１の保護樹脂層１２ａの弾性係
数が第２の保護樹脂層１３ａの弾性係数よりも大きい。
具体的には、第１の保護樹脂層１２ａの弾性係数は２５
０kg／mm2 、第２の保護樹脂層１３ａの弾性係数は５０
kg／mm2 である。First and second protective resin layers 12a, 13a
Are made of polyimide or polyetheramide-based resin (resin having a main skeleton structure called polyimide or polyetheramide), but have different bulk moduli, and the first protective resin layer 12a has a second bulk modulus of second resin. Is larger than the bulk modulus of the protective resin layer 13a. This difference in the bulk modulus is caused by the difference in the amount of siloxane conversion contained in the protective resin. That is, since the amount of siloxane conversion of the second protective resin layer 13a is larger than that of the first protective resin layer 12a, the elastic coefficient of the first protective resin layer 12a is smaller than the elastic coefficient of the second protective resin layer 13a. large.
Specifically, the elastic modulus of the first protective resin layer 12a is 25
0 kg / mm 2 , and the elastic modulus of the second protective resin layer 13a is 50
kg / mm 2 .
【００１０】第１の保護樹脂層１２ａの弾性係数が２０
０kg／mm2 を下回ると柔軟性が高くなり、半導体素子３
を支持板１に押え付ける力が低下して望ましくない。一
方、第１の保護樹脂層１２ａの弾性係数が３００kg／mm
2 を上回ると、柔軟性が乏しくなり、温度サイクル試験
で割れが生じ易く、半導体素子の表面を傷つけるおそれ
があり望ましくない。従って、第１の保護樹脂層１２ａ
の弾性係数を２００〜３００kg／mm2 に設定するのが望
ましい。The elastic modulus of the first protective resin layer 12a is 20
If it is less than 0 kg / mm 2 , the flexibility increases and the semiconductor element 3
This is undesirable because the force pressing the support against the support plate 1 is reduced. On the other hand, the elastic modulus of the first protective resin layer 12a is 300 kg / mm.
If it exceeds 2 , the flexibility becomes poor, cracks are likely to occur in a temperature cycle test, and the surface of the semiconductor element may be damaged, which is not desirable. Therefore, the first protective resin layer 12a
Is desirably set to 200 to 300 kg / mm 2 .
【００１１】また、第２の保護樹脂層１２ａの弾性係数
が１００kg／mm2 を上回ると樹脂が硬くなりすぎて前述
した応力緩和効果が十分に得られず、樹脂封止体１４と
第２の保護樹脂層１３ａとの間にすき間が生じることが
ある。一方、第２の保護樹脂層１３ａの弾性係数が２０
kg／mm2 を下回ると樹脂の柔軟性が高すぎて、第２の保
護樹脂層１３ａを支持板１及び第１の保護樹脂層１２ａ
の上面に適度な厚さで被覆することができなくなり望ま
しくない。従って、第２の保護樹脂層１３ａの弾性係数
を２０〜１００kg／mm2 とするのが望ましい。On the other hand, if the elastic modulus of the second protective resin layer 12a exceeds 100 kg / mm 2 , the resin becomes too hard, and the above-mentioned stress relaxation effect cannot be sufficiently obtained. There may be a gap between the protective resin layer 13a and the protective resin layer 13a. On the other hand, the elastic modulus of the second protective resin layer 13a is 20
If it is less than kg / mm 2 , the flexibility of the resin is too high, so that the second protective resin layer 13a is supported by the support plate 1 and the first protective resin layer 12a.
Cannot be coated with an appropriate thickness on the upper surface of the substrate. Therefore, it is desirable that the elastic modulus of the second protective resin layer 13a be 20 to 100 kg / mm 2 .
【００１２】エポキシ樹脂から成る樹脂封止体１４は第
２の保護樹脂層１３ａ及び支持板１の露出表面及び連結
外部リード１ａと非連結外部リード１０の一部とを被覆
している。A resin sealing body 14 made of epoxy resin covers the second protective resin layer 13a, the exposed surface of the support plate 1, and the connected external leads 1a and a part of the unconnected external leads 10.
【００１３】第１及び第２の保護樹脂層１２ａ、１３ａ
を図３に示すように配置し、且つそれ等の材料を上述し
たように決定すれば、発明の作用及び効果の欄で説明し
た作用効果即ち半田２のクラック防止が達成される。ま
た、第２の保護樹脂層１３ａの弾性係数が小さいので、
フリップチップ６のバンプ電極６ｂをつぶすような力が
フリップチップ６に作用しない。First and second protective resin layers 12a, 13a
If the materials are arranged as shown in FIG. 3 and these materials are determined as described above, the operation and effect described in the section of operation and effect of the invention, that is, crack prevention of the solder 2 can be achieved. Further, since the elastic coefficient of the second protective resin layer 13a is small,
A force that crushes the bump electrode 6b of the flip chip 6 does not act on the flip chip 6.
【００１４】[0014]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 半導体素子３はダイオード、ＦＥＴ等であって
もよい。 （２） 回路基板５上の回路素子はフリップチップ６に
限ることなく、厚膜抵抗、コンデンサチップ、ＩＣチッ
プ、トランジスタチップ等又はこれ等の組み合せであっ
てもよい。 （３） 樹脂封止体１４を支持板１の下面側には設けな
いようにすることができる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The semiconductor element 3 may be a diode, an FET, or the like. (2) The circuit element on the circuit board 5 is not limited to the flip chip 6, but may be a thick film resistor, a capacitor chip, an IC chip, a transistor chip, or a combination thereof. (3) The resin sealing body 14 may not be provided on the lower surface side of the support plate 1.
【図１】従来の樹脂封止型回路装置を示す断面図であ
る。FIG. 1 is a sectional view showing a conventional resin-sealed circuit device.
【図２】図１の一部を拡大して示す断面図である。FIG. 2 is an enlarged sectional view showing a part of FIG. 1;
【図３】本発明の実施例の樹脂封止型回路装置を示す断
面図である。FIG. 3 is a sectional view showing a resin-sealed circuit device according to an embodiment of the present invention.
１ 支持板 ２ 半田 ３ 半導体素子 ５ 回路基板 １２ａ 第１の保護樹脂層 １３ａ 第２の保護樹脂層 １４ 樹脂封止体 DESCRIPTION OF SYMBOLS 1 Support plate 2 Solder 3 Semiconductor element 5 Circuit board 12a 1st protective resin layer 13a 2nd protective resin layer 14 Resin sealing body
Claims (1)
素子と、 前記支持板上に固着された回路基板と、 前記回路基板上に固着された回路素子と、 前記半導体素子及び前記半導体素子の周辺の前記支持板
の表面部分を連続的に被覆するように配置されたポリイ
ミド又はポリエーテルアミド系樹脂から成る第１の保護
樹脂層と、 前記回路素子、前記回路基板、前記第１の保護樹脂層、
及び少なくとも前記半導体素子と前記回路基板との間の
前記支持板の表面部分を連続的に被覆するように配置さ
れたポリイミド又はポリエーテルアミド系樹脂から成る
第２の保護樹脂層と、 前記第２の保護樹脂層を被覆するように配置されたエポ
キシ系樹脂から成る樹脂封止体とを備え、前記第１の保
護樹脂層が前記第２の保護樹脂層の体積弾性係数よりも
大きい体積弾性係数を有していることを特徴とする樹脂
封止型回路装置。1. A support plate made of metal having heat dissipation properties, a semiconductor element fixed on the support plate by a conductive bonding material, a circuit board fixed on the support plate, and A fixed circuit element, and a first protective resin layer made of polyimide or polyetheramide-based resin disposed so as to continuously cover the semiconductor element and a surface portion of the support plate around the semiconductor element. The circuit element, the circuit board, the first protective resin layer,
And a second protective resin layer made of a polyimide or polyetheramide-based resin disposed so as to continuously cover at least a surface portion of the support plate between the semiconductor element and the circuit board; A resin sealing body made of an epoxy resin disposed so as to cover the protective resin layer, wherein the first protective resin layer has a bulk modulus larger than the bulk modulus of the second protective resin layer. A resin-sealed circuit device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01790597A JP3196821B2 (en) | 1997-01-16 | 1997-01-16 | Resin-sealed circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01790597A JP3196821B2 (en) | 1997-01-16 | 1997-01-16 | Resin-sealed circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10209344A JPH10209344A (en) | 1998-08-07 |
| JP3196821B2 true JP3196821B2 (en) | 2001-08-06 |
Family
ID=11956769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01790597A Expired - Fee Related JP3196821B2 (en) | 1997-01-16 | 1997-01-16 | Resin-sealed circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3196821B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006179538A (en) * | 2004-12-21 | 2006-07-06 | Hitachi Ltd | Semiconductor power module |
| JP5732884B2 (en) | 2011-02-09 | 2015-06-10 | 富士通株式会社 | Semiconductor device, manufacturing method thereof, and power supply device |
| WO2018159678A1 (en) | 2017-02-28 | 2018-09-07 | 三菱電機株式会社 | Semiconductor device |
-
1997
- 1997-01-16 JP JP01790597A patent/JP3196821B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10209344A (en) | 1998-08-07 |
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