JP3372498B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sealing technique for an LSI having a PPGA (Plastic Pin Grid Array) structure, and more particularly, a technique which is effective for use in heat dissipation by air cooling without impairing signal propagation characteristics. It is about.

[0002]

2. Description of the Related Art A semiconductor device has an increased number of pins (or leads) for connection with an external circuit as the packaging density is improved. PGA that has a package structure that enables multiple pins and can be mounted on a conventional printed circuit board
(Pin grid array).

Ceramics have been conventionally used for PGA packages, and sintered metals have been used as wiring materials. However, since ceramic is high in cost and has a high dielectric constant, it causes an electrostatic capacitance between lines for wiring. Further, since the sintered metal has a high electric resistance, a series resistance component is included in the power supply and the signal wiring. Therefore, in the power supply system, a loss occurs due to the resistance component, while in the signal system, a signal delay occurs due to the electrostatic capacitance of the ceramic and the electric resistance of the wiring.

Therefore, Nikkei Electronics "Separate Volume No.
2 Micro Devices "1984.6.11, P160.
As described in ~ P168, attention has been paid to a plastic PGA that can reduce the cost in place of the ceramic.
(Apllication Specific IC) LSI
Applications are expanding to such areas. As the package base, a material having a low dielectric constant such as glass fiber-containing epoxy, triazine, or polyimide, which is also a printed circuit board material, is used, and wiring is made of copper having a low electric resistance.

A technique related to such a PPGA is disclosed in, for example, Japanese Patent Laid-Open No. 60-38841 and Japanese Patent Laid-Open No. 60-38841.
-38842 is available.

[0006]

However, in the packaging technology using plastic as described above, the thermal conductivity of plastic is worse than that of ceramics, and cooling of semiconductor chips due to high heat generation due to high integration and signal generation. High speed propagation cannot be satisfied.

Japanese Patent Application Laid-Open No. 60-136348 deals with cooling of a semiconductor device with high heat generation. That is, a hole is formed in the LSI mounting portion of the organic printed board material, a board having good thermal conductivity is attached to the back surface of the printed board, and the LSI is attached to the good heat conducting board through the hole on the surface. However, in this structure, the difference in thermal expansion between the members is larger than that in the case where ceramics are used, and unless some measures are taken in the joining, destruction will occur.

Also, a plastic pin grid for mounting the LSI on a substrate made of glass epoxy resin.
JP-A-60-136345 discloses the use of an elastomer in the array package to eliminate the difference in thermal expansion between the adhesives between the joints. However, the elastomer has poor thermal conductivity, and there is a problem in heat dissipation measures.

Further, since the elastomer has a structure with a lot of air bubbles, it is easier for water to enter than the epoxy adhesive,
There is a problem that the wiring in the cavity is corroded.

Further, in order to facilitate heat dissipation, it is desirable to perform natural air cooling or wind speed of several m / S, but conventionally, heat dissipation cannot be expected sufficiently when the semiconductor device has several tens of watts.

Therefore, an object of the present invention is to provide a sealing technique capable of cooling a semiconductor device of several tens of watts while guaranteeing high-speed signal propagation characteristics.

Another object of the present invention is to provide a package structure having a low cost, high reliability and high performance by combining a package made of a normal printed circuit board and a heat diffusion plate made of a cheap material. It is in.

Still another object of the present invention is to bond or cover various inconsistencies due to the characteristics of structural materials with a soft material, thereby making it possible to freely combine materials by making the material property relationships independent. It provides a technology that does not sacrifice reliability and performance at cost.

The above objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

In the semiconductor device of the present invention, a semiconductor chip is selectively mounted on one main surface, and the semiconductor device is made of copper that radiates the heat generated in the semiconductor chip from the other main surface opposite to the one main surface. Thermal diffusion plate, the thermal diffusion plate and the semiconductor chip
The elastic modulus located between is 0.001-100kg / mm
^2, a soft material, a resin film formed so as to surround the periphery of the semiconductor chip in a region other than a region where the semiconductor chip is mounted on one main surface of the heat diffusion plate, and a plurality of resin films formed thereon. A flexible multilayer wiring board consisting of thin film wiring layers, connecting means for connecting the plurality of thin film wiring layers to the semiconductor chip, and the plurality of thin film wiring layers covered by the heat diffusion plate, A structure having a large number of electrodes protruding to the one main surface side of the diffusion plate is provided.

[0017]

[0018]

According to the above-mentioned means, the semiconductor chip is mounted on one main surface of the heat diffusion plate, and at least the heat generated in the semiconductor chip is radiated from the other main surface opposite to the one main surface. Therefore, the heat generated in the semiconductor chip is quickly dissipated from the other main surface of the semiconductor chip through the heat diffusion plate, while the multilayer wiring board such as plastic with each wiring layer built-in has a line capacitance, wiring The above inductance and resistance are minimized to prevent deterioration of signal propagation characteristics. Therefore, even if a plastic package is used, sufficient heat dissipation can be performed without impairing the signal propagation characteristics. Also, use a heat diffusion plate made of copper, which has a high thermal conductivity.
Heat dissipation from the semiconductor chip
Efficiently and effectively from the other main surface opposite the mounting surface
It can be carried out. In addition, the heat spreader has multiple thin film wirings.
Formed over a layer and a number of electrodes connected to it
Therefore, a further heat dissipation effect can be obtained. Well
In addition, the tree formed to surround the semiconductor chip.
Is it an oil film and multiple thin film wiring layers formed on it?
Since it has a flexible multilayer wiring board consisting of
Wiring can be formed.

[0020]

(Embodiment 1) FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention.

The LSI chip 1 is bonded to a pedestal portion formed in the central portion of the heat diffusion plate 2 via an elastomer 3 having a rubber-like elasticity containing a filler having good thermal conductivity. The heat diffusion plate 2 is formed into a rectangular shape or a rectangular shape using a copper material, the pedestal portion is made thicker than the other portions, and the opposite surface is made flat.

In the periphery of the chip 1, a wiring board 4 made of plastic, glass epoxy or the like and having wirings in multiple layers is provided with a soft material, for example, an elastomer 5 containing a filler having good thermal conductivity. And heat diffusion plate 2
Is joined to. The wiring board 4 has an opening in the center thereof, and the pedestal of the chip 1 and the heat diffusion plate 2 is located in the opening. The heat diffusion plate 2 has substantially the same outer dimensions as the wiring board 4, and increases the heat dissipation area of the chip 1. A large number of pins 6 (electrodes) are embedded in the wiring board 4 at regular intervals and are connected to the wirings in the wiring board 4, respectively. The pin 6 is erected by soldering or caulking, and its material is Be-C which has a high elastic deformation limit.
u or the like is used. Incidentally, 42 alloy, phosphor bronze, etc. have been used conventionally.

The inner end of the wiring board 4 has a stepped shape, the wiring is exposed on the surface of each step, and a bonding wire 7 made of a gold, copper or aluminum material is provided between the wiring and the wiring on the chip 1. It is connected (TAB (Tape Automated Bonding) may be used instead of the bonding wire 7).

A fin 9 (heat sink) is joined to the upper surface of the heat diffusion plate 2 (the surface on which the chip 1 is not provided) via a soft material such as an elastomer 8. The fin 9 is made of an aluminum material having excellent thermal conductivity, and further has a plurality of deep grooves formed therein so that the heat radiation area is widened. If the elastomer 8 contains a filler having good thermal conductivity, which will be described later, the heat radiation effect is further improved.

Furthermore, in order to protect the exposed surface of the chip 1 and a part of the wiring board 4 adjacent to it, that is, the electrode exposed from the inner end of the wiring board 4, the cap 10 is made of a soft material, for example, the wiring board via the elastomer 12. It is joined to 4. All the elastomers including the elastomer 12 are provided to absorb the difference in thermal expansion between the members to be joined.

Further, in order to prevent the chip 1, the electrode exposed from the side end of the wiring board 4 and the bonding wire 7 from being penetrated from the elastomer 12 for joining the wiring board 4 and the cap 10, the coating gel 1 is used.
Protected by 1. This coating gel 11
Is preferably a material that prevents wire breakage and moisture intrusion. Between the heat diffusion plate 2 and the wiring board 4, or between the wiring board 4 and the cap 1.
In the case where 0s are bonded with an elastomer, if not only the surface of the chip 1 but also the side surface of the chip 1 is covered with a moisture-resistant silicone gel, Al corrosion of the bonding pad due to the invasion of water can be prevented. This is because when the elastomer is cured, air bubbles may remain inside the elastomer, which may serve as a water entry path.

The coating gel 11 is made of, for example, a material having an elastic modulus of 100 kgf / mm ² or less, such as silicone, polyurethane, or another gel-like substance, and has a thermal expansion coefficient of 20 × 10.
It is possible to use a material filled with fused silica or alumina at ^-6 / ° C or less, or a silicon-modified phenol-curable epoxy resin.

The thermal expansion coefficient and the thermal conductivity of the materials used for the above respective parts are shown in Table 1.

[0029]

[Table 1]

As is clear from Table 1, copper, which is a material considered as the heat diffusion plate 2 compared to silicon, has a large coefficient of thermal expansion. Aluminum, which is the main structural material of the fin 9, is even larger. In addition, glass fiber-containing epoxy, glass fiber-containing polyimide, glass fiber-containing bismaleide triazine, etc., which are considered to have low dielectric constant, are
Similarly, it has a larger coefficient of thermal expansion than silicon. If AlN or Cu / Mo / Cu clad material is used for the heat diffusion plate 2, the matching with silicon is good, but the matching with other constituent materials still has a problem.

However, in the present invention, since the deformable elastomer is used for the mutual joining between the mismatched materials, the above-mentioned problem of matching is solved. However, soft material,
For example, elastomer has poor thermal conductivity, so it is desirable to form it as thin as possible or to mix a filler having good thermal conductivity as shown in Table 1.

When an alumina filler-containing methyl phenyl siloxane rubber (for example, trade name "Toray SE-4400") is used as the elastomer, the elongation at the tensile fracture limit is 100%, and a safety factor of 50% is estimated. A design distortion amount of 50% is obtained. Further, there is a methyl phenyl siloxane gel (for example, trade name “Toray JCR6110”) having a large breaking limit elongation, and the breaking limit elongation is 200%, so that 100% is obtained as a design strain amount. Tables 2 and 3 have been obtained as preferable packaging materials designed on the basis of this premise. Here, the structure shown in FIG. 1 is used together, a package having a chip size of 14.5 mm square, a fin size of 60 mm square, and a thickness of the heat diffusion plate 2 of 1 mm. The fin shape has a height of 18 mm and a fin spacing of 4 mm,
The air was cooled at a wind speed of 1 m / sec. In addition, the displacement is -55 ℃ ~
It is a value at 150 ° C. (ΔT = 205 ° C.).

[0033]

[Table 2]

[0034]

[Table 3]

Table 2 shows the case where the copper heat diffusion plate 2 is used, and the displacement at the maximum temperature difference 205 ° C. during the temperature cycle between the silicon chip of 14.5 mm square and the silicon chip is 21 μm. Considering the design strain as 100% of the gel, the adhesive thickness is 2
It is set to 1 μm or more, and is set to 25 μm in the first embodiment. On the other hand, the displacement of the 60 mm square copper heat diffusion plate and the aluminum fin at 205 ° C is 40 μm,
From the% design strain amount, the rubber thickness becomes 100 μm. When the respective thermal resistances were calculated under such conditions, the total was 2.24 ° C./W as shown in Table 2, and a good value was obtained.

Table 3 shows the case where aluminum nitride (AlN) is used as the heat diffusion plate 2, and the silicon chip and A
The displacement of 1N is small, 2 μm, and a 25 μm gold-silicon alloy (weight 8%) can be used. This makes the first
The value can be set to 1/1000 or less of the thermal resistance of the gel portion in the table, but 250 is used for joining AlN and aluminum fins.
It requires the insertion of a thick rubber material of μm, which results in 20 times the thermal resistance. However, overall, it was 1.98 ° C / W
It is smaller than the example in the table and can sufficiently cool a semiconductor chip of about 30 W. In addition, Cu / Mo / Cu clad plate (for example, CLYMAX: manufactured by Climax),
Cu-impregnated sintered tungsten, copper plate containing Fe—Ni mesh (for example, manufactured by Sumitomo Special Metals Co., Ltd.), aluminum, etc. can be handled in the same manner as the heat diffusion plate.

2A and 3 are enlarged sectional views showing details of the wiring board 4 and the pins 6. FIG. 2 corresponds to a TTL (transistor-transistor logic) interface. 2B is a perspective view showing the pin arrangement of FIG. 2A, and FIGS. 2C and 2D are partially enlarged perspective views of FIG. 2A. FIG. 3 corresponds to an ECL (emitter coupled logic) interface. 3 is characterized in that the ground layer 4a is provided between the power supply layer 4b and the signal layer 4c for impedance matching. In the first embodiment, for example, the layer interval is 10
50 Ω was obtained at 0 μm.

The wiring board 4 has a plurality of wiring layers (ground layer 4a, power supply layer 4b, signal layer 4c) laminated at regular intervals in a plastic material. FIGS. 2A and 3 show an example in which the ground layer 4 a is connected to the pin 6.
Is fitted into a through hole 4d formed in the wiring board 4 and fixed by solder 4e. In this case, the wiring layer not connected to the pin 6 is insulated so as not to contact the through hole 4d. The pin 6 is made of a material having rigidity against bending. Further, as shown in FIG. 2B, a large number of pins 6 are formed on almost the entire surface of the wiring board 4.

The connection portion of the wiring board 4 with the chip 1 is formed in a stepped shape, and the wiring layer is exposed in each step. Ground layer 4a
As shown in FIG. 2 (c), a part of the part is extended as a side surface conductive part 4f on the side where the substrate side and the power supply layer 4b are formed, and is connected to the chip by a bonding wire on the surface of the power supply layer 4b. There is. Further, the side surface conducting portion 4f is shown in FIG.
As shown in FIG. 5, it may be formed on the entire side edge of the wiring board 4, and a part thereof may extend to the surface on which the power supply layer 4b is formed. Since the chip 1 and the wiring layer are connected to each other by using a soft material such as an elastomer, the bonding wire 7 having a loop shape is used so as to absorb the displacement of each rigid body. .

Further, since the epoxy potting having a high rigidity cannot be used for the sealing for the same reason, the silicone gel (eg, the highly reliable sealing material in recent years) (for example,
Potting is performed using KJR9010 manufactured by Shin-Etsu Silicon Co., Ltd. or JCR6110 manufactured by Toray Dow Corning Silicone Co., Ltd. as the coating gel 11.

Furthermore, as a mechanical protection, the cap 10 is sealed with the elastomer 12, but the internal pressure rises due to the heating during curing to generate blowholes, the internal and external pressures become the same, and the elastomer is cured before it is cured. High reliability is obtained by using an elastomer whose cure time temperature can be controlled so that the elastomer 12 cures after the blowhole closes again.

FIGS. 4A, 4B, and 4C show details of the signal layer 4c, the power supply layer 4b, and the ground layer 4a in FIG. 2, and show about 1/4 of the entire device. There is. here,
The structure has a structure in which the plating conductive line used in the PGA package has been abolished and the parasitic capacitance of the wiring has been reduced by 30 to 40%. The realization of this is aided by the fact that the mounting portion of the chip 1 is a through hole. In addition, since each of the wiring layers uses copper wiring, the electric resistance can be reduced. Therefore, when the resistance level is the same as the conventional one, it becomes possible to design the wiring, particularly the signal wiring, in a fine width.

In FIG. 4B, the ground (Gnd) wiring 4b ', the end of which extends to the inner end of the wiring board 4, is shown.
And other wiring 4b ″ for power supply voltage. This wiring 4b ′ for grounding is connected via the side surface conducting portion 4f at the inner end of the wiring board 4 as shown in FIG. 2 (c) or (d). Strata 4a
It is connected to the. With this structure,
Since the wiring layers for the power supply and the ground can be on the same surface, the bonding can be simplified and the ground potential can be stabilized.

Further, as shown in FIG. 4B, a large number of power supply layers 4b are provided in parallel, but they may be combined to form a wide wiring. Recent LSIs tend to require a stable number of power lines of different voltages. Therefore, the power supply layer 4b is arranged in the middle so as to meet the demand. Then, a counter electrode is installed so as to have the shortest distance to the mounting portion 13 of the chip 1, and the connection points are connected by a bonding wire. The inductance can be minimized by preparing a plurality of lines for one power source.
The conduction from the chip 1 is connected to the power supply layer 4b by the bonding wire 7 via the side surface conduction portion 4f shown in FIGS.

QF with leads protruding radially around
For P (Quad Flat Package) type, all wiring must be led out to the outermost periphery of the package, but in the pin grid array package, the plating wire extending from the internal wiring is eliminated. Because I did
The wiring at the pin installation portion is only the termination, and it is possible to connect to an external circuit board via the pin 6 with a relatively short wiring, and it is possible to reduce the average parasitic capacitance, inductance, and resistance.

There is also a case where it is desired to incorporate a bypass capacitor connected between the power supply layer 4b and the ground layer 4a into the package. On the other hand, as shown in FIG. 5, a mounting space 19 for the chip type bypass capacitor 14 is secured on the power supply layer 4b or the signal layer 4c. Then, the power supply layer 4b or the signal layer 4c facing the corner portion of the chip 1
Bypass capacitor 14 is placed in the non-wiring area,
Wiring layers for connecting the bonding wires 7 are concentrated on both sides thereof in parallel. The tip of each wiring is made to face the pad 1a of the chip 1 so that the bypass capacitor 14 does not interfere with the bonding process. The bypass capacitor 14 installed in the non-wiring region has its both terminals connected between the power supply layer 4b and the ground layer 4a. The bonding wire 7 is connected between the end of the wiring layer and the pad 1a of the chip 1.

Table 3 compares the TTL interface structure shown in FIG. 2 with the conventional package structure.

[0048]

[Table 4]

As is clear from Table 4, the electrostatic capacity is improved to about 1/2 and the resistance is improved to about 1/10. This improvement enables high speed signal transmission. Specifically, it can be applied to an LSI having a clock frequency of about 150 MHz. This is because the chip mounting part has a through-hole structure, and a copper wiring and a wiring substrate made of a low dielectric constant organic material are arranged in the periphery thereof in a multilayer structure, and the layer structure is an LSI.
Signal / Power / Ground, Signal / Ground / Power,
This is due to the combination of ground / signal / ground / signal / ground / power supply / power supply / ground, which enables high-speed pulse propagation.

The soft materials used in the present application, namely the elastomer and the coating gel, all have an elastic modulus in the range of 0.001 to 100 kg / mm ² , preferably 0.01.
A material in the range of 10 kg / mm ² is used. Further, a thickness capable of absorbing the mismatch of thermal expansion between the materials forming the package,
That is, the strain amount is 5 to 1000%, preferably 50 to
A controlled thickness of 200% is recommended. Here, a soft material having an elastic modulus of 0.001 to 100 kg / mm ² is 0.001.
Silicone rubber having an elastic coefficient of 05 to 0.5 kgf / mm ² , for example, methyl phenyl siloxane or the like (reaction type with platinum catalyst) containing a filler such as Al ₂ O ₃ (which may or may not be included), For example, TSE322RTV (Toshiba Silicone Co., Ltd.), Shin-Etsu Chemical Co., Ltd. KJR9022, Dow Toray Silicone Co., Ltd. CY52-223 and the like are available. Silicone rubber is also made of the same base material (methylphenyl siloxane, etc.) as KE110 (Shin-Etsu Chemical Co., Ltd.) and KJR901.
0, Dow Toray Silicone JCR6110, etc.

There is a rubber-modified epoxy XNR3508 (dicyandiamide cured type containing carbon filler) (manufactured by Ciba Geigy) having an elastic modulus of 50 to 100 kgf / mm ² . Further, there are polyurethane rubber, UE539, polyurethane gel and the like having an elastic modulus of 0.1 to 50 kgf / mm ² . The point is that a rubber-based or gel-based material may be used, and a filler can be added if necessary.

FIG. 7 shows the relationship between the size of the package that achieves a strain amount of 5 to 1000% and the rubber thickness of the joint.

The package size in FIG. 7 is the size of a heat diffusion plate (Cu) or a glass fiber-containing epoxy resin substrate. The rubber thickness indicates the case where silicone rubber (trade name "Toray SE4400") is used as a bonding agent.

(Second Embodiment) FIG. 6 is a partially enlarged sectional view showing a second embodiment of the present invention.

The second embodiment is characterized in that the flexible multilayer board 15 is used for the wiring board 4. The flexible multilayer board 15 can be obtained by forming a thin film wiring layer into a multilayer on a film such as polyimide or maleimide. In the second embodiment, the ground layer 4 is provided on the top of the wiring layer.
a is arranged, and this ground layer 4 a is soldered to the pin 16.

Further, in the second embodiment, the wiring board 4
Is flexible, the pins cannot be held by the wiring board 4 as in the first embodiment shown in FIG. Therefore, a brim is provided at the base of the pin 16, the brim is embedded in the heat diffusion plate 2, and fixed by the solder 17 to secure the mounting strength. Here, the flange is provided on the pin, but the pin 6 shown in FIG. 1 having no flange may be embedded in the heat diffusion plate 2.

Since the wiring board 4 is thinner than the chip 1, a gap is formed on the wiring board 4 in the flat cap 10. Therefore, a cap 18 in the form of a dish having a bulge portion in the peripheral portion is used, and the peripheral surface of the cap 18 is set to the elastomer 12
The flexible multi-layer board 15 is bonded to the flexible multi-layer board 15.

Further, in the second embodiment, the interlayer conductive portion 4g is provided in a necessary portion of the flexible multilayer board 15 as in the side surface conductive portion 4f of the first embodiment.

Although the invention made by the present invention has been specifically described based on the first and second embodiments, the present invention is not limited to the first and second embodiments, and the scope does not deviate from the gist thereof. It goes without saying that various changes can be made with.

For example, in the configurations of the first and second embodiments, the combination of each member can be as shown in Table 5.

[0061]

[Table 5]

In Table 5, the type 3-1 water pillow is a liquid heat sink using the trade name "Fluorinert" as a cooling medium, and the cooling medium is enclosed in a bag-shaped member,
This is used instead of the fin 9 shown in FIG.

[0063]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the semiconductor chip is mounted on one main surface of the heat diffusion plate, and at least the heat generated in the semiconductor chip is radiated from the other main surface opposite to the one main surface. The heat generated in the above is quickly radiated from the other main surface of the semiconductor chip through the heat diffusion plate, while the multilayer wiring board such as plastic with each wiring layer built-in has a line capacitance, an inductance and a resistance on the wiring. To minimize signal propagation characteristics. Therefore, even if a plastic package is used, sufficient heat dissipation can be performed without impairing the signal propagation characteristics. Also,
In the present invention, the thermal diffusion made of copper having high thermal conductivity
By using a plate, the heat dissipation from the semiconductor chip is semi-conducting.
Efficiently from the other main surface opposite to the body chip mounting surface
It can be done effectively. Further, according to the present invention, heat
The diffuser is composed of multiple thin film wiring layers and a large number of
Further heat dissipation effect because it is formed over the electrode
Obtainable. Moreover, according to the present invention, the semiconductor chip
Resin film and film that surrounds the
And a flexible film composed of a plurality of thin film wiring layers formed thereon.
Since it has a sible multilayer wiring board, fine wiring can be formed.
Wear.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention.

FIG. 2A is an enlarged cross-sectional view showing details of a wiring board and pins corresponding to a TTL interface.

2 (b) is a perspective view showing the pin arrangement of FIG. 2 (a).

FIG. 2 (c) is a partially enlarged perspective view of FIG. 2 (a).

2 (d) is a partially enlarged perspective view of FIG. 2 (a).

FIG. 3 is an enlarged cross-sectional view showing details of a wiring board and pins corresponding to an ECL interface.

FIG. 4 (a) is a plan view showing details of the signal layer of FIG. 2 (a).

4 (b) is a plan view showing details of the power supply layer in FIG. 2 (a).

FIG. 4 (c) is a plan view showing details of the ground layer of FIG. 2 (a).

FIG. 5 is a plan view showing details of an installation portion of a bypass capacitor.

FIG. 6 is a partially enlarged cross-sectional view showing a second embodiment of the present invention.

FIG. 7 shows the relationship between package size and thickness that achieves a distortion amount of 5 to 1000%.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Chip, 1a ... Pad, 2 ... Thermal diffusion plate, 3, 5, 8, 12 ... Elastomer, 4 ... Wiring board, 4a ... Ground layer, 4b ... Power layer, 4c ...
.Signal layer, 4d ... through hole, 4e, 17 ...
Solder, 4f ... Side conducting part, 4g ... Interlayer conducting part, 6,16 ... Pin, 7 ... Bonding wire, 9 ... Fin, 10, 18 ... Cap, 11
... Coating gel, 13 ... Mounting part, 14 ...
-Bypass capacitor, 15 ... Flexible multilayer board.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuo Nakano 2326 Imai, Ome City, Tokyo Metropolitan Hiratsugu Co., Ltd. Device Development Center (72) Kazuo Koide 2326 Imai, Ome City, Tokyo Hirate Co., Ltd. In the device development center (72) Akira Yamagiwa 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Prefecture, Kanagawa Plant, Hitachi, Ltd. (72) Inventor Takao Oba, 1 Horiyamashita, Hadano, Kanagawa Prefecture, Ltd., Hitachi, Ltd., Kanagawa Plant (72) ) Inventor Toshio Hatada 502 Jinrachicho, Tsuchiura-shi, Ibaraki 502 Hitachi Institute of Mechanical Engineering, Inc. (72) Inventor Hitoshi Matsushima 502, Jinchocho, Tsuchiura-shi, Ibaraki Hitachi Institute of Mechanical Engineering (72) Inventor Kunio Miyazaki Ibaraki 4026 Kuji Town, Hitachi City, Hitachi Prefecture Hitachi Research Laboratory, Hitachi, Ltd. (56) Reference References JP-A 1-253942 (JP, A) JP-A 1-199460 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/12

Claims (3)

(57) [Claims] 1. A heat diffusion plate made of copper, in which a semiconductor chip is selectively mounted on one main surface, and heat generated in the semiconductor chip is radiated from another main surface opposite to the one main surface, Elasticity located between the heat diffusion plate and the semiconductor chip
Material with a rate of 0.001 to 100 kg / mm ²
And a resin film formed so as to surround the periphery of the semiconductor chip in a region other than the region where the semiconductor chip is mounted on one main surface of the heat diffusion plate, and a plurality of thin film wiring layers formed thereon. A flexible multilayer wiring board consisting of, connecting means for connecting the plurality of thin film wiring layers and the semiconductor chip, connected to the plurality of thin film wiring layers covered by the thermal diffusion plate, the thermal diffusion plate of the A semiconductor device having a large number of electrodes protruding to one main surface side. 2. The semiconductor device according to claim 1, wherein one ends of a plurality of wiring layers of the multilayer wiring board are formed on the resin film so as to surround the semiconductor chip. 3. The semiconductor device according to claim 1, wherein the resin film is made of polyimide or maleimide.