JP2001284809A - Multilayer circuit board and its manufacturing method - Google Patents

Multilayer circuit board and its manufacturing method

Info

Publication number
JP2001284809A
JP2001284809A JP2000100752A JP2000100752A JP2001284809A JP 2001284809 A JP2001284809 A JP 2001284809A JP 2000100752 A JP2000100752 A JP 2000100752A JP 2000100752 A JP2000100752 A JP 2000100752A JP 2001284809 A JP2001284809 A JP 2001284809A
Authority
JP
Japan
Prior art keywords
circuit board
multilayer circuit
insulating layer
outermost
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000100752A
Other languages
Japanese (ja)
Inventor
Takashi Kariya
隆 苅谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2000100752A priority Critical patent/JP2001284809A/en
Publication of JP2001284809A publication Critical patent/JP2001284809A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer circuit board, wherein manufacturing processes can be simplified and strength is high. SOLUTION: A printed board 2 is so laminated that an insulating board 4a is arranged on the one uppermost layer of a multilayer circuit board 1. Viaholes 6a which penetrate the insulating board 4a in the width wise direction are arranged, and pins 12 are fixed in the viaholes 6a. In this case, the surface of a copper foil 5a to which base end portions 13 of the pins 12 are bonded is covered with the insulating board 4a, except apertures formed by the viaholes 6a. Consequently, it is unnecessary to previously arrange solder resist before soldering the pins 12. Hence, processes can be simplified, and holding strength of the pins 12 can be improved. The insulating board 4a is formed of glass cloth base material epoxy resin, so that the strength of the whole multilayer circuit board 1 can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多層回路基板およ
びその製造方法に関するものである。
The present invention relates to a multilayer circuit board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】多層回路基板の製造方法としては、例え
ば導体回路を形成させたプリント基板の複数枚を積層さ
せて、一括プレスする方法がある。これは、銅張積層板
に所定の回路パターンを形成したプリント基板を、接着
層を挟んで複数枚積層し、一括プレスすることにより多
層化する方法である。このような一括積層型の多層回路
基板の製造方法によれば、工程の簡素化や低コスト化が
図れるという利点がある。
2. Description of the Related Art As a method of manufacturing a multi-layer circuit board, for example, there is a method of laminating a plurality of printed circuit boards on which conductive circuits are formed and pressing them at once. This is a method of laminating a plurality of printed circuit boards on which a predetermined circuit pattern is formed on a copper-clad laminate with an adhesive layer interposed therebetween and by pressing all together. According to such a method of manufacturing a multilayer circuit board of a batch lamination type, there is an advantage that the process can be simplified and the cost can be reduced.

【0003】このようにして製造される多層回路基板に
おいては、最外面に露出する銅箔に、パターニングを行
って回路パターンやピン立て用の接続用ランドを形成さ
せておき、この接続用ランドに外部端子との接続用のピ
ンがはんだ付けによって装着される。
In the multilayer circuit board manufactured as described above, a connection land for forming a circuit pattern and pins is formed on a copper foil exposed on the outermost surface by patterning. Pins for connection to external terminals are mounted by soldering.

【0004】[0004]

【発明が解決しようとする課題】しかし、上記のような
方法では、ピンをはんだ付けする作業の際に、はんだが
隣接する回路パターンの間に流れて、短絡等を起こすの
を回避するために、最外面に予めソルダレジストを塗布
しておく工程が必要となっていた。また、上記の多層回
路基板では、はんだ付けされたピンを支持する構造は、
銅箔上に形成された接続用ランドであるため、より強い
力でピンの基端部分を支持可能な構成が求められてい
た。
However, in the above-described method, it is necessary to prevent the solder from flowing between adjacent circuit patterns and causing a short circuit or the like during the soldering operation of the pins. In addition, a step of previously applying a solder resist to the outermost surface has been required. Also, in the above multilayer circuit board, the structure for supporting the soldered pins is
Since the connection lands are formed on the copper foil, a configuration capable of supporting the base end portion of the pin with a stronger force has been required.

【0005】本発明は、上記した事情に鑑みてなされた
ものであり、その目的は、製造工程を簡略化できる多層
回路基板の製造方法を提供することであり、また他の目
的は、ピンの支持強度の高い多層回路基板を提供するこ
とにある。
[0005] The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a multilayer circuit board capable of simplifying the manufacturing process. An object of the present invention is to provide a multilayer circuit board having high supporting strength.

【0006】[0006]

【課題を解決するための手段】上記の課題を解決するた
めに請求項1の発明に係る多層回路基板は、絶縁層の表
裏両面のうち一方の面に導体層が形成されたプリント基
板の複数が積層されたものであって、前記多層回路基板
の表裏一対の最外面のうち、少なくとも一方側の面には
前記絶縁層が配されて最外絶縁層が設けられるようにし
て前記プリント基板が積層されているとともに、前記最
外絶縁層には、厚さ方向に貫通する孔部が設けられてお
り、この孔部内には、前記多層回路基板を他の部材に接
続するピンが固着されていることを特徴とする。
According to another aspect of the present invention, there is provided a multilayer circuit board comprising a plurality of printed circuit boards having a conductor layer formed on one of the front and back surfaces of an insulating layer. Wherein the insulating layer is disposed on at least one surface of a pair of outermost surfaces of the front and back surfaces of the multilayer circuit board, and the printed circuit board is provided with the outermost insulating layer. While being laminated, the outermost insulating layer is provided with a hole penetrating in the thickness direction, and a pin for connecting the multilayer circuit board to another member is fixed in the hole. It is characterized by being.

【0007】請求項2の発明は、請求項1に記載のもの
であって、前記最外絶縁層は、ガラス布エポキシ樹脂に
より形成されていることを特徴とする。
According to a second aspect of the present invention, in the first aspect, the outermost insulating layer is formed of a glass cloth epoxy resin.

【0008】請求項3の発明に係る多層回路基板の製造
方法は、絶縁層の表裏両面のうち一方の面に導体層を形
成したプリント基板の複数を積層して構成される多層回
路基板を製造する方法であって、(a)前記多層回路基板
の表裏一対の最外面のうち、少なくとも一方側の面には
前記絶縁層が配されて最外絶縁層が設けられるようにし
て、前記プリント基板を積層する工程、(b)前記最外絶
縁層の厚さ方向に貫通する孔部を形成する工程、(c)前
記孔部内に、前記多層回路基板を他の部材に接続するピ
ンを固着する工程を実行することを特徴とする。ここ
で、上記の(b)の工程は、必ずしも(a)の工程よりも後に
行う必要はなく、(b)、(a)の順に行ってもよい。
According to a third aspect of the present invention, there is provided a method of manufacturing a multilayer circuit board comprising a plurality of printed circuit boards each having a conductor layer formed on one of the front and back surfaces of an insulating layer. The method of (a), wherein the insulating layer is disposed on at least one of the outermost surfaces of the pair of front and back surfaces of the multilayer circuit board so that the outermost insulating layer is provided, and the printed circuit board is provided. Laminating, (b) forming a hole penetrating in the thickness direction of the outermost insulating layer, (c) fixing a pin for connecting the multilayer circuit board to another member in the hole. Performing a process. Here, the step (b) need not always be performed after the step (a), and may be performed in the order of (b) and (a).

【0009】[0009]

【発明の作用、および発明の効果】請求項1の発明によ
れば、多層回路基板の最外面には最外絶縁層が配されて
おり、この最外絶縁層を厚さ方向に貫通する孔部内にピ
ンが固定されている。このため、ピンの基端部分が接着
される導体層は、最外絶縁層によって覆われており、ピ
ンの保持強度を向上させることができる。
According to the first aspect of the present invention, the outermost insulating layer is disposed on the outermost surface of the multilayer circuit board, and the hole penetrates the outermost insulating layer in the thickness direction. A pin is fixed inside the unit. For this reason, the conductor layer to which the base end portion of the pin is bonded is covered with the outermost insulating layer, and the holding strength of the pin can be improved.

【0010】請求項2の発明によれば、絶縁層はガラス
布エポキシ樹脂により形成されている。これにより、多
層回路基板は、強度が高い絶縁層により補強されること
となり、多層回路基板全体の強度を向上させることがで
きる。
According to the second aspect of the present invention, the insulating layer is formed of a glass cloth epoxy resin. Thereby, the multilayer circuit board is reinforced by the insulating layer having high strength, and the strength of the entire multilayer circuit board can be improved.

【0011】請求項3の発明によれば、ピンの基端部が
接続される導体層には、あらかじめ最外絶縁層が設けら
れているため、ピンをはんだ付けする作業の際に、ソル
ダレジストを設ける必要がない。このため、多層回路基
板の製造工程を簡略化することができる。
According to the third aspect of the present invention, the outermost insulating layer is provided in advance on the conductor layer to which the base end of the pin is connected. There is no need to provide For this reason, the manufacturing process of the multilayer circuit board can be simplified.

【0012】[0012]

【発明の実施の形態】以下、本発明を具体化した一実施
形態について、図1〜図3を参照しつつ詳細に説明す
る。本発明の多層回路基板1は、複数のプリント基板2
を積層したものであり、一方の最外面(図3において、
最下面)には絶縁性基板4a(本発明の最外絶縁層に該
当する)が配され、この絶縁性基板4aの厚さ方向に貫
通するビアホール6aが設けられ、このビアホール6a
内にピン12が固着されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIGS. The multilayer circuit board 1 of the present invention includes a plurality of printed circuit boards 2.
Are laminated, and one outermost surface (in FIG. 3,
An insulating substrate 4a (corresponding to the outermost insulating layer of the present invention) is disposed on the lowermost surface), and a via hole 6a is provided through the insulating substrate 4a in the thickness direction.
The pin 12 is fixed inside.

【0013】多層回路基板1を形成するプリント基板2
の出発材料は、銅張積層板3である。銅張積層板3は、
例えば板状のガラス布エポキシ樹脂により形成される絶
縁性基板4の一方の面(図1において下面側)に、全面
に銅箔5が貼り付けられた周知の構造である(図1
A)。
Printed circuit board 2 forming multilayer circuit board 1
Is a copper-clad laminate 3. The copper-clad laminate 3
For example, it has a known structure in which a copper foil 5 is attached to the entire surface of one surface (the lower surface side in FIG. 1) of an insulating substrate 4 formed of a plate-like glass cloth epoxy resin (FIG. 1).
A).

【0014】この絶縁性基板4の所定の位置に、絶縁性
基板4の銅箔5とは反対側の面(図1において上面側)
からレーザ照射を行い、絶縁性基板4の厚さ方向に貫通
して銅箔5に到達するビアホール6を形成する(図1
B)。レーザ加工は、例えばパルス発振型炭酸ガスレー
ザ加工装置によって行うことが可能であり、その場合に
は、パルスエネルギーが2.0〜10.0mJ、パルス
幅が1〜100μs、パルス間隔が0.5ms以上、シ
ョット数が3〜50という条件で形成することが望まし
い。
At a predetermined position on the insulating substrate 4, a surface of the insulating substrate 4 opposite to the copper foil 5 (an upper surface in FIG. 1)
Is applied to form a via hole 6 penetrating in the thickness direction of the insulating substrate 4 and reaching the copper foil 5 (FIG. 1).
B). Laser processing can be performed by, for example, a pulse oscillation type carbon dioxide laser processing apparatus. In this case, the pulse energy is 2.0 to 10.0 mJ, the pulse width is 1 to 100 μs, and the pulse interval is 0.5 ms or more. And the number of shots is desirably 3 to 50.

【0015】この後、生成されたビアホール6の内部に
残留する樹脂を取り除くためのデスミア処理を行う。デ
スミア処理は、例えば過マンガン酸カリウム処理、酸素
プラズマ放電、コロナ放電処理等により行うことができ
る。
Thereafter, a desmear process is performed to remove the resin remaining inside the generated via hole 6. The desmear treatment can be performed by, for example, potassium permanganate treatment, oxygen plasma discharge, corona discharge treatment, or the like.

【0016】次に、銅箔5を例えばポリエチレンテレフ
タレート製の保護フィルムで覆った状態で(図示せ
ず)、ビアホール6内に、銅箔5を一方の電極とした電
気めっき法により、めっき導体7を形成させる(図1
C)。めっき導体7の充填量は、その上面が絶縁性基板
4の表面から僅かに低くなる程度とするのが好ましい。
めっき金属としては、銅がもっとも好ましいが、スズ、
銀、はんだ、銅/スズ、銅/銀等、めっき可能な金属で
あればよい。
Next, with the copper foil 5 covered with a protective film made of, for example, polyethylene terephthalate (not shown), a plated conductor 7 is formed in the via hole 6 by electroplating using the copper foil 5 as one electrode. (Fig. 1
C). It is preferable that the filling amount of the plated conductor 7 is such that the upper surface thereof is slightly lower than the surface of the insulating substrate 4.
Copper is most preferred as the plating metal, but tin,
Any metal that can be plated, such as silver, solder, copper / tin, or copper / silver, may be used.

【0017】ビアホール6内のめっき導体7に重ねるよ
うにして、バンプめっきにより例えばスズ等の低融点材
料からなる導電性バンプ8を形成させる。導電性バンプ
8は、絶縁性基板4の上面から僅かに突出されるように
充填される(図1D)。この後、前記の保護フィルムを
銅箔5から剥ぎ取った後、銅箔5を周知のエッチング手
法によりエッチングして導体回路10が形成される(図
1E)。
A conductive bump 8 made of a low melting point material such as tin is formed by bump plating so as to overlap the plated conductor 7 in the via hole 6. The conductive bumps 8 are filled so as to slightly protrude from the upper surface of the insulating substrate 4 (FIG. 1D). Thereafter, after the protective film is peeled off from the copper foil 5, the copper foil 5 is etched by a well-known etching method to form the conductor circuit 10 (FIG. 1E).

【0018】次いでプリント基板2において、導電性バ
ンプ8を形成させた面上に、熱硬化性の接着剤11(例
えば、エポキシ樹脂製のものを使用できる。)がロール
コート法により塗布される(図1F)。
Next, on the surface of the printed circuit board 2 on which the conductive bumps 8 are formed, a thermosetting adhesive 11 (for example, an epoxy resin can be used) is applied by a roll coating method ( (FIG. 1F).

【0019】このようにして複数のプリント基板2を製
造した後に、最下層に配される外層用プリント基板2a
を形成させる。外層用プリント基板2aは、板状のガラ
ス布エポキシ樹脂により形成される絶縁性基板4aの一
方の面に、全面に銅箔5が貼り付けられた銅張積層板3
を出発材料とし、銅箔5aを周知のエッチング手法によ
りエッチングして、所定の位置に導体回路10aを形成
させる。このとき、絶縁性基板4aには、後述のビアホ
ール6aを形成させる際に位置決めをするためのターゲ
ットマーク(図示せず)を、絶縁性基板4aの表面側
(図2において下面側)から判別可能なように設けてお
く。
After manufacturing a plurality of printed circuit boards 2 in this manner, the outermost printed circuit board 2a disposed at the lowermost layer
Is formed. The printed circuit board 2a for the outer layer is a copper-clad laminate 3 in which a copper foil 5 is attached to the entire surface of one side of an insulating substrate 4a formed of a plate-like glass cloth epoxy resin.
Is used as a starting material, the copper foil 5a is etched by a well-known etching technique to form a conductor circuit 10a at a predetermined position. At this time, a target mark (not shown) for positioning when forming a via hole 6a to be described later can be distinguished from the front surface side (the lower surface side in FIG. 2) of the insulating substrate 4a. It is provided as follows.

【0020】このようにして形成された複数枚のプリン
ト基板2,2aを位置合わせして重ね合わせる(図2
G)。このとき最上層のプリント基板2は、導体回路1
0が外側を向き、導電性バンプ8が内側を向くようにし
て配置されており、その下方に位置するプリント基板2
は、上側に導体回路10が位置するようにして積層され
る。こうして、上側に位置するプリント基板2の導電性
バンプ8が、その下側に位置するプリント基板2の導体
回路10に接続可能な方向に積層される。また、最下層
に設けられる外層用プリント基板2aは、その絶縁性基
板4aが外側に向くようにして配置されており、導体回
路10aは、直上に重なるプリント基板2の導電性バン
プ8と接続されるようにして、重ねあわされる。
The plurality of printed circuit boards 2 and 2a thus formed are aligned and superposed (FIG. 2).
G). At this time, the uppermost printed circuit board 2 is
0 is directed outward and the conductive bumps 8 are directed inward, and the printed circuit board 2 located therebelow.
Are stacked such that the conductor circuit 10 is located on the upper side. Thus, the conductive bumps 8 of the upper printed circuit board 2 are stacked in a direction connectable to the conductor circuit 10 of the lower printed circuit board 2. The printed circuit board 2a for the outer layer provided on the lowermost layer is arranged so that the insulating substrate 4a faces outward, and the conductor circuit 10a is connected to the conductive bump 8 of the printed circuit board 2 which is directly overlaid. So that they overlap.

【0021】そして、例えば180℃、70分で加熱真
空プレスすることにより、接着剤11が硬化し、各プリ
ント基板2,2aが一体化した多層回路基板1が形成さ
れる(図2H)。このとき、各プリント基板2の導電性
バンプ8の先端が、隣接するプリント基板2の導体回路
10の所定位置に接続されており、これにより隣接する
プリント基板2の導体回路10間が電気的に接続され
る。
The adhesive 11 is cured by, for example, heating and vacuum pressing at 180 ° C. for 70 minutes to form the multilayer circuit board 1 in which the printed boards 2 and 2a are integrated (FIG. 2H). At this time, the tip of the conductive bump 8 of each printed circuit board 2 is connected to a predetermined position of the conductive circuit 10 of the adjacent printed circuit board 2, thereby electrically connecting the conductive circuits 10 of the adjacent printed circuit board 2. Connected.

【0022】次に、絶縁性基板4aのターゲットマーク
を施した位置情報に基づいて、絶縁性基板4aの下面側
からレーザ照射を行い、絶縁性基板4aの厚さ方向に貫
通して導体回路10a達するビアホール6a(本発明の
孔部)を形成させる。次いで、ビアホール6a内に、導
電性金属により形成されたピン12を挿入し、ピン12
の基端部13を導体回路10aにはんだ付けにより接着
させる(図3I)。
Next, based on the information on the position of the target mark on the insulating substrate 4a, laser irradiation is performed from the lower surface side of the insulating substrate 4a to penetrate through the insulating substrate 4a in the thickness direction. A via hole 6a (a hole according to the present invention) is formed. Next, the pin 12 formed of a conductive metal is inserted into the via hole 6a,
Is bonded to the conductor circuit 10a by soldering (FIG. 3I).

【0023】以上のように、本実施形態によれば、多層
回路基板1は、複数枚のプリント基板2が重ねあわさ
れ、一方の最外面に外層用プリント基板2aがその絶縁
性基板4aを外側に向けて配されるように重ねられて接
着される。そして、この絶縁性基板4aの厚さ方向に貫
通するビアホール6aが設けられ、ビアホール6a内に
ピン12が固着される。この際、ピン12の基端部13
が接着される銅箔5aは、ビアホール6aにより開口し
ている以外の面が、絶縁性基板4aで覆われている。こ
のため、ピン12をはんだ付けする作業の前に、あらか
じめソルダレジストを設ける必要がない。これにより、
多層回路基板1の製造工程を簡略化することができる。
また、ピン12の基端部13が固定される銅箔10a
は、絶縁性基板4aによって保護されているので、ピン
12の保持強度を向上させることができる。
As described above, according to the present embodiment, the multilayer circuit board 1 has a plurality of printed boards 2 stacked one on top of the other, and the outermost printed board 2a has the insulating board 4a on the outermost surface. Are stacked and adhered so as to be arranged toward. Then, a via hole 6a penetrating in the thickness direction of the insulating substrate 4a is provided, and the pin 12 is fixed in the via hole 6a. At this time, the proximal end 13 of the pin 12
The surface of the copper foil 5a to which is adhered is covered with the insulating substrate 4a except for the surface opened by the via hole 6a. Therefore, it is not necessary to provide a solder resist in advance before the operation of soldering the pins 12. This allows
The manufacturing process of the multilayer circuit board 1 can be simplified.
Further, a copper foil 10a to which the base end 13 of the pin 12 is fixed.
Is protected by the insulating substrate 4a, so that the holding strength of the pins 12 can be improved.

【0024】また、絶縁性基板4aはガラス布基材エポ
キシ樹脂により形成されている。これにより、多層回路
基板1全体の強度を向上させることができる。
The insulating substrate 4a is formed of a glass cloth base epoxy resin. Thereby, the strength of the entire multilayer circuit board 1 can be improved.

【0025】なお、本発明の技術的範囲は、上記した実
施形態によって限定されるものではなく、均等の範囲に
まで及ぶものである。
The technical scope of the present invention is not limited to the above-described embodiment, but extends to an equivalent range.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係る回路基板の製造工程
を示す断面図 (A)銅張積層板の断面図 (B)銅張積層板にビアホールを形成したときの断面図 (C)ビアホールにめっき導体を充填したときの断面図 (D)ビアホールに導電性バンプを形成させたときの断
面図 (E)銅箔をパターニングして導体回路を形成させたと
きの断面図 (F)回路基板に接着層が塗布されたときの断面図
FIG. 1 is a cross-sectional view showing a manufacturing process of a circuit board according to an embodiment of the present invention. (A) Cross-sectional view of a copper-clad laminate. (B) Cross-sectional view when a via hole is formed in a copper-clad laminate. Sectional view when the via hole is filled with a plated conductor (D) Sectional view when a conductive bump is formed in the via hole (E) Sectional view when a conductive circuit is formed by patterning copper foil (F) Circuit Sectional view when the adhesive layer is applied to the substrate

【図2】回路基板の積層工程を示す断面図 (G)回路基板を積層したときの断面図 (H)回路基板を接着して形成された多層回路基板の断
面図
FIG. 2 is a cross-sectional view showing a circuit board laminating process; (G) a cross-sectional view when circuit boards are stacked; (H) a cross-sectional view of a multilayer circuit board formed by bonding circuit boards.

【図3】本発明の多層回路基板の断面図 (I)最外層の絶縁性基板にビアホールが形成され、ビ
アホール内にピンが接続された多層回路基板の断面図
FIG. 3 is a cross-sectional view of a multilayer circuit board of the present invention. (I) A cross-sectional view of a multilayer circuit board in which a via hole is formed in an outermost insulating substrate and pins are connected in the via hole.

【符号の説明】[Explanation of symbols]

1…多層回路基板 2…プリント基板 4…絶縁性基板(絶縁層) 4a…絶縁性基板(最外絶縁層) 5…銅箔(導体層) 6a…ビアホール(孔部) 10,10a…導体回路(導体層) 12…ピン 13…基端部 DESCRIPTION OF SYMBOLS 1 ... Multilayer circuit board 2 ... Printed board 4 ... Insulating board (insulating layer) 4a ... Insulating board (outermost insulating layer) 5 ... Copper foil (conductor layer) 6a ... Via hole (hole part) 10, 10a ... Conductor circuit (Conductor layer) 12 ... pin 13 ... base end

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁層の表裏両面のうち一方の面に導体
層が形成されたプリント基板の複数が積層された多層回
路基板であって、 前記多層回路基板の表裏一対の最外面のうち、少なくと
も一方側の面には前記絶縁層を配することでそれを最外
絶縁層として前記プリント基板が積層されているととも
に、前記最外絶縁層には、厚さ方向に貫通する孔部が設
けられており、この孔部内には、前記多層回路基板を他
の部材に接続するピンが固着されていることを特徴とす
る多層回路基板。
1. A multilayer circuit board in which a plurality of printed circuit boards each having a conductor layer formed on one of the front and back surfaces of an insulating layer are stacked, wherein: The printed circuit board is laminated on at least one surface by disposing the insulating layer and using it as the outermost insulating layer, and the outermost insulating layer is provided with a hole penetrating in the thickness direction. A pin for connecting the multilayer circuit board to another member is fixed in the hole.
【請求項2】 前記最外絶縁層は、ガラス布エポキシ樹
脂により形成されていることを特徴とする請求項1に記
載の多層回路基板。
2. The multilayer circuit board according to claim 1, wherein the outermost insulating layer is formed of a glass cloth epoxy resin.
【請求項3】 絶縁層の表裏両面のうち一方の面に導体
層を形成したプリント基板の複数を積層して構成される
多層回路基板を製造する方法であって、 (a)前記多層回路基板の表裏一対の最外面のうち、少な
くとも一方側の面には前記絶縁層を配し、それを最外絶
縁層として、前記プリント基板を積層する工程、 (b)前記最外絶縁層の厚さ方向に貫通する孔部を形成す
る工程、 (c)前記孔部内に、前記多層回路基板を他の部材に接続
するピンを固着する工程を実行することを特徴とする多
層回路基板の製造方法。
3. A method for manufacturing a multilayer circuit board comprising a plurality of printed circuit boards each having a conductor layer formed on one of the front and back surfaces of an insulating layer, wherein: (a) the multilayer circuit board; A step of arranging the insulating layer on at least one surface of a pair of outermost surfaces of the front and back sides, and using the printed circuit board as an outermost insulating layer, and (b) a thickness of the outermost insulating layer. Forming a hole penetrating in the direction, and (c) fixing a pin for connecting the multilayer circuit board to another member in the hole.
JP2000100752A 2000-04-03 2000-04-03 Multilayer circuit board and its manufacturing method Pending JP2001284809A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000100752A JP2001284809A (en) 2000-04-03 2000-04-03 Multilayer circuit board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000100752A JP2001284809A (en) 2000-04-03 2000-04-03 Multilayer circuit board and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2001284809A true JP2001284809A (en) 2001-10-12

Family

ID=18614904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000100752A Pending JP2001284809A (en) 2000-04-03 2000-04-03 Multilayer circuit board and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2001284809A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100568880B1 (en) 2005-12-09 2006-04-10 주식회사 영은전자 Printed circuit board having combining structure by etching and the combining method
JP2007088058A (en) * 2005-09-20 2007-04-05 Denso Corp Multilayer substrate and method of manufacturing same
JP2012004440A (en) * 2010-06-18 2012-01-05 Shinko Electric Ind Co Ltd Wiring board
JP2012009606A (en) * 2010-06-24 2012-01-12 Shinko Electric Ind Co Ltd Wiring board

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135056A (en) * 1987-11-20 1989-05-26 Hitachi Ltd Semiconductor device
JPH0335550A (en) * 1989-06-30 1991-02-15 Ibiden Co Ltd Manufacture of electronic part mount substrate
JPH04165656A (en) * 1990-10-30 1992-06-11 Nec Corp Semiconductor device
JPH0817963A (en) * 1994-06-28 1996-01-19 Nippon Avionics Co Ltd Manufacturing method of pga package and printed-wiring board
JPH09116273A (en) * 1995-08-11 1997-05-02 Shinko Electric Ind Co Ltd Multilayered circuit board and its manufacture
JPH11317477A (en) * 1999-03-19 1999-11-16 Hitachi Ltd Semiconductor device
JP2000003980A (en) * 1998-04-17 2000-01-07 Sumitomo Metal Electronics Devices Inc Semiconductor mounting circuit board and its manufacture

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135056A (en) * 1987-11-20 1989-05-26 Hitachi Ltd Semiconductor device
JPH0335550A (en) * 1989-06-30 1991-02-15 Ibiden Co Ltd Manufacture of electronic part mount substrate
JPH04165656A (en) * 1990-10-30 1992-06-11 Nec Corp Semiconductor device
JPH0817963A (en) * 1994-06-28 1996-01-19 Nippon Avionics Co Ltd Manufacturing method of pga package and printed-wiring board
JPH09116273A (en) * 1995-08-11 1997-05-02 Shinko Electric Ind Co Ltd Multilayered circuit board and its manufacture
JP2000003980A (en) * 1998-04-17 2000-01-07 Sumitomo Metal Electronics Devices Inc Semiconductor mounting circuit board and its manufacture
JPH11317477A (en) * 1999-03-19 1999-11-16 Hitachi Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088058A (en) * 2005-09-20 2007-04-05 Denso Corp Multilayer substrate and method of manufacturing same
KR100568880B1 (en) 2005-12-09 2006-04-10 주식회사 영은전자 Printed circuit board having combining structure by etching and the combining method
JP2012004440A (en) * 2010-06-18 2012-01-05 Shinko Electric Ind Co Ltd Wiring board
JP2012009606A (en) * 2010-06-24 2012-01-12 Shinko Electric Ind Co Ltd Wiring board

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