JP2971594B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JP2971594B2
JP2971594B2 JP3052416A JP5241691A JP2971594B2 JP 2971594 B2 JP2971594 B2 JP 2971594B2 JP 3052416 A JP3052416 A JP 3052416A JP 5241691 A JP5241691 A JP 5241691A JP 2971594 B2 JP2971594 B2 JP 2971594B2
Authority
JP
Japan
Prior art keywords
bus bar
lead
leads
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3052416A
Other languages
Japanese (ja)
Other versions
JPH04287356A (en
Inventor
昭彦 岩谷
順一 有田
昌弘 一谷
一郎 安生
村上　　元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3052416A priority Critical patent/JP2971594B2/en
Publication of JPH04287356A publication Critical patent/JPH04287356A/en
Application granted granted Critical
Publication of JP2971594B2 publication Critical patent/JP2971594B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特にＬＯＣ(Lead On Chip)構造を備えた樹脂封止
形ＬＳＩパッケージに適用して有効な技術に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a resin-sealed LSI package having a LOC (Lead On Chip) structure.

【０００２】[0002]

【従来の技術】４メガビット（Mbit）ダイナミックＲＡ
Ｍ（Dynamic Random Access Memory)や、１６メガビッ
トＤＲＡＭなどの大規模集積回路を形成した半導体チッ
プを収容する樹脂封止形ＬＳＩパッケージは、チップサ
イズが従来よりも増大する一方でパッケージ寸法の増大
には規格上の制約があるという理由から、パッケージ本
体を構成する樹脂の肉厚が極めて薄くなっている。その
ため、パッケージ本体内のインナーリード長が極めて短
くなり、リードがパッケージから抜け易くなったり、リ
ードを折り曲げる際にパッケージにクラックが発生した
りするという問題が生じている。2. Description of the Related Art 4 Mbit dynamic RA
A resin-encapsulated LSI package that accommodates a semiconductor chip on which a large-scale integrated circuit such as a dynamic random access memory (M) or a 16-Mbit DRAM is formed. The thickness of the resin constituting the package body is extremely thin because of the restrictions on the standard. As a result, the length of the inner lead in the package body becomes extremely short, which causes a problem that the lead is easily removed from the package and a crack occurs in the package when the lead is bent.

【０００３】さらに、上記樹脂封止形ＬＳＩパッケージ
のうち、ＳＯＪ(Small Outline J-lead package)などの
表面実装形ＬＳＩパッケージでは、上記した問題に加え
て、パッケージ中に含まれる水分が半田リフロー時の熱
で膨張することに起因する、いわゆるリフロークラック
が深刻な問題になっている。Further, among the above-mentioned resin-sealed LSI packages, a surface-mount LSI package such as a SOJ (Small Outline J-lead package) has, in addition to the above-described problem, water contained in the package during solder reflow. The so-called reflow crack caused by expansion due to the heat of the heat has become a serious problem.

【０００４】これらの問題の解決策として、チップを搭
載するタブ（ダイパッド）を廃止し、チップの主面に接
着した絶縁テープ上にリードを配置してリードとチップ
のボンディングパッドとをボンディングワイヤにより結
線する、いわゆるＬＯＣ（リード・オン・チップ) 構造
や、リード上に接着した絶縁テープの上にチップを搭載
し、リードとボンディングパッドとをワイヤで結線す
る、いわゆるＣＯＬ(Chip On Lead)構造などのタブレス
リードフレーム方式が提案されている。As a solution to these problems, a tab (die pad) for mounting a chip is abolished, leads are arranged on an insulating tape adhered to the main surface of the chip, and the leads and the bonding pads of the chip are connected by bonding wires. A so-called LOC (lead-on-chip) structure for connecting wires, a so-called COL (Chip On Lead) structure for mounting a chip on an insulating tape adhered to the leads and connecting the leads and bonding pads with wires Has been proposed.

【０００５】上記タブレスリードフレーム方式を用いた
ＬＳＩパッケージは、インナーリード長を長くするこ
とができるため、パッケージの耐熱性や耐湿性が向上す
る。チップ周辺でインナーリードをひき回す必要がな
いので、サイズの大きいチップでも従来寸法のパッケー
ジに収容することが可能となる。チップ内の配線長を
短くすることができるため、信号の配線遅延が低減され
る。水分がたまってリフロークラックの原因となるタ
ブの廃止により、リフロークラック耐性が向上する、な
どの特徴がある。In the LSI package using the above-mentioned tabless lead frame system, the inner lead length can be increased, so that the heat resistance and moisture resistance of the package are improved. Since it is not necessary to turn the inner leads around the chip, even a large-sized chip can be accommodated in a package having a conventional size. Since the wiring length in the chip can be reduced, signal wiring delay is reduced. There is such a feature that the reflow crack resistance is improved by eliminating the tab that causes the reflow crack due to accumulation of moisture.

【０００６】また、上記ＬＯＣ構造のＬＳＩパッケージ
においては、チップに電源（電源電圧〔ＶCC〕、基準電
圧〔ＶSS〕）を供給するそれぞれのインナーリードをチ
ップの長辺に平行して引き伸ばし、それらをチップの主
面上の中央部に配置する方式が採用されている（以下、
本願においては、チップ中央部に引き伸ばされた上記電
源供給用インナーリードをバスバーリードと称する）。
このバスバーリードを有するＬＯＣ構造のＬＳＩパッケ
ージは、チップの主面のどの箇所にも短距離で電源を供
給することができるので、電源ノイズが低減され、回路
の高速動作を実現することができるという利点がある。In the LSI package having the LOC structure, inner leads for supplying power (power supply voltage [V CC ] and reference voltage [V SS ]) to the chip are extended in parallel with the long side of the chip. The method of arranging them at the center on the main surface of the chip is adopted (hereinafter, referred to as
In the present application, the power supply inner lead extended to the center of the chip is referred to as a bus bar lead.)
Since the LSI package having the LOC structure having the bus bar leads can supply power to any part of the main surface of the chip in a short distance, power supply noise can be reduced and high-speed operation of the circuit can be realized. There are advantages.

【０００７】なお、上記バスバーリードを有するＬＯＣ
構造のＬＳＩパッケージについては、日経ＢＰ社、１９
９１年２月１日発行の「日経マイクロデバイス、２月１
日号」Ｐ８９〜Ｐ９７、特願平２−２３４１９３号公報
などに記載がある。The LOC having the bus bar leads
For the structure of LSI package, see Nikkei BP, 19
"Nikkei Micro Devices, February 1, 1991"
JP-A-P89-P97, Japanese Patent Application No. 2-234193, and the like.

【０００８】[0008]

【発明が解決しようとする課題】ところが、前記バスバ
ーリードを有するＬＯＣ構造のＬＳＩパッケージは、温
度サイクル試験時にクラックが生じ易いという欠点があ
った。However, the LSI package having the LOC structure having the bus bar leads has a disadvantage that cracks are easily generated during a temperature cycle test.

【０００９】本発明者が検討したところによると、パッ
ケージクラック発生のメカニズムは、以下のようなもの
であると考えられる。According to the study by the present inventors, the mechanism of the occurrence of package cracks is considered to be as follows.

【００１０】すなわち、ＬＯＣ構造のＬＳＩパッケージ
に使用されている絶縁テープは、その熱膨張率が他の部
材（チップ、リード、樹脂）に比べて大きいため、温度
サイクル試験の低温側でこの絶縁テープが収縮した際、
その収縮応力によって絶縁テープの側面と樹脂との界面
に剥離が生じると共に、バスバーリードに撓みが発生す
る。That is, since the insulating tape used in the LSI package having the LOC structure has a higher coefficient of thermal expansion than other members (chip, lead, resin), the insulating tape is used at a lower temperature in a temperature cycle test. When shrinks,
The contraction stress causes peeling at the interface between the side surface of the insulating tape and the resin, and also causes the bus bar leads to bend.

【００１１】これにより、絶縁テープの側面と樹脂との
界面に生じた剥離がバスバーリードの側面、次いで上面
へと進展し、バスバーリードのコーナー部に応力が集中
してパッケージクラックが発生する。As a result, the peeling generated at the interface between the side surface of the insulating tape and the resin propagates to the side surface of the bus bar lead and then to the upper surface, and stress is concentrated on the corner portion of the bus bar lead to cause a package crack.

【００１２】本発明は、上述したパッケージクラック発
生のメカニズムに着目してなされたものであり、その目
的は、バスバーリードを有するＬＯＣ構造のＬＳＩパッ
ケージのクラックを防止することのできる技術を提供す
ることにある。The present invention has been made in view of the above-described mechanism of the occurrence of package cracks, and an object thereof is to provide a technique capable of preventing cracks in an LOC structure LSI package having bus bar leads. It is in.

【００１３】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１４】[0014]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１５】本発明のバスバーリードを有するＬＯＣ構
造の半導体集積回路装置（ＬＳＩパッケージ）は、下記
の構成(1）〜(8）のうち、少なくとも一つを備えてい
る。A semiconductor integrated circuit device (LSI package) having a LOC structure having bus bar leads according to the present invention has at least one of the following structures (1) to (8).

【００１６】(1).バスバーリードの複数のインナーリー
ドの延在方向と交差する部分に選択的にメッキを施し、
このメッキ部をボンディングエリアとする。(1) selectively plating portions of the bus bar leads that intersect with the extending direction of the plurality of inner leads,
This plated portion is used as a bonding area.

【００１７】(2).バスバーリードの上面に凹凸を設け
る。(2) Provide unevenness on the upper surface of the bus bar lead.

【００１８】(3).バスバーリードの側面に凹凸を設け
る。(3) Provide irregularities on the side surfaces of the bus bar leads.

【００１９】(4).バスバーリードを絶縁テープの上面と
平行する面内でジグザグ状に折り曲げる。(4) The bus bar leads are bent in a zigzag shape in a plane parallel to the upper surface of the insulating tape.

【００２０】[0020]

【００２１】(5).インナーリードおよびバスバーリード
の下面に配置される絶縁テープの面積をそれらの面積と
略等しくすることによって、絶縁テープの面積を必要最
小限まで縮小する。(5) By making the area of the insulating tape disposed on the lower surface of the inner lead and the bus bar lead substantially equal to the area of the insulating tape, the area of the insulating tape is reduced to the minimum necessary.

【００２２】(6).絶縁テープを熱膨張率1.４×１０-5／
℃以下の絶縁材料で構成する。(6) The thermal expansion coefficient of the insulating tape is 1.4 × 10 −5 /
It is composed of an insulating material of below ° C.

【００２３】[0023]

【００２４】[0024]

【作用】上記した手段(1) によれば、リード（インナー
リードおよびバスバーリード）と樹脂との接着性が向上
する。すなわち、表面にＡｇなどのメッキを施したリー
ドは、メッキ処理をしないリードに比べて樹脂との接着
力が弱いので、バスバーリードの複数のインナーリード
の延在方向と交差する部分にメッキを施し、このメッキ
部をボンディングエリアとすることにより、リードの全
面にメッキを施している従来技術に比べてリードと樹脂
との接着性が向上する。According to the above means (1), the adhesiveness between the lead (inner lead and bus bar lead) and the resin is improved. That is, a lead having a surface plated with Ag or the like has a weaker adhesive force with resin than a lead which is not plated, so that a portion of the bus bar lead which intersects with the extending direction of the plurality of inner leads is plated. By using this plated portion as a bonding area, the adhesion between the lead and the resin is improved as compared with the prior art in which the entire surface of the lead is plated.

【００２５】上記した手段(2) によれば、バスバーリー
ドの上面に凹凸を設けることにより、バスバーリードの
上面が平坦な場合に比べてバスバーリードと樹脂との接
着力が向上する。According to the above-mentioned means (2), by providing unevenness on the upper surface of the bus bar lead, the adhesive strength between the bus bar lead and the resin is improved as compared with the case where the upper surface of the bus bar lead is flat.

【００２６】上記した手段(3) によれば、バスバーリー
ドの側面に凹凸を設けることにより、バスバーリードの
撓みが抑制されると共に、応力が集中するコーナー位置
が分散されるため、バスバーリードのコーナー部への応
力集中が緩和される。According to the above-mentioned means (3), by providing irregularities on the side surfaces of the bus bar leads, the deflection of the bus bar leads is suppressed, and the corner positions where stress is concentrated are dispersed. Stress concentration on the part is reduced.

【００２７】上記した手段(4) によれば、バスバーリー
ドを絶縁テープの上面に平行な面内でジグザグ状に折り
曲げることにより、前記手段(3) と同様の効果が得ら
れ、そのコーナー部への応力集中が緩和される。According to the above means (4), the same effect as the above means (3) is obtained by bending the bus bar leads in a zigzag shape in a plane parallel to the upper surface of the insulating tape. Stress concentration is reduced.

【００２８】[0028]

【００２９】上記した手段(5) によれば、絶縁テープの
面積を必要最小限にすることにより、その収縮応力が低
減される。また、テープ接着剤の濡れにくい部分を除去
することもできる。According to the above means (5), the contraction stress of the insulating tape is reduced by minimizing the area of the insulating tape. In addition, it is possible to remove a portion of the tape adhesive that is difficult to wet.

【００３０】上記した手段(6) によれば、絶縁テープを
熱膨張率1.４×１０-5／℃以下の絶縁材料で構成するこ
とにより、その収縮応力が低減される。According to the above means (6), the shrinkage stress is reduced by forming the insulating tape from an insulating material having a thermal expansion coefficient of 1.4 × 10 −5 / ° C. or less.

【００３１】[0031]

【００３２】以下、本発明を実施例により説明する。な
お、実施例を説明するための全図において、同一の機能
を有するものは同一の符号を付け、その繰り返しの説明
は省略する。Hereinafter, the present invention will be described with reference to examples. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

【００３３】[0033]

【実施例】本実施例のＬＳＩパッケージを図１〜図３に
より説明する。図１は、このＬＳＩパッケージのインナ
ーリードおよびバスバーリードを示す要部平面図、図２
は、このＬＳＩパッケージの要部破断斜視図、図３は、
このＬＳＩパッケージの短辺方向に沿った断面図であ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An LSI package according to this embodiment will be described with reference to FIGS. FIG. 1 is a plan view of an essential part showing inner leads and bus bar leads of this LSI package.
Is a cutaway perspective view of a principal part of this LSI package, and FIG.
FIG. 3 is a cross-sectional view of the LSI package along a short side direction.

【００３４】図２および図３に示すように、本実施例の
ＬＳＩパッケージ１は、樹脂封止形ＬＳＩパッケージの
一種のＳＯＪである。このＬＳＩパッケージ１は、例え
ば４００（ｍｉｌ）のパッケージサイズを有している。
パッケージ本体２は、例えばシリコーンフィラーを添加
したエポキシ系樹脂からなり、その内部にはシリコン単
結晶からなる長方形の半導体チップ３が封止されてい
る。このチップ３の主面には、例えば１６メガビット
（Mbit）の大容量を有するＤＲＡＭが形成されている。As shown in FIGS. 2 and 3, the LSI package 1 of this embodiment is a SOJ, which is a kind of a resin-sealed LSI package. The LSI package 1 has a package size of, for example, 400 (mil).
The package body 2 is made of, for example, an epoxy resin to which a silicone filler is added, and a rectangular semiconductor chip 3 made of silicon single crystal is sealed therein. On the main surface of the chip 3, a DRAM having a large capacity of, for example, 16 megabits (Mbit) is formed.

【００３５】上記チップ３の主面上には、例えば４枚の
絶縁テープ４が接着されている。この絶縁テープ４の基
材は、例えば熱膨張率（α）が1.４×１０-5／℃以下
で、厚さが0.１mm以下のポリイミド系樹脂テープからな
り、エポキシ系またはポリイミド系の接着剤によってチ
ップ３の主面上に接着されている。On the main surface of the chip 3, for example, four insulating tapes 4 are adhered. The base material of the insulating tape 4 is, for example, a polyimide resin tape having a coefficient of thermal expansion (α) of 1.4 × 10 −5 / ° C. or less and a thickness of 0.1 mm or less. The chip 3 is bonded to the main surface of the chip 3 with an adhesive.

【００３６】上記４枚の絶縁テープ４に挟まれたチップ
３の主面の中央部には、チップ３の長辺方向に沿って複
数のボンディングパッド５が形成されている。また、上
記絶縁テープ４上には、チップ３の長辺方向に沿って複
数のインナーリード６Ａが配置されている。すなわち、
本実施例のＬＳＩパッケージ１は、チップ３の主面上に
絶縁テープ４を介してインナーリード６Ａを配置したＬ
ＯＣ（リード・オン・チップ）構造を採用している。A plurality of bonding pads 5 are formed at the center of the main surface of the chip 3 sandwiched between the four insulating tapes 4 along the long side direction of the chip 3. A plurality of inner leads 6A are arranged on the insulating tape 4 along the long side direction of the chip 3. That is,
In the LSI package 1 of the present embodiment, an inner lead 6A is disposed on the main surface of the chip 3 with an insulating tape 4 interposed therebetween.
An OC (lead-on-chip) structure is adopted.

【００３７】上記インナーリード６Ａは、パッケージ本
体２の長辺の側面から外方に延在するアウターリード６
Ｂと一体に構成されている。アウターリード６Ｂのそれ
ぞれには、規格に基づき所定の番号が付されている。本
実施例のＬＳＩパッケージ１は、例えば２４本のアウタ
ーリード６Ｂを有し、図２に示すように、パッケージ本
体２の手前の左端から右端に沿って１番端子〜６番端
子、９番端子〜１４番端子が配置され、パッケージ本体
２の向こう側の右端から左端に沿って１５番端子〜２０
番端子、２３番端子〜２８番端子が配置されている。The inner lead 6A is an outer lead 6 extending outward from the long side surface of the package body 2.
And B. A predetermined number is assigned to each of the outer leads 6B based on a standard. The LSI package 1 of this embodiment has, for example, 24 outer leads 6B, and as shown in FIG. 2, the first to sixth terminals and the ninth terminal from the left end to the right end in front of the package body 2. Nos. 15 to 20 are arranged along the left end from the right end on the other side of the package body 2.
Terminals 23 and 28 are arranged.

【００３８】上記２４本の端子のうち、パッケージ本体
２の手前の１番端子および１４番端子は電源電圧
〔ＶCC〕端子である。電源電圧〔ＶCC〕は、例えば回路
の動作電圧５〔Ｖ〕である。また、パッケージ本体２の
向こう側の１５番端子および２８番端子は基準電圧〔Ｖ
SS〕端子である。基準電圧〔ＶSS〕は、例えば回路の基
準電圧０〔Ｖ〕（ＧＮＤ）である。Of the 24 terminals, terminals 1 and 14 in front of the package body 2 are power supply voltage [V CC ] terminals. The power supply voltage [V CC ] is, for example, an operation voltage 5 [V] of the circuit. The 15th and 28th terminals on the other side of the package body 2 are connected to a reference voltage [V
SS ] terminal. The reference voltage [V SS ] is, for example, the reference voltage 0 [V] (GND) of the circuit.

【００３９】２番端子はデータ入力信号端子、３番端子
は空き端子、４番端子はライトイネーブル信号端子、５
番端子はロウアドレスストローブ信号端子、６番端子、
９〜１３番端子、１６〜２０番端子および２３番端子は
アドレス信号端子、２４番端子は空き端子、２５番端子
はカラムアドレスストローブ信号端子、２６番端子は空
き端子、２７番端子はデータ出力端子である。なお、チ
ップ３の短辺には、チップ支持用リード６Ｃが設けられ
ている。Terminal 2 is a data input signal terminal, terminal 3 is an empty terminal, terminal 4 is a write enable signal terminal,
Terminal is a row address strobe signal terminal, terminal 6,
Terminals 9 to 13, 16 to 20, and 23 are address signal terminals, terminal 24 is an empty terminal, terminal 25 is a column address strobe signal terminal, terminal 26 is an empty terminal, and terminal 27 is a data output. Terminal. Note that a chip supporting lead 6C is provided on the short side of the chip 3.

【００４０】上記アウターリード６Ｂ、インナーリード
６Ａおよびチップ支持用リード６Ｃのそれぞれは、リー
ドフレームから切断され、かつ成形されている。リード
フレームは、例えば４２アロイなどのＦｅ−Ｎｉ合金、
またはＣｕで構成されており、その板厚は１５０〜２５
０μｍ程度である。Each of the outer lead 6B, inner lead 6A, and chip supporting lead 6C is cut from a lead frame and formed. The lead frame is made of, for example, a Fe-Ni alloy such as 42 alloy,
Or, it is composed of Cu, and its plate thickness is 150 to 25.
It is about 0 μm.

【００４１】上記２４本のインナーリード６Ａのうち、
電源電圧〔ＶCC〕端子である１番端子および１４番端子
は、図２の手前の絶縁テープ４上のバスバーリード７と
一体に形成されている。また、基準電圧〔ＶSS〕端子で
ある１５番端子および２８番端子は、図２の向こう側の
絶縁テープ４上のバスバーリード７と一体に形成されて
いる。上記一対のバスバーリード７，７のそれぞれは、
コの字状のパターンを有しており、例えばエポキシ系ま
たはポリイミド系接着剤によって絶縁テープ４上に接着
されている。Of the above 24 inner leads 6A,
Pin 1 and Pin 14 is the power supply voltage [V CC] terminal is formed integrally with the bus bar lead 7 on the front of the insulating tape 4 in FIG. Terminals 15 and 28, which are reference voltage [ VSS ] terminals, are formed integrally with the bus bar leads 7 on the insulating tape 4 on the other side in FIG. Each of the pair of busbar leads 7, 7
It has a U-shaped pattern, and is adhered onto the insulating tape 4 by, for example, an epoxy-based or polyimide-based adhesive.

【００４２】上記バスバーリード７によって三方を囲ま
れたインナーリード６Ａ（２番端子〜６番端子、９番端
子〜１３番端子、１６番端子〜２０番端子、２３番端子
〜２７番端子）のそれぞれは、エポキシ系またはポリイ
ミド系接着剤によって絶縁テープ４上に接着されてい
る。The inner lead 6A (terminals 2 to 6, terminals 9 to 13, terminal 16 to terminal 20, terminal 23 to terminal 27) surrounded on three sides by the bus bar lead 7 described above. Each is adhered on the insulating tape 4 by an epoxy or polyimide adhesive.

【００４３】上記インナーリード６Ａのそれぞれは、ボ
ンディングワイヤ８を通じてチップ３のボンディングパ
ッド５と電気的に接続されている。電源電圧〔ＶCC〕端
子を構成するインナーリード６Ａに接続されるボンディ
ングワイヤ８、および基準電圧〔ＶSS〕端子を構成する
インナーリード６Ａに接続されるワイヤ８のそれぞれの
一端は、バスバーリード７上にボンディングされてい
る。また、信号端子を構成するインナーリード６Ａに接
続されるボンディングワイヤ８のそれぞれの一端は、バ
スバーリード７の上を跨ぐようにしてインナーリード６
Ａ上にボンディングされている。Each of the inner leads 6A is electrically connected to the bonding pad 5 of the chip 3 through a bonding wire 8. One end of each of the bonding wire 8 connected to the inner lead 6A constituting the power supply voltage [V CC ] terminal and the wire 8 connected to the inner lead 6A constituting the reference voltage [V SS ] terminal is connected to the bus bar lead 7. Bonded on top. One end of each of the bonding wires 8 connected to the inner leads 6 </ b> A constituting the signal terminals extends over the bus bar leads 7.
A is bonded on A.

【００４４】上記ボンディングワイヤ８は、Ａｕ、Ｃ
ｕ、Ａｌあるいはこれらの金属の表面に絶縁性樹脂を被
覆した被覆ワイヤからなる。また、ボンディングワイヤ
８は、例えば熱圧着に超音波振動を併用したボンディン
グ法を用いてボンディングされている。The bonding wires 8 are made of Au, C
u, Al or a coated wire in which the surface of these metals is coated with an insulating resin. The bonding wire 8 is bonded using, for example, a bonding method in which ultrasonic vibration is used in combination with thermocompression bonding.

【００４５】図１に示すように、上記インナーリード６
Ａおよびバスバーリード７の上面において、ボンディン
グワイヤ８の一端が接続される領域（ボンディングエリ
ア））には、Ａｇ、ＡｕまたはＰｄからなるメッキパタ
ーン９が形成されている。すなわち、本実施例のＬＳＩ
パッケージ１は、インナーリード６ａおよびバスバーリ
ード７のボンディングエリアだけにメッキを施し、その
他のエリアにはメッキを施していない。具体的には、図
１に示されるように、インナーリード６Ａの先端部の上
面、およびバスバーリード７のインナーリード６Ａの延
在方向と交差する部分の選択された領域の上面のみにメ
ッキが施され、それらのメッキ領域はボンディングエリ
アであり、そのメッキ領域にワイヤボンディングがなさ
れる。As shown in FIG. 1, the inner lead 6
A plating pattern 9 made of Ag, Au or Pd is formed in a region (bonding area) to which one end of the bonding wire 8 is connected on the upper surface of the A and the bus bar lead 7. That is, the LSI of the present embodiment
In the package 1, only the bonding area of the inner lead 6a and the bus bar lead 7 is plated, and the other areas are not plated. Specifically, as shown in FIG. 1, plating is applied only to the upper surface of the tip of the inner lead 6A and only to the upper surface of a selected region of the bus bar lead 7 which intersects with the extending direction of the inner lead 6A. These plating areas are bonding areas, and wire bonding is performed on the plating areas.

【００４６】また、図１および図３に示すように、上記
バスバーリード７は、絶縁テープ４の外縁よりも内側に
配置されている。すなわち、本実施例のＬＳＩパッケー
ジ１は、バスバーリード７の側面を絶縁テープ４の側面
から遠ざけている。As shown in FIGS. 1 and 3, the bus bar leads 7 are arranged inside the outer edge of the insulating tape 4. That is, in the LSI package 1 of the present embodiment, the side surface of the bus bar lead 7 is kept away from the side surface of the insulating tape 4.

【００４７】以上のように構成された本実施例によれ
ば、下記のような作用、効果を得ることができる。According to the present embodiment configured as described above, the following operations and effects can be obtained.

【００４８】(1).インナーリード６Ａおよびバスバーリ
ード７のボンディングエリアだけにメッキを施し、その
他のエリアにはメッキを施さないことにより、インナー
リード６Ａおよびバスバーリード７の全面にメッキを施
す場合に比べて、インナーリード６Ａおよびバスバーリ
ード７とパッケージ本体２を構成する樹脂との接着性が
向上する。(1) When plating is performed only on the bonding area of the inner lead 6A and the bus bar lead 7 and is not plated on the other area, the plating is performed on the entire surface of the inner lead 6A and the bus bar lead 7. In comparison, the adhesiveness between the inner lead 6A and the bus bar lead 7 and the resin forming the package body 2 is improved.

【００４９】(2).バスバーリード７の側面を絶縁テープ
４の側面から遠ざけることにより、万一絶縁テープ４の
側面と樹脂との界面に剥離が生じた場合でも、この剥離
がバスバーリード７の側面へと進展するのを防止するこ
とができる。(2) By separating the side surface of the bus bar lead 7 from the side surface of the insulating tape 4, even if the interface between the side surface of the insulating tape 4 and the resin should occur, this separation will It can be prevented from progressing to the side.

【００５０】(3).絶縁テープ４を熱膨張率1.４×１０-5
／℃以下の絶縁材料で構成することにより、その収縮応
力を低減することができる。(3) The thermal expansion coefficient of the insulating tape 4 is 1.4 × 10 −5.
By using an insulating material having a temperature of / ° C. or lower, the shrinkage stress can be reduced.

【００５１】(4).絶縁テープ４の厚さを0.１mm以下にす
ることにより、その体積が小さくなるので、その収縮応
力を低減することができる。(4) By reducing the thickness of the insulating tape 4 to 0.1 mm or less, its volume is reduced, so that its shrinkage stress can be reduced.

【００５２】(5).上記(1) 〜(4) により、パッケージク
ラックの発生率を低減することができるので、ＤＲＡＭ
の動作信頼性、寿命が向上する。(5) According to the above (1) to (4), the rate of occurrence of package cracks can be reduced.
The operating reliability and life of the device are improved.

【００５３】図４は、本発明の他の実施例であるＬＳＩ
パッケージ１のインナーリード６Ａおよびバスバーリー
ド７を示す要部平面図である。FIG. 4 shows an LSI according to another embodiment of the present invention.
FIG. 3 is a plan view of a main part showing an inner lead 6A and a bus bar lead 7 of the package 1;

【００５４】本図に示すように、インナーリード６Ａお
よびバスバーリード７のそれぞれの下面に配置された絶
縁テープ４は、その面積がインナーリード６Ａおよびバ
スバーリード７の面積と略等しくなっている。このよう
に、本実施例のＬＳＩパッケージ１は、絶縁テープ４の
面積を必要最小限まで縮小し、その収縮応力を低減した
ので、パッケージクラックの発生率を低減することがで
きる。As shown in the drawing, the area of the insulating tape 4 disposed on the lower surface of each of the inner lead 6A and the bus bar lead 7 is substantially equal to the area of the inner lead 6A and the bus bar lead 7. As described above, in the LSI package 1 of the present embodiment, the area of the insulating tape 4 is reduced to a necessary minimum and the shrinkage stress is reduced, so that the rate of occurrence of package cracks can be reduced.

【００５５】図５は、本発明の他の実施例であるＬＳＩ
パッケージ１のインナーリード６Ａおよびバスバーリー
ド７を示す要部平面図である。FIG. 5 shows an LSI according to another embodiment of the present invention.
FIG. 3 is a plan view of a main part showing an inner lead 6A and a bus bar lead 7 of the package 1;

【００５６】本図に示すように、バスバーリード７は、
その側面の一部に凹凸パターン１０が設けられている。
これにより、絶縁テープ４の収縮応力に起因するバスバ
ーリード７の撓みが抑制されるので、パッケージクラッ
クの発生率を低減することができる。As shown in the figure, the bus bar lead 7 is
An uneven pattern 10 is provided on a part of the side surface.
This suppresses the deflection of the bus bar leads 7 due to the shrinkage stress of the insulating tape 4, so that the rate of occurrence of package cracks can be reduced.

【００５７】図６は、本発明の他の実施例であるＬＳＩ
パッケージ１の短辺方向に沿った断面図である。FIG. 6 shows an LSI according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view of the package 1 along a short side direction.

【００５８】本図に示すように、バスバーリード７は、
その厚さがインナーリード６Ａよりも薄くなっている。
これにより、バスバーリード７のコーナー部に集中する
応力が低減されるので、パッケージクラックの発生率を
低減することができる。As shown in the figure, the bus bar lead 7
The thickness is smaller than the inner lead 6A.
This reduces the stress concentrated on the corners of the bus bar leads 7, thereby reducing the rate of occurrence of package cracks.

【００５９】バスバーリード７の厚さをインナーリード
６Ａよりも薄く加工するには、例えばプレスで圧潰した
り、エッチングしたりすればよい。In order to make the thickness of the bus bar lead 7 thinner than that of the inner lead 6A, for example, it may be crushed by a press or etched.

【００６０】図７は、本発明の他の実施例であるＬＳＩ
パッケージ１のインナーリード６Ａおよびバスバーリー
ド７を示す要部平面図である。FIG. 7 shows an LSI according to another embodiment of the present invention.
FIG. 3 is a plan view of a main part showing an inner lead 6A and a bus bar lead 7 of the package 1;

【００６１】本図に示すように、バスバーリード７は、
その上面に多数のディンプル（窪み）１１が設けられて
いる。これにより、上面が平坦な場合に比べてバスバー
リード７とパッケージ本体２を構成する樹脂との接着力
が向上するので、パッケージクラックの発生率を低減す
ることができる。As shown in the figure, the bus bar lead 7 is
Many dimples (dents) 11 are provided on the upper surface. As a result, the adhesive strength between the bus bar leads 7 and the resin forming the package body 2 is improved as compared with the case where the upper surface is flat, so that the rate of occurrence of package cracks can be reduced.

【００６２】図８は、本発明の他の実施例であるＬＳＩ
パッケージ１のインナーリード６Ａおよびバスバーリー
ド７を示す要部平面図である。FIG. 8 shows an LSI according to another embodiment of the present invention.
FIG. 3 is a plan view of a main part showing an inner lead 6A and a bus bar lead 7 of the package 1;

【００６３】本図に示すように、バスバーリード７は、
絶縁フィルム４の上面に平行な面内でジクザグ状に折り
曲げられている。これにより、絶縁テープ４の収縮応力
に起因するバスバーリード７の撓みが抑制されるので、
そのコーナー部への応力集中が緩和され、パッケージク
ラックの発生率を低減することができる。As shown in the figure, the bus bar lead 7
It is bent in a zigzag shape in a plane parallel to the upper surface of the insulating film 4. Thereby, the bending of the bus bar lead 7 due to the contraction stress of the insulating tape 4 is suppressed,
Stress concentration at the corners is reduced, and the rate of occurrence of package cracks can be reduced.

【００６４】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

【００６５】実施例では、本発明をＳＯＪに適用した場
合について説明したが、これに限定されるものではな
く、少なくともバスバーリードを有するＬＯＣ構造の樹
脂封止形ＬＳＩパッケージ全般に適用することができ
る。In the embodiment, the case where the present invention is applied to the SOJ has been described. However, the present invention is not limited to this. The present invention can be applied to at least a general resin-sealed LSI package having a LOC structure having bus bar leads. .

【００６６】[0066]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下の通りである。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

【００６７】本発明によれば、バスバーリードを有する
ＬＯＣ構造の樹脂封止形ＬＳＩパッケージのクラック発
生率を低減することができるので、樹脂封止形ＬＳＩパ
ッケージの信頼性、寿命が向上する。According to the present invention, the rate of occurrence of cracks in a resin-sealed LSI package having a LOC structure having bus bar leads can be reduced, so that the reliability and life of the resin-sealed LSI package can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例である半導体集積回路装置の
要部平面図である。FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.

【図２】この半導体集積回路装置の要部破断斜視図であ
る。FIG. 2 is a cutaway perspective view of a main part of the semiconductor integrated circuit device.

【図３】この半導体集積回路装置の断面図である。FIG. 3 is a sectional view of the semiconductor integrated circuit device.

【図４】本発明の他の実施例である半導体集積回路装置
の要部平面図である。FIG. 4 is a main part plan view of a semiconductor integrated circuit device according to another embodiment of the present invention;

【図５】本発明の他の実施例である半導体集積回路装置
の要部平面図である。FIG. 5 is a main part plan view of a semiconductor integrated circuit device according to another embodiment of the present invention;

【図６】本発明の他の実施例である半導体集積回路装置
の断面図である。FIG. 6 is a sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

【図７】本発明の他の実施例である半導体集積回路装置
の要部平面図である。FIG. 7 is a plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention;

【図８】本発明の他の実施例である半導体集積回路装置
の要部平面図である。FIG. 8 is a plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ ＬＳＩパッケージ ２ パッケージ本体 ３ 半導体チップ ４ 絶縁テープ ５ ボンディングパッド ６Ａ インナーリード ６Ｂ アウターリード ６Ｃ チップ支持用リード ７ バスバーリード ８ ボンディングワイヤ ９ メッキパターン １０ 凹凸パターン １１ ディンプル（窪み） DESCRIPTION OF SYMBOLS 1 LSI package 2 Package body 3 Semiconductor chip 4 Insulating tape 5 Bonding pad 6A Inner lead 6B Outer lead 6C Chip supporting lead 7 Bus bar lead 8 Bonding wire 9 Plating pattern 10 Uneven pattern 11 Dimple (dent)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 安生 一郎 東京都小平市上水本町５丁目20番１号 株式会社日立製作所 武蔵工場内 (72)発明者 村上 元 東京都小平市上水本町５丁目20番１号 株式会社日立製作所 武蔵工場内 (56)参考文献 特開 平４−114438（ＪＰ，Ａ) 特開 平４−219965（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/50 H01L 21/60 301 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ichiro Yasuo 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Musashi Plant, Hitachi, Ltd. (72) Inventor Gen Murakami 5-chome, Josuihoncho, Kodaira-shi, Tokyo No. 20 No. 1 Inside the Musashi Plant, Hitachi, Ltd. (56) References JP-A-4-114438 (JP, A) JP-A-4-219965 (JP, A) (58) Fields investigated (Int. Cl. 6) , DB name) H01L 23/50 H01L 21/60 301

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップの主面上に絶縁テープを介
してバスバーリードおよび複数のインナーリードを配置
し、前記バスバーリードおよび複数のインナーリードと
前記半導体チップのボンディングパッドとをボンディン
グワイヤにより結線し、前記複数のインナーリード、バ
スバーリード、ボンディングワイヤおよび半導体チップ
を樹脂で封止するリード・オン・チップ構造を有する半
導体集積回路装置であって、前記バスバーリードの前記
インナーリードの延在方向と交差する部分に選択的にメ
ッキを施し、このメッキ部をボンディングエリアとした
ことを特徴とする半導体集積回路装置。1. A bus bar lead and a plurality of inner leads are arranged on a main surface of a semiconductor chip via an insulating tape, and the bus bar lead and the plurality of inner leads are connected to bonding pads of the semiconductor chip by bonding wires. A semiconductor integrated circuit device having a lead-on-chip structure for sealing the plurality of inner leads, bus bar leads, bonding wires and a semiconductor chip with a resin, wherein the bus bar leads intersect with the extending direction of the inner leads. A semiconductor integrated circuit device characterized in that a portion to be plated is selectively plated, and the plated portion is used as a bonding area. 【請求項２】 半導体チップの主面上に絶縁テープを介
してバスバーリードおよび複数のインナーリードを配置
し、前記バスバーリードおよび複数のインナーリードと
前記半導体チップのボンディングパッドとをボンディン
グワイヤにより結線し、前記複数のインナーリード、バ
スバーリード、ボンディングワイヤおよび半導体チッブ
を樹脂で封止するリード・オン・チップ構造を有する半
導体集積回路装置であって、前記バスバーリードの上面
に凹凸を設けたことを特徴とする半導体集積回路装置。2. A bus bar lead and a plurality of inner leads are arranged on a main surface of a semiconductor chip via an insulating tape, and the bus bar lead and the plurality of inner leads are connected to bonding pads of the semiconductor chip by bonding wires. A semiconductor integrated circuit device having a lead-on-chip structure for sealing the plurality of inner leads, bus bar leads, bonding wires and semiconductor chips with a resin, wherein irregularities are provided on an upper surface of the bus bar leads. Semiconductor integrated circuit device. 【請求項３】 半導体チップの主面上に絶縁テープを介
してバスバーリードおよび複数のインナーリードを配置
し、前記バスバーリードおよび複数のインナーリードと
前記半導体チップのボンディングパッドとをボンディン
グワイヤにより結線し、前記複数のインナーリード、バ
スバーリード、ボンディングワイヤおよび半導体チッブ
を樹脂で封止するリード・オン・チップ構造を有する半
導体集積回路装置であって、前記バスバーリードの側面
に凹凸を設けたことを特徴とする半導体集積回路装置。3. A bus bar lead and a plurality of inner leads are arranged on a main surface of a semiconductor chip via an insulating tape, and the bus bar lead and the plurality of inner leads are connected to bonding pads of the semiconductor chip by bonding wires. A semiconductor integrated circuit device having a lead-on-chip structure for sealing the plurality of inner leads, bus bar leads, bonding wires and semiconductor chips with resin, wherein irregularities are provided on side surfaces of the bus bar leads. Semiconductor integrated circuit device. 【請求項４】 半導体チップの主面上に絶縁テープを介
してバスバーリードおよび複数のインナーリードを配置
し、前記バスバーリードおよび複数のインナーリードと
前記半導体チップのボンディングパッドとをボンディン
グワイヤにより結線し、前記複数のインナーリード、バ
スバーリード、ボンディングワイヤおよび半導体チッブ
を樹脂で封止するリード・オン・チップ構造を有する半
導体集積回路装置であって、前記バスバーリードを前記
絶縁テープの上面に平行な面内でジグザグ状に折り曲げ
たことを特徴とする半導体集積回路装置。4. A bus bar lead and a plurality of inner leads are arranged on a main surface of a semiconductor chip via an insulating tape, and the bus bar lead and the plurality of inner leads are connected to bonding pads of the semiconductor chip by bonding wires. A semiconductor integrated circuit device having a lead-on-chip structure for sealing the plurality of inner leads, bus bar leads, bonding wires and semiconductor chips with resin, wherein the bus bar leads are parallel to an upper surface of the insulating tape; A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is bent in a zigzag shape. 【請求項５】 半導体チップの主面上に絶縁テープを介
してバスバーリードおよび複数のインナーリードを配置
し、前記バスバーリードおよび複数のインナーリードと
前記半導体チップのボンディングパッドとをボンディン
グワイヤにより結線し、前記複数のインナーリード、バ
スバーリード、ボンディングワイヤおよび半導体チッブ
を樹脂で封止するリード・オン・チップ構造を有する半
導体集積回路装置であって、前記インナーリードおよび
前記バスバーリードの下面に配置された前記絶縁テープ
の面積を前記インナーリードおよび前記バスバーリード
の面積と略等しくしたことを特徴とする半導体集積回路
装置。5. A bus bar lead and a plurality of inner leads are arranged on a main surface of a semiconductor chip via an insulating tape, and the bus bar lead and the plurality of inner leads are connected to bonding pads of the semiconductor chip by bonding wires. A semiconductor integrated circuit device having a lead-on-chip structure for sealing the plurality of inner leads, bus bar leads, bonding wires, and semiconductor chips with a resin, wherein the semiconductor integrated circuit device is disposed on lower surfaces of the inner leads and the bus bar leads. 2. The semiconductor integrated circuit device according to claim 1, wherein an area of said insulating tape is substantially equal to an area of said inner lead and said bus bar lead. 【請求項６】 半導体チップの主面上に絶縁テープを介
してバスバーリードおよび複数のインナーリードを配置
し、前記バスバーリードおよび複数のインナーリードと
前記半導体チップのボンディングパッドとをボンディン
グワイヤにより結線し、前記複数のインナーリード、バ
スバーリード、ボンディングワイヤおよび半導体チッブ
を樹脂で封止するリード・オン・チップ構造を有する半
導体集積回路装置であって、前記絶縁テープが熱膨張率
1.４×１０-5／℃以下の絶縁材料からなることを特徴と
する半導体集積回路装置。6. A bus bar lead and a plurality of inner leads are arranged on a main surface of a semiconductor chip via an insulating tape, and the bus bar lead and the plurality of inner leads are connected to bonding pads of the semiconductor chip by bonding wires. A semiconductor integrated circuit device having a lead-on-chip structure for sealing the plurality of inner leads, bus bar leads, bonding wires and semiconductor chips with a resin, wherein the insulating tape has a thermal expansion coefficient
A semiconductor integrated circuit device comprising an insulating material having a temperature of 1.4 × 10 −5 / ° C. or less.
JP3052416A 1991-03-18 1991-03-18 Semiconductor integrated circuit device Expired - Lifetime JP2971594B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3052416A JP2971594B2 (en) 1991-03-18 1991-03-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3052416A JP2971594B2 (en) 1991-03-18 1991-03-18 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH04287356A JPH04287356A (en) 1992-10-12
JP2971594B2 true JP2971594B2 (en) 1999-11-08

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ID=12914190

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Country Link
JP (1) JP2971594B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3109707B2 (en) * 1993-03-29 2000-11-20 日立化成工業株式会社 Heat resistant adhesive and semiconductor package containing the same
JP3169072B2 (en) 1998-05-15 2001-05-21 日本電気株式会社 Semiconductor device

Also Published As

Publication number Publication date
JPH04287356A (en) 1992-10-12

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