JPH06333977A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH06333977A JPH06333977A JP5147050A JP14705093A JPH06333977A JP H06333977 A JPH06333977 A JP H06333977A JP 5147050 A JP5147050 A JP 5147050A JP 14705093 A JP14705093 A JP 14705093A JP H06333977 A JPH06333977 A JP H06333977A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor substrate
- bonding
- metal layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
- H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関し、特に耐湿性強度向上を目的とする構造を
有する半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a structure intended to improve moisture resistance and strength and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来のボンディング工程前の半導体装置
は、図５に示すように、半導体基板１１上の一部に、金
属層であるボンディングパッド１２が形成されており、
半導体基板１１を保護するためのパッシベーション膜１
４が、ボンディングパッド１２とボンディングワイヤと
を接続するための開口部１５をボンディングパッド１２
上に露出させるように、半導体基板１１上に形成された
構造であった。2. Description of the Related Art As shown in FIG. 5, a conventional semiconductor device before a bonding step has a bonding pad 12, which is a metal layer, formed on a part of a semiconductor substrate 11.
Passivation film 1 for protecting semiconductor substrate 11
4, the bonding pad 12 has an opening 15 for connecting the bonding pad 12 and the bonding wire.
The structure was formed on the semiconductor substrate 11 so as to be exposed above.
【０００３】[0003]
【発明が解決しようとする課題】上述の構造を有する半
導体装置にワイヤボンディングを施した場合、図６に示
すように、接点１７に於いてボンディングワイヤ１６を
ボンディングパッド１２に接続した後も、ボンディング
パッド１２の表面の一部１８が開口部１５の底面に露出
した状態であるために、例えば外部からの水分侵入によ
り露出部１８が腐蝕し、断線に至る危険性があった。When wire bonding is applied to the semiconductor device having the above structure, as shown in FIG. 6, even after the bonding wire 16 is connected to the bonding pad 12 at the contact 17, the bonding is performed. Since a part 18 of the surface of the pad 12 is exposed to the bottom surface of the opening 15, there is a risk that the exposed portion 18 will be corroded by moisture intrusion from the outside, leading to disconnection.
【０００４】このような従来技術の問題点に鑑み、本発
明の主な目的は、外部からの水分侵入等により金属層で
あるボンディングパッドが腐蝕されることがない、耐温
性に優れる半導体装置を提供することにある。In view of the above problems of the prior art, the main object of the present invention is to prevent the corrosion of the bonding pad, which is a metal layer, due to the intrusion of moisture from the outside, and the semiconductor device having excellent temperature resistance. To provide.
【０００５】[0005]
【課題を解決するための手段】上述した目的は本発明に
よれば、半導体基板と、前記半導体基板上に形成された
ボンディングパッドとしての金属層と、前記金属層の全
面に形成された、該金属層の表面保護膜としての被膜と
を有することを特徴とする半導体装置、及び半導体装置
の製造方法であって、半導体基板上にボンディングパッ
ドとしての金属層を形成する過程と、前記金属層の全面
に該金属層の表面保護膜としての被膜を形成する過程
と、前記半導体基板上及び前記被膜上に前記半導体基板
の保護膜としてのパッシベーション膜を形成する過程
と、前記被膜を露出させるべく前記被膜上の前記パッシ
ベーション膜に開口を設ける過程と、前記金属層とボン
ディングワイヤとが接触するように、前記開口内にて露
出した前記被膜上から前記ボンディングワイヤを接着す
る過程とを有することを特徴とする半導体装置の製造方
法を提供することにより達成される。尚、前記被膜が数
１０ｎｍ以下の厚さを有する酸化膜であると更によい。According to the present invention, the above object is achieved by forming a semiconductor substrate, a metal layer as a bonding pad formed on the semiconductor substrate, and a metal layer formed on the entire surface of the metal layer. A semiconductor device having a coating as a surface protective film of a metal layer, and a method for manufacturing a semiconductor device, which comprises a step of forming a metal layer as a bonding pad on a semiconductor substrate, and a step of forming the metal layer. A step of forming a film as a surface protective film of the metal layer on the entire surface, a step of forming a passivation film as a protective film of the semiconductor substrate on the semiconductor substrate and the film, and a step for exposing the film. A process of forming an opening in the passivation film on the film, and a process of exposing the film in the opening so that the metal layer and the bonding wire come into contact with each other. It is achieved by providing a method of manufacturing a semiconductor device characterized by having a step of bonding the serial bonding wire. It is more preferable that the coating film is an oxide film having a thickness of several tens nm or less.
【０００６】[0006]
【作用】このようにすれば、ボンディングワイヤを接続
した後でも、ボンディングワイヤとの接続部以外のボン
ディングパッド表面に酸化膜が残るため、ボンディング
パッドが露出せず、外部からの水分侵入によるボンディ
ングパッドの腐蝕を防止することができる。With this structure, even after the bonding wire is connected, the oxide film remains on the surface of the bonding pad other than the connection portion with the bonding wire, so that the bonding pad is not exposed, and the bonding pad due to the intrusion of moisture from the outside is exposed. It is possible to prevent corrosion.
【０００７】[0007]
【実施例】以下、本発明の好適実施例を添付の図面につ
いて詳しく説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.
【０００８】図１は、本発明が適用された半導体装置の
一部分を示す縦断面図である。FIG. 1 is a vertical sectional view showing a part of a semiconductor device to which the present invention is applied.
【０００９】半導体基板１上には図示されない電気回路
が形成されている。この電気回路からの信号を外部に取
り出すため、または取り入れるために、例えばＡｌ（ア
ルミニウム）からなるボンディングパッド２が半導体基
板１上に形成されている。また、ボンディングパッド２
上には、厚さ数１０ｎｍ以下のＳｉＯ2（酸化シリコ
ン）からなる酸化膜３が形成されている。更に、ＳｉＮ
等からなるパッシベーション膜４が、酸化膜３を露出さ
せるための開口部５以外の半導体基板１上に形成されて
いる。An electric circuit (not shown) is formed on the semiconductor substrate 1. A bonding pad 2 made of, for example, Al (aluminum) is formed on the semiconductor substrate 1 in order to take out or take in a signal from the electric circuit to the outside. Also, the bonding pad 2
An oxide film 3 made of SiO 2 (silicon oxide) having a thickness of several 10 nm or less is formed on the top. Furthermore, SiN
A passivation film 4 made of, for example, is formed on the semiconductor substrate 1 except the opening 5 for exposing the oxide film 3.
【００１０】次に、上述した半導体装置の製造工程の一
例を、図２及び図３を参照しながら説明する。Next, an example of the manufacturing process of the above-mentioned semiconductor device will be described with reference to FIGS.
【００１１】まず、図２に示すように、半導体基板１上
にアルミニウム等の金属からなるボンディングパッド２
を所望のパターンに形成する。次に、図３に示すよう
に、ボンディングパッド２上にＳｉＯ2膜等の酸化膜３
を選択的に形成する。ここで、酸化膜３の厚さは数１０
ｎｍ以下とする。次に、半導体基板１の全面にＳｉＯ等
のパッシベーション膜４を形成した後、ドライエッチン
グ法を用いて酸化膜３上に開口部５を形成することによ
り、図１に示す半導体装置が完成する。First, as shown in FIG. 2, a bonding pad 2 made of a metal such as aluminum is formed on a semiconductor substrate 1.
Are formed into a desired pattern. Next, as shown in FIG. 3, an oxide film 3 such as a SiO 2 film is formed on the bonding pad 2.
Are selectively formed. Here, the thickness of the oxide film 3 is several tens.
nm or less. Next, a passivation film 4 of SiO or the like is formed on the entire surface of the semiconductor substrate 1, and then an opening 5 is formed on the oxide film 3 by using a dry etching method to complete the semiconductor device shown in FIG.
【００１２】続いて、本実施例の半導体装置を用いてワ
イヤボンディングを行った場合について、図４を用いて
説明する。Next, a case where wire bonding is performed using the semiconductor device of this embodiment will be described with reference to FIG.
【００１３】まず、熱圧着法や熱音波熱圧着法等を用い
て、Ａｕ（金）等からなるボンディングワイヤ６を、開
口部５の底面に露出した酸化膜３に５０グラムから８０
グラムの圧力で押し付ける。酸化膜３は約数１０ｎｍ以
下の厚みであるため、ボンディング時の熱と圧力によっ
てつぶされ、ボンディングパッド２とボンディングワイ
ヤ６とが接点７に於いて融着する。このとき、アルミニ
ウムからなるボンディングパッド２と金からなるボンデ
ィングワイヤ６とが合金状態となり、電気的には全く問
題なく接続される。また、接点７以外のボンディングパ
ッド２の表面には酸化膜３が残ってボンディンパッド２
を保護する。First, using a thermocompression bonding method or a thermosonic thermocompression bonding method, a bonding wire 6 made of Au (gold) or the like is applied to the oxide film 3 exposed on the bottom surface of the opening 5 from 50 g to 80 g.
Press with gram pressure. Since the oxide film 3 has a thickness of about several tens of nm or less, it is crushed by heat and pressure during bonding, and the bonding pad 2 and the bonding wire 6 are fused at the contact 7. At this time, the bonding pad 2 made of aluminum and the bonding wire 6 made of gold are in an alloy state and are electrically connected without any problem. In addition, the oxide film 3 remains on the surface of the bonding pad 2 other than the contact 7, and the bond pad 2
Protect.
【００１４】尚、本実施例に於いては、ボンディングパ
ッド２とボンディングワイヤ６との融着を熱圧着法を用
いて行ったが、酸化膜３が破壊される方法であれば、他
の圧力を用いる方法を用いてもよいし、また熱音波振動
による方法を用いてもよい。In the present embodiment, the bonding pad 2 and the bonding wire 6 are fused by the thermocompression bonding method, but if the method is to destroy the oxide film 3, another pressure is applied. May be used, or a method using thermosonic vibration may be used.
【００１５】[0015]
【発明の効果】以上説明したように、本発明による半導
体装置によれば、ボンディングワイヤを接続した後で
も、ボンディングパッドの露出部全面が酸化膜で保護さ
れるため、外部からの水分侵入等によりボンディングパ
ッドが腐蝕することがなく、耐湿性強度が大いに向上す
る。As described above, according to the semiconductor device of the present invention, even after the bonding wire is connected, the entire exposed surface of the bonding pad is protected by the oxide film. The bonding pad is not corroded, and the moisture resistance strength is greatly improved.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明に係る半導体装置の一例を示す縦断面図
である。FIG. 1 is a vertical sectional view showing an example of a semiconductor device according to the present invention.
【図２】図３と共に図１の半導体装置の製造工程を説明
する図である。FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor device of FIG. 1 together with FIG.
【図３】図２と共に図１の半導体装置の製造工程を説明
する図である。FIG. 3 is a diagram illustrating a manufacturing process of the semiconductor device of FIG. 1 together with FIG.
【図４】図１の半導体装置を用いてワイヤボンディング
を行った場合の一例を示す縦断面図である。FIG. 4 is a vertical cross-sectional view showing an example when wire bonding is performed using the semiconductor device of FIG.
【図５】従来の半導体装置を示す縦断面図である。FIG. 5 is a vertical cross-sectional view showing a conventional semiconductor device.
【図６】図５に示す従来の半導体装置を用いてワイヤボ
ンディングを行った場合の一例を示す縦断面図である。6 is a vertical cross-sectional view showing an example of wire bonding performed using the conventional semiconductor device shown in FIG.
１ 半導体基板 ２ ボンディングパッド ３ 酸化膜 ４ パッシベーション膜 ５ 開口部 ６ ボンディングワイヤ ７ ボンディングパッドとボンディングワイヤとの接点 １１ 半導体基板 １２ ボンディングパッド １３ 酸化膜 １４ パッシベーション膜 １５ 開口部 １６ ボンディングワイヤ １７ ボンディングパッドとボンディングワイヤとの接
点 １８ ワイヤボンディング後のボンディングパッドの露
出部1 semiconductor substrate 2 bonding pad 3 oxide film 4 passivation film 5 opening 6 bonding wire 7 contact point between bonding pad and bonding wire 11 semiconductor substrate 12 bonding pad 13 oxide film 14 passivation film 15 opening 16 bonding wire 17 bonding pad and bonding Contact with wire 18 Exposed part of bonding pad after wire bonding
Claims (4)
ての金属層と、 前記金属層の全面に形成された、該金属層の表面保護膜
としての被膜とを有することを特徴とする半導体装置。1. A semiconductor substrate, a metal layer as a bonding pad formed on the semiconductor substrate, and a film formed on the entire surface of the metal layer as a surface protective film of the metal layer. Characteristic semiconductor device.
る酸化膜であることを特徴とする請求項１に記載の半導
体装置。2. The semiconductor device according to claim 1, wherein the coating film is an oxide film having a thickness of several tens nm or less.
成する過程と、 前記金属層の全面に該金属層の表面保護膜としての被膜
を形成する過程と、 前記半導体基板上及び前記被膜上に前記半導体基板の保
護膜としてのパッシベーション膜を形成する過程と、 前記被膜を露出させるべく前記被膜上の前記パッシベー
ション膜に開口を設ける過程と、 前記金属層とボンディングワイヤとが接触するように、
前記開口内にて露出した前記被膜上から前記ボンディン
グワイヤを接着する過程とを有することを特徴とする半
導体装置の製造方法。3. A method of manufacturing a semiconductor device, comprising: forming a metal layer as a bonding pad on a semiconductor substrate; and forming a film as a surface protective film of the metal layer on the entire surface of the metal layer. A step of forming a passivation film as a protective film of the semiconductor substrate on the semiconductor substrate and the coating film, a step of forming an opening in the passivation film on the coating film to expose the coating film, and the metal layer Contact the bonding wire with
And a step of adhering the bonding wire on the coating film exposed in the opening.
る酸化膜であることを特徴とする請求項３に記載の半導
体装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 3, wherein the coating film is an oxide film having a thickness of several tens of nm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147050A JPH06333977A (en) | 1993-05-25 | 1993-05-25 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147050A JPH06333977A (en) | 1993-05-25 | 1993-05-25 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06333977A true JPH06333977A (en) | 1994-12-02 |
Family
ID=15421371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5147050A Pending JPH06333977A (en) | 1993-05-25 | 1993-05-25 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06333977A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010171421A (en) * | 2008-12-26 | 2010-08-05 | National Institute Of Advanced Industrial Science & Technology | Semiconductor device and manufacturing method thereof |
| WO2013190638A1 (en) * | 2012-06-19 | 2013-12-27 | パイオニア株式会社 | Connection structure of conductor, electronic equipment |
| JP2017034192A (en) * | 2015-08-05 | 2017-02-09 | 株式会社東芝 | Semiconductor device and method of manufacturing the same |
| JP2018078152A (en) * | 2016-11-07 | 2018-05-17 | Koa株式会社 | Chip resistor |
-
1993
- 1993-05-25 JP JP5147050A patent/JPH06333977A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010171421A (en) * | 2008-12-26 | 2010-08-05 | National Institute Of Advanced Industrial Science & Technology | Semiconductor device and manufacturing method thereof |
| WO2013190638A1 (en) * | 2012-06-19 | 2013-12-27 | パイオニア株式会社 | Connection structure of conductor, electronic equipment |
| JP2017034192A (en) * | 2015-08-05 | 2017-02-09 | 株式会社東芝 | Semiconductor device and method of manufacturing the same |
| JP2018078152A (en) * | 2016-11-07 | 2018-05-17 | Koa株式会社 | Chip resistor |
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