JP2674567B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2674567B2 JP2674567B2 JP13368295A JP13368295A JP2674567B2 JP 2674567 B2 JP2674567 B2 JP 2674567B2 JP 13368295 A JP13368295 A JP 13368295A JP 13368295 A JP13368295 A JP 13368295A JP 2674567 B2 JP2674567 B2 JP 2674567B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- insulating film
- film
- semiconductor device
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Wire Bonding (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
にバンプ電極を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having bump electrodes.
【0002】[0002]
【従来の技術】半導体集積回路の実装技術の1つである
TAB(tape automated bondin
g)では、半導体シリコン基板上に形成された電極パッ
ド上のバンプとフィルムキャリアテープのインナリード
とを熱圧着し接合している。2. Description of the Related Art A TAB (tape automated bond), which is one of the mounting techniques for semiconductor integrated circuits.
In g), the bumps on the electrode pads formed on the semiconductor silicon substrate and the inner leads of the film carrier tape are bonded by thermocompression bonding.
【0003】図3(a),(b)は従来の半導体装置の
一例を示す平面図およびB−B′線断面図である。3A and 3B are a plan view and a cross-sectional view taken along the line BB 'showing an example of a conventional semiconductor device.
【0004】図3(a),(b)に示すように、シリコ
ン基板1の上に設けたBPSG膜等のフィールド絶縁膜
2の上にアルミニウム膜からなる電極パッド3を形成
し、電極パッド3を含む表面に耐湿性の低いフィールド
絶縁膜2を保護するプラズマ窒化膜(プラズマCVD法
により形成した窒化シリコン膜)からなるカバー絶縁膜
5を形成する。次に、電極パッド3の上のカバー絶縁膜
5を選択的にエッチングしてバンプ形成用の開口部7を
形成し、開口部7に露出した電極パッド3の表面および
開口部7の周囲にバリアメタル膜8を介してバンプ9を
形成する。As shown in FIGS. 3A and 3B, an electrode pad 3 made of an aluminum film is formed on a field insulating film 2 such as a BPSG film provided on a silicon substrate 1, and the electrode pad 3 is formed. A cover insulating film 5 made of a plasma nitride film (a silicon nitride film formed by a plasma CVD method) that protects the field insulating film 2 having low moisture resistance is formed on the surface including. Next, the cover insulating film 5 on the electrode pad 3 is selectively etched to form an opening 7 for forming a bump, and a barrier is formed on the surface of the electrode pad 3 exposed in the opening 7 and around the opening 7. Bumps 9 are formed via the metal film 8.
【0005】[0005]
【発明が解決しようとする課題】この従来の半導体装置
では、図4に示すように、バンプ9にフィルムキャリア
のインナリード10を熱圧着して接合する際に、バンプ
9から電極パッド3に上部からの機械的応力が加わり、
電極パッド3が横方向に変形して機械的強度の弱い電極
パッド3の側面に突出してカバー絶縁膜5を破壊し、ク
ラック11や剥れを発生させ、この破壊されたカバー絶
縁膜5より外部の水分が入り込み電極パッド3の腐食を
生じ、導電性劣化や断線等を発生させるという問題点が
あった。In this conventional semiconductor device, as shown in FIG. 4, when the inner leads 10 of the film carrier are bonded to the bumps 9 by thermocompression bonding, the bumps 9 and the electrode pads 3 are placed on top of each other. Mechanical stress from
The electrode pad 3 is deformed in the lateral direction and protrudes to the side surface of the electrode pad 3 having a weak mechanical strength to break the cover insulating film 5, causing cracks 11 and peeling, and the outside of the broken cover insulating film 5. However, there is a problem in that the water enters into the electrode pad 3 to cause corrosion, resulting in deterioration of conductivity and disconnection.
【0006】このような問題を防ぐ方法として特開平1
−209746号公報に記載されているように、アルミ
ニウム多層配線を用いて電極パッドへ加わる応力を分散
させるという技術があるが、構造、工程が複雑になると
いう欠点がある。[0006] As a method for preventing such a problem, Japanese Patent Laid-Open No. Hei 1
As described in JP-A-209746, there is a technique of dispersing stress applied to an electrode pad by using aluminum multi-layer wiring, but there is a drawback that a structure and a process are complicated.
【0007】本発明の目的は、簡単な構造で、且つ工程
を増やすことなく耐湿性の低下を防止できる半導体装置
を提供することにある。An object of the present invention is to provide a semiconductor device having a simple structure and capable of preventing the deterioration of moisture resistance without increasing the number of steps.
【0008】[0008]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に形成した絶縁膜上に設けた電極パッド
と、前記電極パッドのバンプ形成領域の周囲に形成した
溝と、前記溝を含む表面に形成して前記電極パッド上の
バンプ形成領域に設けた開口部および前記溝内に設けた
空洞を有する絶縁膜と、バリアメタル膜を介して前記開
口部の前記電極パッドと電気的に接続し且つ前記開口部
周囲の前記空洞上を含む領域の前記絶縁膜上に延在して
形成したバンプとを有する。According to the present invention, there is provided a semiconductor device comprising:
An electrode pad provided on an insulating film formed on a semiconductor substrate, a groove formed around a bump forming region of the electrode pad, and a surface formed including the groove provided on a bump forming region on the electrode pad An insulating film having an opening and a cavity provided in the groove, and a region of the region around the opening including on the cavity electrically connected to the electrode pad of the opening via a barrier metal film. And a bump formed to extend over the insulating film.
【0009】[0009]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【0010】図1(a),(b)は本発明の一実施例を
示す平面図およびA−A′線断面図である。FIGS. 1A and 1B are a plan view and a sectional view taken along the line AA 'showing an embodiment of the present invention.
【0011】図1(a),(b)に示すように、シリコ
ン基板1の上に形成したBPSG膜からなるフィールド
絶縁膜2の上にアルミニウム膜等からなりバンプ形成領
域の周囲に溝4を有する電極パッド3を形成する。次
に、電極パッド3を含む表面にプラズマCVD法により
形成した窒化シリコン膜(プラズマ窒化膜)等の耐湿性
にすぐれたカバー絶縁膜5を設けてパターニングし、電
極パッド3のバンプ形成領域に開口部7を形成すると共
に溝4内に幅2μm程度の空洞6を形成する。次に、開
口部7に露出した電極パッド3の表面を含むカバー絶縁
膜5の表面にチタン膜等のバリアメタル膜8をスパッタ
法で200nmの厚さに形成した後、レジスト膜を用い
て選択的に金膜をめっきし、形成された金膜をマスクと
してバリアメタル膜8を除去し、開口部7の電極パッド
3とバリアメタル膜8を介して電気的に接続し、且つ開
口部7の周囲に形成した空洞6上の領域を含むカバー絶
縁膜5の上に延在するバンプ9を形成する。As shown in FIGS. 1 (a) and 1 (b), a groove 4 made of an aluminum film or the like is formed on a field insulating film 2 made of a BPSG film formed on a silicon substrate 1 around a bump forming region. The electrode pad 3 having is formed. Next, a cover insulating film 5 having excellent moisture resistance such as a silicon nitride film (plasma nitride film) formed by a plasma CVD method is provided on the surface including the electrode pad 3 and patterned, and an opening is formed in a bump forming region of the electrode pad 3. The part 7 is formed and the cavity 6 having a width of about 2 μm is formed in the groove 4. Next, a barrier metal film 8 such as a titanium film is formed to a thickness of 200 nm on the surface of the cover insulating film 5 including the surface of the electrode pad 3 exposed in the opening 7 by a sputtering method, and then selected using a resist film. The gold film is selectively plated, the barrier metal film 8 is removed using the formed gold film as a mask, the electrode pad 3 of the opening 7 is electrically connected through the barrier metal film 8, and the opening 7 Bumps 9 are formed to extend on the insulating cover film 5 including the region above the cavity 6 formed around the bumps 9.
【0012】図2は本発明を用いた半導体装置の実装状
態を説明するための断面図である。FIG. 2 is a sectional view for explaining a mounted state of a semiconductor device using the present invention.
【0013】図2に示すように、バンプ9にテープキャ
リアのインナリード10をボンディングする際にバンプ
9から電極パッド3に印加される応力により電極パッド
3が変形して電極パッド3の端部が突出し空洞6内のカ
バー絶縁膜5にクラック11を生ずることがあるが、バ
ンプ9の外周とカバー絶縁膜5とはバリアメタル膜8を
介して密封されており、空洞7内に生じたカバー絶縁膜
5のクラック11に外部から水分が侵入するのを防ぐこ
とができる。As shown in FIG. 2, when the inner leads 10 of the tape carrier are bonded to the bumps 9, the stress applied to the electrode pads 3 from the bumps 9 deforms the electrode pads 3 so that the end portions of the electrode pads 3 are Although a crack 11 may be generated in the cover insulating film 5 in the protruding cavity 6, the outer periphery of the bump 9 and the cover insulating film 5 are sealed by the barrier metal film 8, and the cover insulating film generated in the cavity 7 is insulated. It is possible to prevent moisture from entering the crack 11 of the film 5 from the outside.
【0014】なお、開口部7と、バンプ9の外周との間
に空洞6を2重に設けても良く、電極パッド3の横方向
への変形によるカバー絶縁膜のクラックで生ずる水分の
侵入を防ぐ効果を更に高めることができる。The cavity 6 may be doubly provided between the opening 7 and the outer periphery of the bump 9 so as to prevent moisture from entering due to cracks in the cover insulating film due to lateral deformation of the electrode pad 3. The preventive effect can be further enhanced.
【0015】なお、パッド電極3としては、アルミニウ
ム膜の他にアルミニウム−シリコン(1%)合金膜やチ
タン−銅−アルミニウム合金膜等の微細加工には適して
いるが機械的応力に弱い材料を使用することもできる。As the pad electrode 3, in addition to the aluminum film, a material suitable for fine processing such as an aluminum-silicon (1%) alloy film or a titanium-copper-aluminum alloy film but weak against mechanical stress is used. It can also be used.
【0016】[0016]
【発明の効果】以上説明したように本発明は、TAB工
程の熱圧着の際にバンプからパッド電極へ印加される機
械的応力でパッド電極の側面が突出して生じるカバー絶
縁膜のクラックをパッド電極のバンプ形成用開孔部の周
辺に形成した空洞内で発生させることで、バンプの外周
とカバー絶縁膜との密封を維持して周囲からの水分の侵
入を防ぐことができ、これにより、バンプ電極の腐触、
断線及びフィールド絶縁膜への水分の侵入によるリーク
電流の発生を防ぐことができるという効果を有する。As described above, according to the present invention, the cracks in the cover insulating film caused by the side surface of the pad electrode protruding due to the mechanical stress applied from the bump to the pad electrode during the thermo-compression bonding in the TAB process are generated. By generating it in the cavity formed around the bump forming opening of the above, it is possible to maintain the sealing between the outer periphery of the bump and the cover insulating film and prevent the intrusion of moisture from the surroundings. Electrode corrosion,
There is an effect that it is possible to prevent the occurrence of leakage current due to disconnection and entry of moisture into the field insulating film.
【図1】本発明の一実施例を示す平面図およびA−A′
線断面図。FIG. 1 is a plan view showing an embodiment of the present invention and AA ′.
Line sectional view.
【図2】本発明を用いた半導体装置の実装状態を説明す
るための断面図。FIG. 2 is a cross-sectional view for explaining a mounted state of a semiconductor device using the present invention.
【図3】従来の半導体装置の一例を示す平面図およびB
−B′線断面図。FIG. 3 is a plan view showing an example of a conventional semiconductor device and FIG.
-B 'line sectional view.
【図4】従来の半導体装置の問題点を説明するための断
面図。FIG. 4 is a cross-sectional view illustrating a problem of a conventional semiconductor device.
1 シリコン基板 2 フィールド絶縁膜 3 電極パッド 4 溝 5 カバー絶縁膜 6 空洞 7 開口部 8 バリアメタル膜 9 バンプ 10 インナリード 11 クラック 1 Silicon substrate 2 Field insulating film 3 Electrode pad 4 Groove 5 Cover insulating film 6 Cavity 7 Opening 8 Barrier metal film 9 Bump 10 Inner lead 11 Crack
Claims (2)
た電極パッドと、前記電極パッドのバンプ形成領域の周
囲に形成した溝と、前記溝を含む表面に形成して前記電
極パッド上のバンプ形成領域に設けた開口部および前記
溝内に設けた空洞を有する絶縁膜と、バリアメタル膜を
介して前記開口部の前記電極パッドと電気的に接続し且
つ前記開口部周囲の前記空洞上を含む領域の前記絶縁膜
上に延在して形成したバンプとを有することを特徴とす
る半導体装置。1. An electrode pad provided on an insulating film formed on a semiconductor substrate, a groove formed around a bump formation region of the electrode pad, and a surface including the groove formed on the electrode pad. An insulating film having an opening provided in a bump formation region and a cavity provided in the groove, and electrically connected to the electrode pad of the opening via a barrier metal film and on the cavity around the opening. And a bump formed to extend over the insulating film in a region including the semiconductor device.
ム−シリコン合金,チタン−銅−アルミニウム合金のい
ずれか1種からなる請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the electrode pad is made of any one of aluminum, aluminum-silicon alloy, and titanium-copper-aluminum alloy.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13368295A JP2674567B2 (en) | 1995-05-31 | 1995-05-31 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13368295A JP2674567B2 (en) | 1995-05-31 | 1995-05-31 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08330310A JPH08330310A (en) | 1996-12-13 |
JP2674567B2 true JP2674567B2 (en) | 1997-11-12 |
Family
ID=15110419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13368295A Expired - Lifetime JP2674567B2 (en) | 1995-05-31 | 1995-05-31 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2674567B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7141885B2 (en) | 2002-02-13 | 2006-11-28 | Samsung Electronics Co., Ltd. | Wafer level package with air pads and manufacturing method thereof |
JP5017872B2 (en) * | 2006-02-06 | 2012-09-05 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
JP5212297B2 (en) * | 2008-11-07 | 2013-06-19 | 株式会社デンソー | Semiconductor device |
JP5820437B2 (en) * | 2008-12-03 | 2015-11-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP5331610B2 (en) * | 2008-12-03 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
JP5284125B2 (en) * | 2009-01-23 | 2013-09-11 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
-
1995
- 1995-05-31 JP JP13368295A patent/JP2674567B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH08330310A (en) | 1996-12-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970617 |