JPS5840835A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5840835A JPS5840835A JP56138925A JP13892581A JPS5840835A JP S5840835 A JPS5840835 A JP S5840835A JP 56138925 A JP56138925 A JP 56138925A JP 13892581 A JP13892581 A JP 13892581A JP S5840835 A JPS5840835 A JP S5840835A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- substrate
- electrodes
- extraction electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本完明は半導体装置にかかり、とくにモールド樹脂封止
さｒＬ２半導体装置の耐湿性を向上させる構造に関する
ものでおる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly relates to a structure for improving the moisture resistance of an rL2 semiconductor device sealed with a molded resin.
一般にモールド樹脂封入さｆ′した半導体用パッケージ
は、その量産性の良さおよびその低価格のため広く使用
さｎている。しかし、他のパッケージ例えばハーメチッ
クシールさしたセラミックパッケージに比べ、周囲から
の水分や湿気がモールド樹脂中を浸透しやすい。そのた
め浸透してきた水分が狭面安定用及び＠面形状を緩くす
る絶縁膜として使用さｎている不純物含有ガラス、特に
リン珪化ガラス（以下Ｐ Ｓ Ｇｇと称する〕と反応し
てリン酸となる。このリン酸が配線用金属で多るアルミ
ニウムを溶解してしまい、ついには不良に至る欠点を有
し、モールド樹脂封入さ扛た半導体用パッケージの耐湿
性を低下させていた。In general, semiconductor packages encapsulated in molded resin are widely used because of their ease of mass production and low cost. However, compared to other packages such as hermetically sealed ceramic packages, moisture from the surroundings easily penetrates into the mold resin. Therefore, the permeated moisture reacts with impurity-containing glass, particularly phosphorus silicide glass (hereinafter referred to as P S Gg), which is used as an insulating film for stabilizing the narrow surface and loosening the shape of the surface, to form phosphoric acid. This phosphoric acid dissolves aluminum, which is a large amount of wiring metal, which ultimately leads to defects and reduces the moisture resistance of semiconductor packages encapsulated in molded resin.
この不良に対して半導体装置の表面を緻輩なパッシベー
ション膜（以後、カバー膜と称する）で被うことにより
外部から浸透してきた水分とＰｉＧ膜を反応させないよ
うな対策が施されてきた。A countermeasure against this defect has been taken by covering the surface of the semiconductor device with a dense passivation film (hereinafter referred to as a cover film) to prevent the PiG film from reacting with moisture penetrating from the outside.
該対策によりカバー膜で被わｎた部分の耐湿性は向上し
た。しかし、カバー膜で被うことの出来ない部分特に外
部引き出し電極部についてはアルミニウムが露出して騒
るためモールド樹脂中を浸透してきた水分等が原因で溶
解してしまう問題が依然として残っている。こ′ｔ′Ｌ
、を第１図および第２図を用いて説明する。第１図は従
来構造に於けるポンディングパッド部の断面図であり、
■はＰ型半導体基板、２は二酸化シリコン膜、３はＰＳ
Ｇ膜、４は外部引き出し電極、５はカバー膜で必る。こ
ノ状ｍｒｔｓメタライゼーション後カバー膜５を形成し
た段階の断面図である。次に第２図に示すように写真蝕
刻法により外部引出し電極４上のカバー膜５にケースの
内部リードと電気的接続を行うためのスルーホールを開
孔する。この時、カバー族のエッチャントにより、外部
引出し電極４のアルミニウムもエツチングさｎ、膜厚が
薄くなると同時に、エツチングがアルミニウムのグレイ
ンに沿って進み外部引き出し電極４の下のＰＳＧ膜３に
まで達するピンホール６が開いてし′まう。外部引き出
し電極４上にピンホール６が開いた状態で。This measure improved the moisture resistance of the area covered with the cover film. However, there still remains the problem that the parts that cannot be covered with the cover film, especially the external lead-out electrode parts, can be dissolved due to moisture that has penetrated into the mold resin because the aluminum is exposed and noisy. This't'L
, will be explained using FIGS. 1 and 2. Figure 1 is a sectional view of the bonding pad part in the conventional structure.
■: P-type semiconductor substrate, 2: silicon dioxide film, 3: PS
G film, 4 is an external extraction electrode, and 5 is a cover film. FIG. 3 is a cross-sectional view of a stage where a cover film 5 is formed after metallization of the MRTS. Next, as shown in FIG. 2, a through hole for electrical connection to the internal lead of the case is made in the cover film 5 on the external lead electrode 4 by photolithography. At this time, the aluminum of the external extraction electrode 4 is also etched by the cover group etchant, and the film thickness becomes thinner. At the same time, the etching progresses along the grains of the aluminum and reaches the PSG film 3 below the external extraction electrode 4. Hole 6 opens. With a pinhole 6 opened on the external extraction electrode 4.
モールド樹脂封入技術により組み立てらｎた半導体装置
は、周囲に存在する水分等がモールド樹脂中を浸透しシ
リコン半導体板面に達し、外部引き出し′電極４に開い
たスルーホール６を通り、Ｐ８Ｇ膜３と反応してしまい
、リン酸となり、外部引き出し電極４のアルミニラムラ
溶解してし１い。In a semiconductor device assembled using mold resin encapsulation technology, moisture present in the surroundings permeates through the mold resin, reaches the surface of the silicon semiconductor board, passes through the through hole 6 opened in the external extraction electrode 4, and is exposed to the P8G film 3. This reacts with the aluminum to form phosphoric acid, which dissolves the aluminum irregularities of the external lead electrode 4.
ついには半導体装置を不良に到らしめてしまう耐湿性上
の欠陥を有していた。It had a moisture resistance defect that ultimately led to the failure of the semiconductor device.
本元明は、上記不都合を改善（〜、しいてはモールド樹
脂封入さ−ｊした半導体装置の耐湿性を向上させる構造
を提供するものである。The present invention provides a structure that improves the above-mentioned disadvantages (and improves the moisture resistance of a semiconductor device encapsulated in a molded resin).
本兇明は半導体基板上に形成さｎた二酸化シリコン膜と
、該二酸化シリコン膜上に形成さ−ｎたリンカラスＪ−
と、該リンガラス層上に形成さした第１の外部引出し電
極と、該第１の外筒≦引き出し電極上ＶＣ形取さγした
絶縁層と、該絶縁層に開孔さｒした少くとも２個以上の
開孔部と該絶縁層上に形成さγした第２の外部引出し電
極とを有し、前記第１の外部引出し電極と第２の外部引
出し電極とが前記絶縁）−に設けらｎた開孔部を通して
、互いに電気的接続がなさγしていることを特徴とする
半導体装置にある。This paper describes a silicon dioxide film formed on a semiconductor substrate and a link glass formed on the silicon dioxide film.
, a first external extraction electrode formed on the phosphor glass layer, an insulating layer having a VC shape on the first outer cylinder ≦ the extraction electrode, and at least a hole r formed in the insulating layer. It has two or more openings and a second external extraction electrode formed on the insulating layer, and the first external extraction electrode and the second external extraction electrode are provided in the insulation layer. A semiconductor device is characterized in that there is no electrical connection to each other through the openings.
以下本発明の詳細な説明する第３図乃至第６図は本発明
一実施例の工程説明図でめり１次にこｎ等の図を参照し
つつ説明する。The present invention will be explained in detail below with reference to FIGS. 3 to 6, which are process explanatory diagrams of one embodiment of the present invention.
第３図は通常の技法を通用し、Ｐ型シリコン牛導体基板
ｌ上にフィールドの二酸化シリコン膜２゜絶縁及び段部
のだらしのためのＰＳＧ膜３第３第１部引出し電、１ｉ
ｉ４Ａゲート酸化腺７、シリロンゲート８．ソース顎域
或いはドレイン領域であるへ型不純物導入領域９、ソー
ス領域或いはドレイン領域からの引き出し電極１０およ
びカバー膜５が形成さｔ”した状態を弐わしでいる。Fig. 3 shows a PSG film 3 for insulating the field and sloping the step part, a third part 1 lead-out current, 1i, using the usual technique.
i4A gate oxidative gland 7, Sirilong gate 8. The state in which the hemi-type impurity introduction region 9, which is the source jaw region or the drain region, the lead-out electrode 10 from the source region or the drain region, and the cover film 5 have been formed is shown.
次に第４回向に示すように、写真蝕刻法により第１の外
部引き出し１！極４Ａ上のカバー族６に少なくとも２個
以上のコンタクト穴１１ｔ−形成する。Next, as shown in the fourth direction, the first external drawer 1! At least two or more contact holes 11t are formed in the cover group 6 on the pole 4A.
第４図（均は第４図（６）の平向図でめり、第４図（均
では該コンタクト穴１１が１２個形成さしている。In FIG. 4 (the figure is shown in the plan view of FIG. 4 (6)), 12 contact holes 11 are formed in the figure.
咳コンタクト穴１１を開孔する時に第１の外部引き出し
＊ｇ４のアルミニウムがカバー膜５のエラ５−
チャントによりエツチングさｎ該第１の外部引き出し′
に極４の下の１’ＳＧ膜３にまで達するピンホール６が
形成さしてしｌう。次に第５図に示す如く、例えば、ス
パッタ蒸着法などにより、およそ１μｍ程度のアルミニ
ウム１２Ａを全面に形成する。その後写真蝕刻法により
第２の外部引出し電極１２を形成する。この状態を第６
図に示す。この状態では、もはや第２の外部引き出し電
極１２のアルミニウムにはＰＩＳＯ膜３に達するピンホ
ール６は開いていない。そのため、本発明による構造を
有する半導体装置をモールド樹脂封入技術を用いて組み
立てた製品は、たとえ外部より水分が浸透してきても水
分はＭ２の外部引き出し電極においてＰＳＧ膜と反応出
来ないので、第２の外部引出し電極のアルミニウムは溶
解さｎず、耐湿性のすぐｎた半導体装置を得ることが出
来る。When drilling the cough contact hole 11, the aluminum of the first external drawer*g4 is etched by the gills of the cover membrane 5.
A pinhole 6 is formed that reaches the 1'SG film 3 below the pole 4. Next, as shown in FIG. 5, aluminum 12A having a thickness of approximately 1 μm is formed over the entire surface by, for example, sputter deposition. Thereafter, the second external lead electrode 12 is formed by photolithography. This state is the sixth
As shown in the figure. In this state, the pinhole 6 that reaches the PISO film 3 is no longer formed in the aluminum of the second external extraction electrode 12. Therefore, in a product in which a semiconductor device having a structure according to the present invention is assembled using mold resin encapsulation technology, even if moisture penetrates from the outside, the moisture cannot react with the PSG film at the external extraction electrode of M2, so the second The aluminum of the external lead electrode is not melted, and a semiconductor device with excellent moisture resistance can be obtained.
第１図及びＭ２図は従来技術の半導体装置を示す断面図
であり、第３図乃至第６図は本発明の実６−
流側を工程順に示す断面図および平面図である。
図に於いて％ ｌ・・・・・・Ｐ型半導体基板、２・・
・・・・二酸化シリコン膜、３・・・・・・ＰＥＧ膜、
４・・・・・・第１の外部引き出し電極、４Ａ・・・・
・・外部引き出し電極。
５・・・・・・カバー膜、６・・・・・・ピンホール、
７・・・・・・フート酸化膜、８・・・・・・シリコン
ゲート、９・・・・・・ソース領域或いはドレイン領域
であるＮ型不純物導入領域、１０・・・・・・ソース領
域或いはドレイン領域からの引き出し゛電極、１１・・
・・・・第１の外部引き出し電極と第２の外部引き出し
電極を電気的に接続するコンタクト孔、１２・・・・・
・第２の外部引き出し電極である。
７−
第 １ 区
第Ｚ図1 and M2 are cross-sectional views showing a conventional semiconductor device, and FIGS. 3 to 6 are cross-sectional views and plan views showing the practical side of the present invention in the order of steps. In the figure, %l...P-type semiconductor substrate, 2...
...Silicon dioxide film, 3...PEG film,
4...First external extraction electrode, 4A...
・External extraction electrode. 5... Cover film, 6... Pinhole,
7...Foot oxide film, 8...Silicon gate, 9...N-type impurity doped region serving as a source region or drain region, 10...Source region Or an extraction electrode from the drain region, 11...
. . . Contact hole 12 for electrically connecting the first external extraction electrode and the second external extraction electrode.
- It is the second external extraction electrode. 7- Ward 1, Map Z
Claims (1)
の絶縁層上に形成されたリンガラス層と、該リンガラス
層上に形成さ′ｎ友＊ｔの外部引出し電極と、該第１の
外部引き出し電極上に形成さ′ｎ九第２の絶縁層と、該
＃！２の絶縁層に開孔さｒｔｙｃ少くとも２個以上の開
孔部と、該第２の絶域層上に形成さｒＬｆｃ第２の外部
引出し電極とを有し、前記ｗ＆ｌの外部引出し′ｆＩｔ
極と第２の外部引出し電極とが前記第２の絶縁層に設け
らｒした開孔部を通して互いに電気的接続がなさｎてい
ることを特徴とする半導体装置。an insulating layer of Ml formed on a semiconductor substrate;
a phosphor glass layer formed on the insulating layer, an external extraction electrode formed on the phosphorus glass layer, and a second insulating electrode formed on the first external extraction electrode. Layer and #! a second external lead electrode formed on the second insulation layer;
A semiconductor device characterized in that a pole and a second external extraction electrode are electrically connected to each other through an opening provided in the second insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138925A JPS5840835A (en) | 1981-09-03 | 1981-09-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138925A JPS5840835A (en) | 1981-09-03 | 1981-09-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5840835A true JPS5840835A (en) | 1983-03-09 |
| JPS6236386B2 JPS6236386B2 (en) | 1987-08-06 |
Family
ID=15233333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56138925A Granted JPS5840835A (en) | 1981-09-03 | 1981-09-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840835A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54128280A (en) * | 1978-03-29 | 1979-10-04 | Hitachi Ltd | Resin-sealed semiconductor device |
| JPS5619639A (en) * | 1979-07-27 | 1981-02-24 | Hitachi Ltd | Semiconductor device |
-
1981
- 1981-09-03 JP JP56138925A patent/JPS5840835A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54128280A (en) * | 1978-03-29 | 1979-10-04 | Hitachi Ltd | Resin-sealed semiconductor device |
| JPS5619639A (en) * | 1979-07-27 | 1981-02-24 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6236386B2 (en) | 1987-08-06 |
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