JPH012335A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH012335A JPH012335A JP62-158062A JP15806287A JPH012335A JP H012335 A JPH012335 A JP H012335A JP 15806287 A JP15806287 A JP 15806287A JP H012335 A JPH012335 A JP H012335A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- forming
- region
- semiconductor device
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000005530 etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 239000011734 sodium Substances 0.000 claims description 2
- 229910052708 sodium Inorganic materials 0.000 claims description 2
- -1 sodium Chemical class 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 14
- 239000011521 glass Substances 0.000 description 14
- 239000011574 phosphorus Substances 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052776 Thorium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、時にアルミニウ
ム電極の段切れを防止する構造を有する半導体装置の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a structure that prevents breakage of aluminum electrodes.
バイポーラトランジスタ、接合型電界効果トランジスタ
（Ｊ−ＰＥＴ）を用いた個別のトフンジスタ素子におい
ても、従来外付けされていた抵抗を７リコンチ、グ内に
内域した構造のものが増えてきている。Even in individual transistor elements using bipolar transistors and junction field effect transistors (J-PET), structures in which the conventional external resistor is within 7 Ω are increasing.
従来この種の半導体装置は、第３図のようなＮ−チャネ
ルＪ−ＦＥＴを構成する一部分であるＮ＋型ソース拡散
領域３と多結晶／リコン抵抗（ポリシリコン抵抗）６と
を、アルミニウム電極７′で接続していた。Conventionally, in this type of semiconductor device, an N+ type source diffusion region 3 and a polycrystalline/licon resistor (polysilicon resistor) 6, which are part of an N-channel J-FET as shown in FIG. 3, are connected to an aluminum electrode 7. ’ was connected.
〔発明が解決しようとする問題点」
上述した従来の半導体装置は、Ｎ十型ノース憤域３から
電気的接続を行なうため、Ｎ生型領域３上に形成された
酸化膜４１及び４２と、これらの酸化膜４１及び４２に
よシ上下からはさまれた形で形成されているリンガラス
層５とは、フォトリングフッイー技術を用いて、Ｎ生型
ソース領域３に達するまでフッ酸（Ｉ［Ｆ ）系溶液に
てエツチングされる。[Problems to be Solved by the Invention] The conventional semiconductor device described above has oxide films 41 and 42 formed on the N-type region 3 in order to make electrical connection from the N-type north region 3; The phosphorus glass layer 5, which is formed between the oxide films 41 and 42 from above and below, is coated with hydrofluoric acid( Etched with an I[F ) solution.
しかし、酸化膜４１及び４２とリンガラス層５のフッ酸
系６容級に対するエツチング速度は、リンガラス５の力
が酸化膜４１及び４２より速いため、浪化模がＡｏ−バ
ーハング状態となる逆テーパ一部８が形成されてしまい
、Ａｌ竜他７を形成した際、Ａ７段切れ都９ができてし
まい、電気的にオープン不良が発生しｆする伏態となっ
℃おり、歩留上・１ｇ・−直上に悪路４ｊをおよぼす状
態となっ℃いた。However, the etching rate of the oxide films 41 and 42 and the phosphorus glass layer 5 with respect to the 6-volume hydrofluoric acid system is such that the force of the phosphorus glass 5 is faster than that of the oxide films 41 and 42. The taper part 8 is formed, and when the Al dragon and other parts 7 are formed, the A7 step cut end 9 is formed, and an electrical open failure occurs, resulting in a hidden state, which reduces the yield. The situation was such that a rough road 4j was directly above the vehicle.
なお、リンカフス層５；↓−ｒトリウム等の荷動イ；ｒ
ンを淑り込んでしまい、電界による特性変動を防止する
鋤ざがあり、通常、半導体装置には設けられている。ｌ
たリンガラス層５上に設けられるぼ化膜４は、高抵抗ポ
リ７リコン６がリンガラス層５からリンが拡散し、ポリ
シリコンの抵抗値がはくなってしまうことを防止するた
めに設けられる。In addition, the link cuff layer 5;↓−rThe charge movement of thorium, etc.
Semiconductor devices are usually equipped with a comb that prevents the characteristics from changing due to electric fields. l
The phosphor film 4 provided on the phosphor glass layer 5 is provided to prevent the high resistance polysilicon 6 from diffusing phosphorus from the phosphor glass layer 5 and lowering the resistance value of the polysilicon. It will be done.
本発明の半導体装置の裂造刀法は半導体基板の一主面に
第１の絶縁層を形成する工程と、この第１の絶ｄ★層上
にナトリクム等の不純物イオンを捕獲しやすい性質を有
し第１の杷＠層よりエツチング速度の大きい第２の絶縁
層を形成する工程と、この第２の絶、線層の所定領域を
〃３択的に除去し第１の開口部を形成する工程と、この
第１の開口部及び第２の絶縁層を８にりて第２の絶縁層
よシエッチング速度の小さい第３の絶縁層を形成する工
程と、第１の開口部内の所定領域の′ｆＪ３の絶縁層及
び第１の絶縁層を通釈的に除去することにより半導体基
板の一主面に達する第２の開口部を設ける工程とを有し
ている。The manufacturing method for semiconductor devices of the present invention includes the step of forming a first insulating layer on one main surface of a semiconductor substrate, and the process of forming a first insulating layer on this first insulating layer, which has a property of easily capturing impurity ions such as sodium. forming a second insulating layer having a higher etching rate than the first insulating layer; and selectively removing a predetermined region of the second insulating layer to form a first opening. a step of forming a third insulating layer having a lower etching rate than the second insulating layer by etching the first opening and the second insulating layer; and a step of forming a second opening reaching one main surface of the semiconductor substrate by removing the insulating layer and the first insulating layer in the region 'fJ3 in a circular manner.
〔実施例」 次に本発明について図面を参照して説明する。〔Example" Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例により形成されるＪ−ＦＥＴ
のソース領域近傍の縦即ｒ面図である。Ｐ型領域１はゲ
ート領域となり、Ｎ型領域２はチャネル領域、ソース領
域３およびドレイン領域を形成する領域、である。ｎ型
領域２上に酸化膜４１を形成し、その上に電気的特性の
安定化を図るためのリンガラス層５を形成する。次に将
来ｎ十型領域３にアルミニウム電極７を接続するために
開孔され、電気的コンタクト部１０となる領域上のリン
ガラス層５をフッ酸系浴液によりこの電気的コンタクト
部１０よりも広く選択的に除去する。FIG. 1 shows a J-FET formed according to one embodiment of the present invention.
FIG. P type region 1 becomes a gate region, and N type region 2 is a region forming a channel region, source region 3, and drain region. An oxide film 41 is formed on the n-type region 2, and a phosphorus glass layer 5 is formed thereon to stabilize the electrical characteristics. Next, the phosphor glass layer 5 on the area which will be formed into the electrical contact part 10 by forming a hole in order to connect the aluminum electrode 7 to the n-type region 3 in the future is further removed from the electrical contact part 10 by using a hydrofluoric acid bath solution. Widely and selectively removed.
この時、酸化膜４１もエツチングされ、その表面の一部
が除去される。この酸化膜４１の厚さが薄い場合は、ｎ
十型領域３が露出する。次にリンガラス層５．酸化膜４
１．および露出している場合はｎ十型饋域３上に酸化膜
４２を形成し、さらにフッ酸系溶成により、前の工程で
リンガラス層５が選択的に除去された領域内の酸化膜４
２及び４１を選択的に除去することによりｎ十型領域３
に達するｐ電気的コンタクト部１０を開孔する。このよ
うに酸化膜４２．４１からなる均質な部分のみエツチン
グすることとなり逆テーパーとはならず、アルミニウム
電極７を形成してもアルミニウム電極７の段切れとはな
らず、歩留−信頼性とも良好な半導体装置が得られる。At this time, the oxide film 41 is also etched and a portion of its surface is removed. When the thickness of this oxide film 41 is thin, n
Ten-shaped area 3 is exposed. Next, the phosphorus glass layer 5. Oxide film 4
1. If exposed, an oxide film 42 is formed on the n-type region 3, and the oxide film in the region where the phosphorus glass layer 5 was selectively removed in the previous step is further formed by hydrofluoric acid annealing. 4
By selectively removing 2 and 41, the n-type region 3
A p-electrical contact portion 10 is drilled to reach the p-type. In this way, only the homogeneous portion consisting of the oxide film 42, 41 is etched, so that a reverse taper is not formed, and even when the aluminum electrode 7 is formed, there is no break in the aluminum electrode 7, which improves yield and reliability. A good semiconductor device can be obtained.
なお、電気的コンタクト部ｌＯを一辺２μｍの矩形状と
し、Ｎ十型領域３が一辺６μｍの矩形状とした場合に、
リンガラス層５は荷動イオンの影響を受けやすいＮ型領
域２上はおおい、Ｎ十型領域３上の一部もおおうように
一辺５μｍ＆度の矩形状Ｋｔ気的コンタクト部１０形成
に先立って開孔しておく。Note that when the electrical contact portion 10 is made into a rectangular shape with a side of 2 μm and the N-type region 3 is made into a rectangular shape with a side of 6 μm,
A phosphorus glass layer 5 is formed prior to the formation of a rectangular Kt gas contact portion 10 of 5 μm on each side so as to cover the N-type region 2 which is susceptible to the influence of charged ions and also cover a part of the N-type region 3. Leave the hole open.
第２図は本発明の他の実施例の縦萌面図であり、抵抗内
蔵ｎｐｎ ）ランジスタのベース領域近傍を示している
。Ｎ型領域２はコレクタ領域とな）Ｐ型領域１１はベー
ス領域となる。酸化膜４２におおわれたリンガラス層５
は、前述した一実施例の場合と同様にしてＰ型狽域１１
上の電気的コンタクト部１０の外部のみに選択的に形成
することによりこの電気的コンタクト部１０は逆テーパ
ーとはならずアルミニウム電極７には段切れが起こらな
い。ポリ７リコン６は抵抗となり、チッ化膜１２はさら
に水分等の侵入を防ぎ素子の信頼性を高めるだめに設け
ている。FIG. 2 is a vertical plan view of another embodiment of the present invention, showing the vicinity of the base region of an NPN transistor with a built-in resistor. N-type region 2 becomes a collector region) P-type region 11 becomes a base region. Phosphorous glass layer 5 covered with oxide film 42
In the same manner as in the above-mentioned embodiment, the P-type entrapment area 11 is
By selectively forming the upper electrical contact portion 10 only outside the upper electrical contact portion 10, the electrical contact portion 10 does not have a reverse taper, and no step breaks occur in the aluminum electrode 7. The poly-7 silicon 6 serves as a resistor, and the nitride film 12 is provided to further prevent moisture from entering and improve the reliability of the device.
〔発明の幼果」
以上説明したように不発明は、電気的コンタクトを取る
ために酸化膜のような絶縁膜を開孔する際、エツチング
速度の速いリンガラスは電気的コンタクト部より広い範
囲で先にエツチングし、そのあとで酸化膜等を形成した
のち、コンタクト部をリンガラス層より狭い範囲で開孔
１−ることにより、逆デーパ−とはならないようにする
こと罠より、アルミニウム電極の段切れ？防止でき、歩
留・付順性とも安定した′ｆ−尋体装体装置造できる効
果がある。[The fruit of the invention] As explained above, the invention is that when opening a hole in an insulating film such as an oxide film to make an electrical contact, phosphorus glass, which has a high etching rate, can be used over a wider area than the electrical contact area. After first etching and then forming an oxide film, etc., the contact area is opened in a narrower area than the phosphor glass layer to avoid a reverse taper. A break? This has the effect of making it possible to manufacture a 'f-thickness body packaging device with stable yield and placement performance.
第１図は本発明の一実施例を説明するための半導体装置
の縦断面図、第２図（工率発明の他の実施列を説明する
ための半導体装置の縦断面図、第３図は従来の半導体装
置の縦断面図である。
１．１１・・・・・・Ｐ型饋域、２・・・・・・Ｎ型領
域、３・・・・・・Ｎ十型領域、４１．４２・・・・・
・酸化膜、５・・・・・・リンガラス層、６・・・・・
・ポリシリコン、７・・・・・・アルミニウム電極、８
・・・・・・逆チー・・一部、９・・・・・・段切れ部
、ｌＯ・・・・・・昂；気的コンタクト部、１２・・・
・・・チツ化膜。FIG. 1 is a vertical cross-sectional view of a semiconductor device for explaining one embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a semiconductor device for explaining another embodiment of the invention, and FIG. It is a vertical cross-sectional view of a conventional semiconductor device. 1.11...P-type region, 2...N-type region, 3...N-type region, 41. 42...
・Oxide film, 5... Phosphorous glass layer, 6...
・Polysilicon, 7...Aluminum electrode, 8
・・・・・・Reverse chi・・Part, 9・・・・Step break part, 1O・・・Air contact part, 12・・・・
... Chitification membrane.
Claims (1)
、前記第１の絶縁層上にナトリウム等の不純物イオンを
捕獲しやすい性質を有し、前記第１の絶縁層よりエッチ
ング速度の大きい第２の絶縁層を形成する工程と、該第
２の絶縁層の所定領域を選択的に除去し第１の開口部を
形成する工程と、該第１の開口部及び前記第２の絶縁層
を覆って前記第２の絶縁層よりエッチング速度の小さい
第３の絶縁層を形成する工程と、前記第１の開口部内の
所定領域の前記第３の絶縁層及び前記第１の絶縁層を選
択的に除去することにより前記半導体基板の前記一主面
に達する第２の開口部を設ける工程とを有することを特
徴とする半導体装置の製造方法。A step of forming a first insulating layer on one main surface of the semiconductor substrate, and a step of forming a first insulating layer on the first insulating layer, which has a property of easily capturing impurity ions such as sodium, and has a higher etching rate than the first insulating layer. a step of forming a large second insulating layer; a step of selectively removing a predetermined region of the second insulating layer to form a first opening; and a step of forming a first opening and the second insulating layer. forming a third insulating layer covering the second insulating layer and having a lower etching rate than the second insulating layer; and removing the third insulating layer and the first insulating layer in a predetermined region within the first opening. and providing a second opening that reaches the one main surface of the semiconductor substrate by selectively removing the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15806287A JPS642335A (en) | 1987-06-24 | 1987-06-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15806287A JPS642335A (en) | 1987-06-24 | 1987-06-24 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH012335A true JPH012335A (en) | 1989-01-06 |
| JPS642335A JPS642335A (en) | 1989-01-06 |
Family
ID=15663466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15806287A Pending JPS642335A (en) | 1987-06-24 | 1987-06-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS642335A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH044837A (en) * | 1990-04-23 | 1992-01-09 | Rheon Autom Mach Co Ltd | Preparation of baking dough sheet and machine therefor |
| JPH10270555A (en) | 1997-03-27 | 1998-10-09 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JP5055704B2 (en) * | 2004-03-29 | 2012-10-24 | ヤマハ株式会社 | Manufacturing method of semiconductor device |
| CN100370580C (en) | 2004-03-29 | 2008-02-20 | 雅马哈株式会社 | Semiconductor wafer and its producing method |
| JP6536814B2 (en) * | 2015-09-18 | 2019-07-03 | サンケン電気株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57199237A (en) * | 1981-06-01 | 1982-12-07 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS634646A (en) * | 1986-06-24 | 1988-01-09 | Matsushita Electric Works Ltd | Manufacture of semiconductor device |
-
1987
- 1987-06-24 JP JP15806287A patent/JPS642335A/en active Pending
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