JPS60187055A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the parasitic resistance of the active element to be formed on a semiconductor substrate by a method wherein a metal silicide layer is provided between the semiconductor substrate and the epitaxial layer located above the semiconductor substrate, and an electrode is picked up through the intermediary of said metal silicide layer. CONSTITUTION:A metal silicide layer 12 is formed between an epitaxial layer 14 and a semiconductor substrate 10. A diffusion layer 16 to be used for connection of an n<+> type collector, a p type base diffusion layer 18 and an n<+> type diffusion layer 20 are formed on said layer 14 respectively. Also, an Al electrode 24 is formed from above of an oxide film 22, and an npn bipolar transistor TRQ1 is formed using said electrode 24. At this point, the layer 16 is connected to the layer 12. As a result, the collector electrode is picked up through the intermediary of the layers 12 and 16. In this instance, the resistance value of the layer 12 is remarkably made lower than that of the diffusion layer and, besides, the layer 12 is provided on the lower side of the layer 14. As a result, the resistance of the TRQ1 which is in parasitic in series to the collector becomes very low, thereby enabling to improve the characteristics such as working speed and the like of the TRQ1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor integrated circuit device technology, and particularly to technology that is particularly effective when applied to bipolar semiconductor integrated circuit devices.

[Background technology]

For example, in a semiconductor integrated circuit device in which a bipolar transistor is formed, in order to lower the collector resistance of the bipolar transistor, a buried layer made of a diffusion layer is provided in the region where the bipolar transistor is formed. . (Special Publication No. 40-19,859).

However, in such technology, since the buried layer is a diffusion layer, the resistance of the diffusion layer itself increases the collector resistance of a bipolar transistor, for example.
The inventor has found that this problem arises.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device technology that can reduce the parasitic resistance of active elements formed on a semiconductor substrate and improve their characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

In other words, by taking out the electrode through the metal silicide layer, the purpose is to reduce the parasitic resistance of the active element formed on the semiconductor substrate and improve its characteristics. .

[Example 1] Hereinafter, a typical example of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 1 shows a first embodiment of a semiconductor integrated circuit device according to the present invention.

The semiconductor integrated circuit device shown in the figure first uses a semiconductor substrate formed by forming a p-type silicon single crystal semi-dead substrate 10K and an n-type silicon epitaxial layer 14. A metal silicide layer 12 is formed between the epitaxial layer 14 and the substrate 10. That is, the epitaxial layer 14 is grown on the metal silicide layer 12. In this epitaxial layer 14, an n+ pear-shaped collector connection diffusion layer 16, a p-type base diffusion layer 18, and an n++ emitter diffusion layer 20 are selectively diffused.

Further, an aluminum electrode 24 is formed on the oxide film 22 in which holes are partially provided, thereby forming an npn type bipolar transistor Q1.

Here, the collector connection diffusion layer 16 reaches and connects to the metal silicide layer 12. As a result, the collector electrode of transistor Q1 is taken out via its metal silicide layer 12 and collector connection diffusion layer 16. What should be noted at this time is that the resistance of the metal silicide layer 12 is significantly lower than that of the diffusion layer, and that this low resistance metal silicide layer 12 is provided below the epitaxial layer 4. That's true. As a result, the resistance parasitic in series with the collector of the bipolar transistor Q1 becomes extremely low, and therefore the characteristics such as the operating speed of the bipolar transistor Q1 can be greatly improved.

Note that the metal silicide layer 12 may be formed entirely between the epitaxial layer 14 and the substrate 10, or may be formed partially to function, for example, as a wiring.

[Embodiment 2] FIG. 2 shows a second embodiment of the semiconductor integrated circuit device according to the present invention.

In the semiconductor integrated circuit device shown in the figure, a groove 30 and a recess 32 are formed in the row silicon epitaxial layer 14 by, for example, anisotropic etching. A p+ type separation layer 26 is diffused and formed at the bottom of the groove 32, thereby separating electrically independent element forming regions al, a2, . . . . A metal silicide layer 1 is provided below the epitaxial layer 14 in each element forming region al, a2.
2 is formed into an island shape. Furthermore, in area a1, p
Mold base diffusion layer 20. The n++ emitter diffusion layer 18a and the aluminum electrode 24 form an npn bipolar transistor Q1. Further, in the region a2, a p-type collector diffusion layer 19a, a p-type emitter diffusion layer 1
9b and the θ aluminum electrode 24 form a pnp type laterally transistor Q2. Note that C represents a collector, B represents a base, and E represents an emitter.

Here, the metal silicide layer 12 is formed in each element formation region a1. By being located between the epitaxial layer 14 and the substrate 10 at each region a2, each region al, a2
It functions as a buried layer that reduces the resistance of the substrate. Further, in region a1, a part of the metal silicide layer 12 is located in the recess 32, and is directly connected to the aluminum electrode 24 at this part, so that a very low collector resistance is achieved. . The recess 32 is formed by expanding a part of the groove 30. The groove portion 30 reduces the width of the separation layer 26 in the lateral direction, thereby reducing the distance between the element formation regions al, a2, etc., thereby making it possible to increase the integration density. .

[Embodiment 3] FIG. 3 shows a third embodiment of the semiconductor integrated circuit device according to the present invention.

In the semiconductor integrated circuit device shown in the figure, a recess 34 is previously formed by etching on the substrate 10 in a portion where a bipolar transistor Q1 is to be formed. As a result, the thickness of the epitaxial layer 14 in the relevant portion is selectively increased, and, for example, a high voltage bipolar transistor Q1 is formed.
K so that it can be formed. Even in this case, a sufficiently low collector resistance can be obtained by taking out the collector electrode through the metal silicide layer 12 provided between the epitaxial layer 14 and the substrate 10. Further, by taking out the electrode at a thin part of the epitaxial layer 14, that is, at the edge of the recess 34, an even lower collector resistance can be obtained. This embodiment is particularly suitable for a semiconductor integrated circuit device formed with a mixture of analog circuits and digital circuits, for example.

[Embodiment 4] FIG. 4 shows a fourth embodiment of a semiconductor integrated circuit device according to the present invention.

The embodiment shown in the figure is a semiconductor integrated circuit device in which active elements are formed in an epitaxial layer formed on a semiconductor substrate, and a metal silicide layer is interposed between the semiconductor substrate and the epitaxial layer. Active elements are formed on the semiconductor substrate side below this metal silicide layer, and furthermore, the active elements on this substrate side are connected to the active elements on the epitaxial layer side via the metal silicide layer. It is characterized by the presence of

To explain more specifically, the semiconductor integrated circuit device according to this embodiment is as shown in FIG.
A first n-type silicon epitaxial layer 14A is formed on a p-type silicon single crystal semiconductor substrate 1o, and a second n-type silicon epitaxial layer 14B is further formed thereon. has been done. Bipolar transistors Ql, Q3 . Q4
is formed.

There is n between the first epitaxial layer 14A and the substrate 1o.
A buried layer 11 made of a + type scattering layer is provided in an island shape, and each i
bipolar transistors Ql,
Q3 is formed. 188° 18b & ip type hess diffusion layer, 20a and 20b are n type emitter diffusion layers, and 16a and 16b are n+ pear type collector connection diffusion layers. Each element forming region is electrically isolated by a partial oxide film 23 formed by LOCOS and a p-type isolation layer 26. Then, the partially opened oxide film 2
By the metal silicide layer 12 formed from above 2,
The electrodes are being taken out and the wiring between the electrodes is being carried out.

The second epitaxial layer 14B is the first epitaxial layer 1 in which bipolar transistors Ql and Q3 are formed.
4A, and a bipolar transistor Q4 is also formed here. 18c is the p-type base diffusion layer, 20c is the n++ emitter diffusion layer, and 16c is the
indicate n+ pear-shaped collector connection diffusion layers, respectively. Also,
An isolation region is formed by the partial oxide film 23 and the p++ isolation layer 26. Then, the partially opened oxide film 2
An aluminum electrode 24 is taken out from above 2. In this case, the second epitaxial layer 1
4B, only the portion above the metal silicide layer 12 is made into a single crystal 1, and the other portion is in a polycrystalline state. Transistor Q4 is formed by selecting the single crystal portion.

Therefore, the metal silicide layer 12 is
It is also formed in a portion corresponding to the region where 4 is formed.

Also in this embodiment, the second epitaxial layer 14B
The IC-formed transistor Q4 is
Due to the metal silicide layer 12 formed in the region 4,
The trap is such that its collector resistance is reduced.

Furthermore, the metal silicide layer 12 is applied to the transistor Q1. Q3
The transistors Q1. It also functions as a wiring that interconnects Q3 and the transistor Q4 formed in the second epitaxial layer 14B. Therefore, each transistor Q1. Q3. Q
4 can be connected to each other, for example, as shown in FIG.

[Embodiment 5] Next, FIGS. 5 to 8 show an example of a method for manufacturing the semiconductor integrated circuit device shown in FIG. 1 in the order of steps. Each figure will be explained below.

FIG. 5 shows a p-type silicon single crystal semiconductor substrate 10 on which a metal silicide layer 12 is formed to form the semiconductor device shown in FIG. To form the metal silicide layer 12, first, a metal such as aluminum or platinum is deposited on the entire surface of the substrate 100 by sputtering or the like, and then buttering etching is performed. Next, the patterned metal and the substrate 10 are reacted to form a metal silicide layer 12.

After this, unreacted metal is removed.

FIG. 6 shows a state in which an epitaxial layer 14 is formed on the substrate IO of FIG. At this time, silicon in a single crystal state can be grown in a vapor phase on the metal silicide layer 12.

FIG. 7 shows a state in which an element region is formed in the epitaxial layer 14. That is, an n+ pear-shaped collector connection diffusion layer 16. P-type base diffusion layer 18. and n+
A type emitter diffusion layer 20 is sequentially formed. 22 is a surface oxide film.

FIG. 8 shows a state in which an aluminum electrode 24 is provided to form an npn type bipolar transistor Q1.

[Embodiment 6] FIGS. 9 to 13 show an example of a method for manufacturing the semiconductor integrated circuit device shown in FIG. 3 in the order of steps. Each figure will be explained below.

FIG. 9 shows a semiconductor substrate 1 on which a metal silicide layer 12 is formed to form the semiconductor integrated circuit device shown in FIG.
Indicates 0. Metal silicide layer 12 is formed in the same manner as the process shown in FIG.

al and a2 each indicate a portion that will become an element formation region.

FIG. 10 shows a state in which an epitaxial layer 14 is formed on the semiconductor substrate 10 of FIG. This epitaxial layer 14
is formed in a single crystal state.

FIG. 11 shows a state in which grooves 30 and recesses 32 are formed in the epitaxial layer 14 by anisotropic etching.

FIG. 12 shows element forming regions al, a2 electrically isolated from each other by diffusing the p-type isolation layer 26 into the bottom of the groove 30, and further, within each region al, a2,
P-type base diffusion layer 18a.

n+ type emitter diffusion layer 20. p-type collector diffusion layer 19a
, shows a state in which a p-type emitter diffusion layer 19b is formed.

FIG. 13 shows a state in which an aluminum electrode 24 is formed to form an npn type bipolar transistor Q1 and a pnp type lateral bipolar transistor Q2.

[Embodiment 7] FIGS. 14 to 18 show an example of the method for manufacturing the semiconductor integrated circuit device shown in FIG. 4 in step 111. Each figure will be explained below.

FIG. 14 shows a semiconductor substrate that has been preprocessed to form the semiconductor integrated circuit device shown in FIG. That is,
A first n-type silicon epitaxial layer 14A is formed on the p-type silicon single crystal semiconductor substrate 10. At this time, between the first epitaxial layer 14A and the substrate 10, a buried layer 11 made of an n+ type scattering layer is provided in the form of an island. Bipolar transistors Ql and Q3 are formed on each buried layer 11, respectively. 1'8 a, 18 b&
1p type base diffusion layer, 20a and 20b are n++ emitter diffusion layers, and 16a and 16b are n+ pear type collector connection diffusion layers, respectively. Between each element formation region, L
Electrical isolation is provided by the partial oxide film 23 made of OCO8 and the p++ isolation layer 26.

FIG. 15 shows a state in which a metal silicide layer 12 is formed on the semiconductor substrate of FIG. 14. This metal silicide layer 12 is used to conduct electrode extraction and wiring between the electrodes (internal wiring). The metal silicide layer 12 is formed by, for example, depositing metal and silicon by a spuntan ring method or the like, and then performing a laser annealing process.

FIG. 16 shows a state in which a second epitaxial layer 14B is formed on the metal silicide layer 12. This second
The epitaxial layer 14B is the first epitaxial layer 14 in which the bipolar transistor QllQ3 is formed.
Formed on A. This second epitaxial layer 14
B is grown using the metal silicide layer 12 as a seed, so that only the portion above the metal silicide layer 12 is made into a single crystal, and the other portion is in a polycrystalline state.

15a represents a single crystal portion, and 15b represents a polycrystalline portion.

FIG. 17 shows a state in which isolation regions are formed in the second epitaxial layer 14B. This isolation region is formed by a partial oxide film 23 formed by LOCO 8 and a p-type isolation layer 26.

FIG. 18 shows a state in which the element region has been formed and the electrodes have been taken out. That is, the second epitaxial layer 14B
A bipolar transistor Q4 is formed therein. 18c is a p-type base diffusion layer, 20c is an n++ emitter diffusion layer, and 16c is an n+ pear-shaped collector connection diffusion layer. Then, the aluminum electrode 24 is taken out from above the partially opened oxide film 22.

As a result, a semiconductor integrated circuit device having the three-dimensional structure shown in FIG. 4 is formed.

〔effect〕

(1) In a semiconductor integrated circuit device in which active elements are formed in an epitaxial layer formed on a semiconductor substrate, a metal silicide layer is interposed between the semiconductor substrate and the epitaxial layer, and the metal silicide layer is By extracting the electrodes of the active element through the semiconductor substrate, it is possible to reduce the parasitic resistance of the active element formed on the semiconductor substrate and improve its characteristics.

(2) In a semiconductor integrated circuit device in which active elements are formed in an epitaxial layer formed on a semiconductor substrate, a metal silicide is interposed between the semiconductor substrate and the epitaxial layer, and a metal silicide is provided below the metal silicide. By forming an active element on the semiconductor substrate side, and further connecting the active element on the substrate side to the active element on the epitaxial layer side through the metal silicide layer, a three-dimensional structure and a multi-layer structure can be formed. The effect of being able to configure a semiconductor integrated circuit device with a dimensional structure can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). Not even.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to bipolar semiconductor integrated circuit device technology, which is the background field of application.
The present invention is not limited thereto, and can be applied to, for example, MO8m conductor integrated circuit device technology.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part showing a first embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a cross-sectional view of a main part showing a second embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 5 is a sectional view of a main part and an equivalent circuit diagram showing a fourth embodiment of a semiconductor integrated circuit device according to the present invention; FIG. 5 is a semiconductor substrate on which a metal silicide layer is formed to form the semiconductor device shown in FIG. 1; 6 is a sectional view showing a state in which an epitaxial layer is formed on the substrate of FIG. 5, FIG. 7 is a sectional view showing a state in which an element region is formed in the epitaxial layer, and FIG. 9 is a cross-sectional view showing a state with electrodes taken out; FIG. 9 is a cross-sectional view of a main part showing a semiconductor substrate on which a metal silicide layer is formed to form the semiconductor integrated circuit device shown in FIG. 2; FIG. 9 is a cross-sectional view showing a state in which an epitaxial layer is formed on the semiconductor substrate, FIG. 11 is a cross-sectional view showing a state in which grooves and recesses are formed in the epitaxial layer by etching, and FIG. 13 is a sectional view showing a state in which an element region is formed in the semiconductor integrated circuit device, FIG. 13 is a sectional view showing a state in which electrodes are taken out, and FIG. 15 is a cross-sectional view showing a state in which a metal silicide layer is formed on the semiconductor substrate of FIG. 14, and FIG. 16 is a cross-sectional view showing a state in which an epitaxial layer is formed on the metal silicide. FIG. 17 is a cross-sectional view showing a state in which an element region is formed in the epitaxial layer, and FIG. 18 is a cross-sectional view showing a state in which the final electrode is taken out. 10...p- type silicon semiconductor substrate, ]1...n+
Mold embedding layer, 12... Metal silicide layer, 14.14A
. 14B...Epitaxial layer, 15a...Single crystal portion, 15b...Polycrystalline portion, 16. 16 an 1
6 b. 16c...N+ type collector connection diffusion layer, 18°18
a, 18b, 18c - p-type base diffusion layer, 19a...
-p type collector diffusion layer, 19b... p type emitter diffusion layer, 20... n+ type emitter diffusion layer, 22... oxide film, 23... local oxide film, 24... aluminum electrode, 26 . . . p-type separation layer, 30 . . . etched groove, 32 . . . etched recess, al. a2-element formation region, Ql, Q2. Q3. Q4・
...active element (bipolar transistor), C...collector, B...pace, E...emitter, p+p
+ p, ., p-type conductive region, n, -n, "n . . .
n-type conductive region. Figure 5 Figure 6 Figure 7 Figure 8 Figure 7r2θ /θ

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device in which active elements are formed in an epitaxial layer formed on a semiconductor substrate, comprising a metal silicide layer between the semiconductor substrate and the epitaxial layer, A semiconductor integrated circuit device characterized in that electrodes of the active element are taken out through the metal silicide layer. 2. The semiconductor integrated circuit device according to claim 1, wherein wiring is provided by the metal silicide layer. 3. A semiconductor integrated circuit device in which active elements are formed in an epitaxial layer formed on a semiconductor substrate, in which a metal silicide layer is interposed between the semiconductor substrate and the epitaxial layer, and the metal silicide layer is 1. A semiconductor integrated circuit device comprising an active element on a lower semiconductor substrate side, further comprising an active element on the substrate side connected to an active element on the epitaxial layer side via the metal silicide layer.