JPS63246862A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63246862A JPS63246862A JP8151687A JP8151687A JPS63246862A JP S63246862 A JPS63246862 A JP S63246862A JP 8151687 A JP8151687 A JP 8151687A JP 8151687 A JP8151687 A JP 8151687A JP S63246862 A JPS63246862 A JP S63246862A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- film
- electrode
- bipolar transistor
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 10
- 239000010408 film Substances 0.000 abstract description 30
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 7
- 230000001771 impaired effect Effects 0.000 abstract description 2
- 239000011810 insulating material Substances 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、一つの半導体基板上に少なくともＭＯＳトラ
ンジスタとバイポーラトランジスタとバイポーラトラン
ジスタとを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having at least a MOS transistor, a bipolar transistor, and a bipolar transistor on one semiconductor substrate.
近年、バイポーラ素子とＣＭＯ８素子を同一半導体基板
上に集積化しバイポーラ素子が有する高速性とＣＭＯ８
素子が有する低消費電力という画素子の利点を併せ持っ
た複合化半導体装置としてＢｉ−ＭＯＳ 或いはＢｉ
−ＣＭＯ８半導体装置が実用化されている。この様な複
合化半導体装置においては、相互の素子特性を犠牲にす
ることなく、個々の素子特性を生かし相互に補完する特
性を有する事が重要である。In recent years, bipolar elements and CMO8 elements have been integrated on the same semiconductor substrate, and the high speed of bipolar elements and CMO8 elements have been integrated.
Bi-MOS or Bi
-CMO8 semiconductor devices have been put into practical use. In such a composite semiconductor device, it is important to have characteristics that complement each other by making use of the characteristics of individual elements without sacrificing the characteristics of each element.
シリコンゲート電極を有するＭＯＳトランジスタにおい
ては、周知の如くシリコンゲート電極を信号線等の配線
層として利用すふために不純物を添加して抵抗を充分小
さくすることが一般的である。この目的に例えば不純物
リンが用いられ、こをを前記シリコンゲート電極に添加
するととで層抵抗を２０Ω／口程度まで下げることがで
きる。As is well known, in a MOS transistor having a silicon gate electrode, in order to use the silicon gate electrode as a wiring layer for a signal line or the like, it is common to add impurities to make the resistance sufficiently small. For this purpose, for example, impurity phosphorus is used, and by adding it to the silicon gate electrode, the layer resistance can be lowered to about 20 Ω/hole.
シリコンゲート電極の材質は一般的に多結晶シリコン薄
膜が使用されており、多結晶シリコン膜の膜厚は前記の
如く配線層として信号線等に利用すふ場合には厚い方が
よく、一方多結晶シリコンの加工性精度からは薄い方が
望まれる。従って、該多結晶シリコン膜厚は要求される
ＭＯＳトランジスタの性能によっても異なるが、０．３
Ｓｏ、５μｍ程度の範囲で使われている。The material of the silicon gate electrode is generally a polycrystalline silicon thin film, and as mentioned above, the thicker the polycrystalline silicon film is, the better when it is used as a wiring layer for signal lines, etc. From the viewpoint of machinability accuracy of crystalline silicon, a thinner one is desirable. Therefore, the thickness of the polycrystalline silicon film varies depending on the required performance of the MOS transistor, but is 0.3
So, it is used in a range of about 5 μm.
一方、多結晶シリコンでエミッタ・ベース・コレクタ電
極が構成されているバイポーラＮＰＮトランジスタにお
いては、エミッタ・ベース・コレクタの各領域に導入さ
れたのと同一不純物が前記多結晶シリコン電極にも添加
されていることが一般的である。On the other hand, in a bipolar NPN transistor whose emitter, base, and collector electrodes are made of polycrystalline silicon, the same impurities introduced into each region of the emitter, base, and collector are also doped into the polycrystalline silicon electrode. It is common for there to be.
又、シリコンゲート電極、エミッタ・ベース・コレクタ
電極はドライエツチングにより形成されている。この際
、多結晶シリコンに添加されている不純物の１！１１ｇ
４、濃度等の違いによりエツチング速度が大巾に異なる
。ドライエツチングに用いられるガスの種類、組成、流
量、圧力等の電性を変ることによりエツチング速度を変
化することができるが、多結晶シリコンに添加する不純
物の種類等の差によって生じるエツチング速度の差まで
をおぎなう事は出来ない。この際、多結晶シリコン膜厚
を薄くすればある程度の効果は認められるが、プロセス
上の問題により各電極部分に応じた膜厚にすることは困
難である。Furthermore, the silicon gate electrode and emitter/base/collector electrodes are formed by dry etching. At this time, 1!11g of impurities added to polycrystalline silicon
4. Etching speed varies widely due to differences in concentration, etc. The etching rate can be changed by changing the type, composition, flow rate, pressure, etc. of the gas used for dry etching, but the etching rate may vary depending on the type of impurity added to the polycrystalline silicon. It is not possible to cover that. At this time, if the polycrystalline silicon film is made thinner, some effect can be recognized, but due to process problems, it is difficult to make the film thickness suitable for each electrode portion.
尚、多結晶シリコン膜に添加した不純物により、各々エ
ミッタ・ベース・コレクタ領域が形成されるＮＰＮトラ
ンジスタにおいて、多結晶シリコン膜の厚さｌｌ１２０
００ Ｘ以下と出来るだけ薄い方が良好な特性を得るの
で好ましい。In addition, in an NPN transistor in which the emitter, base, and collector regions are formed by impurities added to the polycrystalline silicon film, the thickness of the polycrystalline silicon film is 120 mm.
It is preferable that the thickness be as thin as possible, such as 00X or less, since better characteristics can be obtained.
〔発明が解決しようとする問題点３
種類の異なる不純物が添加された多結晶シリコンを電、
甑として用いる場合には、前述した理由により同時に形
成出来ない問題が生じる。又、ＭＯＳトランジスタとＮ
ＰＮトランジスタにおける多結晶シリコン電極の最適膜
厚が異なっている。従って、Ｂｉ−０ＭＯ８或はＢｉ−
ＭＯＳ 半導体装置の様な複合化半導体装置を実現する
のに際して相互の素子特性を犠牲にすることなく同一半
導体基板に組み込むためＫは製造工程が長くなる等の経
済的損失が大きくなるという欠点がある。[Problems to be solved by the invention: Polycrystalline silicon doped with different types of impurities is
When used as a koshi, there arises a problem that it cannot be formed at the same time due to the above-mentioned reason. Also, MOS transistor and N
The optimum film thickness of the polycrystalline silicon electrode in a PN transistor is different. Therefore, Bi-0MO8 or Bi-
When realizing a composite semiconductor device such as a MOS semiconductor device, K has the drawback of increasing the economic loss due to longer manufacturing process because it is integrated into the same semiconductor substrate without sacrificing the characteristics of each element. .
本発明は、Ｂｉ−０ＭＯ８或はＢｉ−ＭＯ８半導体装置
において、ＭＯＳトランジスタのゲート電極とバイポー
ラトランジスタのエミッタ・べ・ス・コレクタ電極が多
結晶シリコン薄膜から成り、バイポーラトランジスタに
おける該多結晶シリコン薄膜の膜厚は、ＭＯＳトランジ
スタのゲート電極のそれよりも半分以下であるととｆ：
特徴とする。The present invention provides a Bi-0MO8 or Bi-MO8 semiconductor device in which the gate electrode of a MOS transistor and the emitter-base-collector electrode of a bipolar transistor are made of a polycrystalline silicon thin film; The film thickness is less than half that of the gate electrode of the MOS transistor f:
Features.
さらに、バイポーラトランジスタの各電極間は、前記多
結晶シリコン薄膜が選択酸化された絶縁物で分離されて
いること全特徴とする。Further, each electrode of the bipolar transistor is characterized in that the polycrystalline silicon thin film is separated by an insulator that is selectively oxidized.
次に本発明の実施例として同一半導体基板上にＰチャン
ネルＭＯ８ｔｌンジスタとバイポーラトランジスタを形
成する場合について説明する。第１図（Ａ）に示すよう
に、まずＰ型シリコン基板ＩＫＮ型埋込層２ｔ−形成し
、その上にＮｕシリコン層３をエピタキシャル成長させ
る。次に、フォトレジストをマスクにボロン（Ｂ）をイ
オン打込みして絶縁領域４を形成し、いくつかの半導体
の島に分離する。その後耐酸化性膜をマスクにして選択
酸化膜５を形成する。Next, as an embodiment of the present invention, a case where a P-channel MO8tl transistor and a bipolar transistor are formed on the same semiconductor substrate will be described. As shown in FIG. 1A, first, an IKN type buried layer 2t- is formed on a P type silicon substrate, and a Nu silicon layer 3 is epitaxially grown thereon. Next, using a photoresist as a mask, boron (B) ions are implanted to form an insulating region 4, which is separated into several semiconductor islands. Thereafter, a selective oxide film 5 is formed using the oxidation-resistant film as a mask.
第１図（Ｂ）に示すように、ＰチャンネルＭＯＳトラン
ジスタとなる領域にゲート酸化膜６を形成する。次に、
バイポーラトランジスタとなる領域にペース領域７を形
成し、さらにバイポーラトランジスタとなる領域部分の
酸化膜を除去したのち半導体基板全面に良好なバイポー
ラトランジスタの特性が得られる最適膜厚（例えば１ｏ
ｏｏＸ ）の多結晶シリコン層８を被着する。As shown in FIG. 1B, a gate oxide film 6 is formed in a region that will become a P-channel MOS transistor. next,
After forming a pace region 7 in the region that will become a bipolar transistor and removing the oxide film in the region that will become a bipolar transistor, the optimum film thickness (for example, 100 nm) is formed on the entire surface of the semiconductor substrate to obtain good bipolar transistor characteristics.
A polycrystalline silicon layer 8 of ooX) is deposited.
第１図（Ｃ）に示すようｌ’（耐酸化性膜１２をマスク
にしてバイポーラトランジスタのエミッタ・ベース・コ
レクタ多結晶シリコンミ概容々を選択酔化し、エミッタ
１０．ベース１１、コレクタ１２の各電極となる領域を
互に絶縁分離する。As shown in FIG. 1C, the emitter, base, and collector polycrystalline silicon layers of the bipolar transistor are selectively oxidized using the oxidation-resistant film 12 as a mask, and each electrode of the emitter 10, base 11, and collector 12 is heated. The regions are insulated and separated from each other.
次に、第１図（Ｄ）に示すようＫＭＯ８トランジスタ領
域部分の耐酸化性膜を除去しゲートｔａとして必要にな
る多結晶シリコン膜厚８′を追加被着する。Next, as shown in FIG. 1D, the oxidation-resistant film in the KMO8 transistor region is removed, and a polycrystalline silicon film 8' thick, which is required as the gate ta, is additionally deposited.
その後、第１図（Ｅ）に示すように、多結晶シリコン膜
８．８′に熱拡散法等により不純物原子リンを添加し、
シリコンゲート電極の抵抗を低くする。Thereafter, as shown in FIG. 1(E), impurity atoms of phosphorus are added to the polycrystalline silicon film 8.8' by thermal diffusion method or the like.
Lower the resistance of the silicon gate electrode.
尚この際、バイポーラトランジスタの各電極の多結晶シ
リコン８は耐酸化性膜１２でおおわれているので不純物
が添加されない。次いで、フォトレジストをマスクに多
結晶シリコン８．８を選択エツチングしてＭＯＳトラン
ジスタのゲート電極１３ｔ−形成すると共に、バイポー
ラトランジスタ上の多結晶シリコン８′を除去する。尚
、前記耐酸化性膜１２が多結晶シリコン８′を除去する
際のストッパーとなるので下層の多結晶シリコン電極は
エツチグされない。At this time, since the polycrystalline silicon 8 of each electrode of the bipolar transistor is covered with the oxidation-resistant film 12, no impurity is added. Next, the polycrystalline silicon 8.8 is selectively etched using the photoresist as a mask to form the gate electrode 13t of the MOS transistor, and the polycrystalline silicon 8' on the bipolar transistor is removed. Incidentally, since the oxidation-resistant film 12 serves as a stopper when removing the polycrystalline silicon 8', the underlying polycrystalline silicon electrode is not etched.
更にＭＯＳトランジスタの拡散層１４を不純物ボロンを
イオン注入法により添加して形成する。Furthermore, the diffusion layer 14 of the MOS transistor is formed by adding impurity boron by ion implantation.
この際、同時にバイポーラトランジスタのベース電極１
１にも不純物ポロンを添加しベース電極の抵抗を小さく
する。次いで不純物ヒ素をイオン注入法によりエミッタ
及びコレクタ電極１０．９に添加し、バイポーラトラン
ジスタのエミッタ領域及びコレクタ取り出し電極を形成
する。At this time, at the same time, the base electrode 1 of the bipolar transistor
1 is also doped with impurity poron to reduce the resistance of the base electrode. Next, impurity arsenic is added to the emitter and collector electrodes 10.9 by ion implantation to form the emitter region and collector lead-out electrode of the bipolar transistor.
更に半導体装置として完成するために、第１図（Ｆ）に
示すように、ＰＳＧ等の絶縁膜５を被着し、該絶縁膜１
５に上層配線と接続するための開孔窓を開口し蒸着法等
によりアルミニウム１６を被着したのち上ｉ−配線を形
成する。Furthermore, in order to complete the semiconductor device, an insulating film 5 such as PSG is deposited as shown in FIG.
An aperture window is opened in 5 for connection to the upper layer wiring, and aluminum 16 is deposited by vapor deposition or the like, after which an upper i-wiring is formed.
以上説明したように種類の異なる不純物が添加されるエ
ミッタ・ベース・コレクタ多結晶シリコン電極間相互を
酸化膜分離することにより前記各電極を容易にかつ同時
に形成出来る。又、ＭＯＳトランジスタのゲート電極及
びバイポーラトランジスタのエミッタ・ベース・コレク
タ電極の多結晶シリコン膜厚を各々最適な膜厚とするこ
とが出来るので各々の特性はそこなわれずにすむ。As explained above, by separating the emitter, base, and collector polycrystalline silicon electrodes to which different types of impurities are added by an oxide film, each of the electrodes can be formed easily and simultaneously. Further, since the polycrystalline silicon film thicknesses of the gate electrode of the MOS transistor and the emitter/base/collector electrode of the bipolar transistor can be set to the optimum film thicknesses, the characteristics of each can be maintained without being impaired.
また、Ｐｃｈ ＭＯＳトランジスタのソース・ドレイ
ン拡散層形成と同時にバイポーラトランジスタのペース
電極も形成することにより、引き出し抵抗を低くするこ
とが出来るという製造工程の簡略化が、バイポーラ、Ｍ
ＯＳトランジスタ相互の素子特性を犠牲にすることなし
に可能である。In addition, by forming the base electrode of the bipolar transistor at the same time as the source/drain diffusion layer formation of the Pch MOS transistor, the manufacturing process can be simplified by lowering the extraction resistance.
This is possible without sacrificing the device characteristics of the OS transistors.
尚、本発明の実施例ｔ−Ｐｃｈ ＭＯＳトランジスタ
とバイポーラトランジスタを同一半導体基板に形成する
Ｂｉ−ＭＯＳ半導体装置で説明したが、Ｐｃｈ とＮｃ
ｈ ＭＯＳトランジスタをバイポーラトランジスタと同
一半導体基板に形成するＢｉ −ＣＭＯＳ半導体装置を
実現する場合においてＮｃｈＭＯＳトランジスタのソー
ス・ドレイン拡散層形成と同時にバイポーラトランジス
タのエミッタ領域を形成可能となるのでＢｉ−０ＭＯ８
半導体装置と同じ製造工程で実現出来る大きな利点を持
っている。Although the embodiment of the present invention has been described as a Bi-MOS semiconductor device in which a t-Pch MOS transistor and a bipolar transistor are formed on the same semiconductor substrate, Pch and Nc
h When realizing a Bi-CMOS semiconductor device in which a MOS transistor and a bipolar transistor are formed on the same semiconductor substrate, the emitter region of the bipolar transistor can be formed at the same time as the source/drain diffusion layer of the NchMOS transistor is formed.
It has the great advantage of being realized in the same manufacturing process as semiconductor devices.
第１図（Ａ）〜（Ｆ）は本発明によるＢｉ−ＭＯＳ半導
体装置を実現する場合の各製造工程における断面図であ
る。
１・・・・・・Ｐ型シリコン基板、２・・・・・・Ｎ型
埋め地層、３・・・・・・Ｎ型エピタキシャル、４・・
・・・・Ｐ型絶縁領域、５・・・・・・酸化膜、６・・
・・・・ゲート酸化膜、７・・・・・・Ｐ型ベース領Ｍ
、８・・・・・・多結晶シリコン、９・・・・・・コレ
クタ電極、１０・・・・・・エミッタ電源、１１・・・
・・・ベース電極、１３・・・・・・ゲート電極、１４
・・・・・・Ｐ型拡散領域、１５・・・・・・絶縁膜、
１６・・・・・・アルミニウム、１２・・・・・・耐酸
化性膜。”
！ ！ 田
崖 ｌ 同FIGS. 1(A) to 1(F) are cross-sectional views in each manufacturing process when realizing a Bi-MOS semiconductor device according to the present invention. 1... P-type silicon substrate, 2... N-type buried layer, 3... N-type epitaxial, 4...
... P-type insulating region, 5 ... Oxide film, 6 ...
...Gate oxide film, 7...P type base region M
, 8... Polycrystalline silicon, 9... Collector electrode, 10... Emitter power supply, 11...
... Base electrode, 13 ... Gate electrode, 14
...P-type diffusion region, 15...Insulating film,
16... Aluminum, 12... Oxidation resistant film. ” !! Tagaki l Same
Claims (1)
リコンから成るＭＯＳトランジスタとエミッタ・ベース
・コレクタ電極が多結晶シリコンから成るバイポーラト
ランジスタとを有する半導体装置において、バイポーラ
トランジスタのエミッタ・ベース・コレクタ各電極の、
多結晶シリコン膜がＭＯＳトランジスタのゲート電極多
結晶シリコン膜厚の少なくとも半分以下であることを特
徴とする半導体装置。In a semiconductor device having, on one semiconductor substrate, a MOS transistor whose gate electrode is made of polycrystalline silicon and a bipolar transistor whose emitter, base, and collector electrodes are made of polycrystalline silicon, each of the emitter, base, and collector electrodes of the bipolar transistor is ,
A semiconductor device characterized in that the polycrystalline silicon film is at least half the thickness of a gate electrode polycrystalline silicon film of a MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8151687A JPS63246862A (en) | 1987-04-01 | 1987-04-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8151687A JPS63246862A (en) | 1987-04-01 | 1987-04-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63246862A true JPS63246862A (en) | 1988-10-13 |
Family
ID=13748509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8151687A Pending JPS63246862A (en) | 1987-04-01 | 1987-04-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63246862A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150058A (en) * | 1988-11-30 | 1990-06-08 | Nec Corp | Bipolar cmos composite semiconductor device |
| US5525530A (en) * | 1992-10-23 | 1996-06-11 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
| US6441441B1 (en) * | 1996-06-07 | 2002-08-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
-
1987
- 1987-04-01 JP JP8151687A patent/JPS63246862A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150058A (en) * | 1988-11-30 | 1990-06-08 | Nec Corp | Bipolar cmos composite semiconductor device |
| US5525530A (en) * | 1992-10-23 | 1996-06-11 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
| US5753957A (en) * | 1992-10-23 | 1998-05-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| US6441441B1 (en) * | 1996-06-07 | 2002-08-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
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