JPS6362377A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate parasitic effect and to reduce the saturation resistance of the collector of a transistor, by insulating all elements constituting an LSI with insulators. CONSTITUTION:Element isolation oxide films 12 are provided on an Si substrate 11. An n<+> diffused layer 14 for compensating collector resistance, a base region 15, an emitter region 16, electrode interconnections 17a-17c for an emitter, a base and a collector, and an element protecting film 18 are sequentially formed. Then an Si substrate 20 is bonded. The Si substrate 11 is removed until the bottom parts of the element isolation films 12 are exposed. Thereafter, a platinum film is deposited on the entire surface, and heat treatment is performed. A platinum silicide layer 22 is formed only at the lower part of a transistor region. A supporting substrate 24 such as a quartz substrate is bonded with polyimide 23. Thereafter the Si substrate 20 is removed. Thus the bipolar LSI, in which all the constituent elements are insulated with insulators, can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a bipolar LSI with low collector saturation resistance and no parasitic effects.
It is related to.

[Conventional technology]

Conventionally, the transistors used in bipolar LSIs are
Generally, as shown in FIG.
In the epitaxially grown layer 4, a base region 5. It is formed by arranging an emitter region 6. In addition, in the same figure,
2a and 2b are n-type buried layers with high impurity concentration, 3 is a P+ diffusion layer for a channel stopper, 7 is an element isolation oxide film, 8 is a surface protection oxide film, and 9 is an n+ diffusion layer for collector resistance compensation. Further, 10a, 10b, and 10c are electrode wirings for the emitter, base, and collector, respectively.

[Problem that the invention seeks to solve]

One of the factors that determines the operating speed of the conventional bipolar LSI mentioned above is the resistance of the n'' buried layer, in other words, the collector saturation resistance r3c of the transistor.

At the same time, the capacitance Csub between the n+ buried layers 2a, 2b and the P- semiconductor substrate 1 is also one of them. r fie+ Cs
The operating speed can be improved by reducing ub, but the normal ion implantation method or thermal diffusion method for forming the N1 buried layer not only has a limit to lowering the resistance but also limits the amount of impurity doping. As the growth increases, the rise of the N1 buried layer into the epitaxial growth layer and the increase in the amount of auto-doping of impurities become noticeable, resulting in an increase in the base-collector junction capacitance cab, resulting in a delay in operating speed and a decrease in breakdown voltage. This may have negative effects such as a decrease in Further, in FIG. 2, transistors Tr1 and Tr2 are electrically insulated by an isolation oxide film 7 and a channel stopper layer 3, but in order to prevent latch-up operation due to parasitic transistors, the relative distance between Tr1 and Tr2, the substrate ratio It was necessary to set extremely complicated parameters such as the resistance n and the impurity concentration of the buried layer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device which is free from parasitic effects and has an extremely small transistor collector saturation resistance rsc.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention eliminates parasitic effects by completely surrounding the side walls and bottom surface of the transistor formation region with an insulating material, and also significantly reduces r8Q by converting the bottom surface of the transistor formation region into a metal silicide layer. It is composed of the following characteristics:

[Example] Next, an example of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(f) are longitudinal cross-sectional views of pellets shown in order of steps to explain one embodiment of the present invention and its manufacturing method.

First, as shown in Figure 1(a), the specific resistance is 0.05 to 0.
．． An oxide film 12 for element isolation and a surface protection oxide film 13 are provided on an n-type Si substrate of about 1 Ωl.

Next, as shown in FIG. 1(b), an n+ diffusion layer 14 for collector resistance compensation is formed. Base area 15. Emitter region 16.
Electrode wiring 17a for emitter, base, and collector;
17b, 17c and the element protection film 18 are sequentially formed.

Next, as shown in FIG. 1(c), the Si substrate 20 is bonded using one polyimide as an adhesive.

At this time, it is necessary to bond the Si substrate 11 and the Si substrate 20 so that they are parallel to each other.

Next, as shown in FIG. 1(d), the Si substrate 11 is removed until the bottom of the element isolation oxide film 12 is exposed by using the lapping and borizing techniques used in the wafer polishing process, and then platinum is coated on the entire surface. A membrane 21 is applied.

Next, heat treatment is performed at about 400°C to 450°C in this state to cause a silicide reaction, and when the unreacted platinum film is removed with aqua regia, as shown in Figure 1(e), only the lower part of the transistor region is exposed. A platinum silicide layer 22 is formed.

Next, as shown in FIG. 1 (f>), a support substrate 24 made of an insulator such as a quartz substrate is bonded with polyimide 23, and then the Si substrate 20 is removed using a mixed solution of hydrofluoric acid and nitric acid. Further, by removing the polyimide 19 using hydrazine or 02 plasma, a bipolar LSI in which all the constituent elements of this embodiment are insulated with an insulator is completed.

Here, the Si substrate 20 serves as a reinforcing material and an element protecting material during lapping and borising. Furthermore, in this example, polyimide was used as the adhesive, but 450
Other materials may be used as long as they have heat resistance of about 0.degree. C. and excellent electrical insulation. Furthermore, the first
In figure (a), about 0.05 to 0.100 n-type Si
The substrate was used in order to obtain ohmic contact without forming a Schottky junction when forming platinum silicide.

〔Effect of the invention〕

As explained above, the present invention can completely suppress parasitic effects, which have been a problem in the past, by insulating all elements constituting an LSI with an insulator.

In addition, when realizing a conventional bipolar LSI, high concentration n+
Although the formation of a buried layer, a P+ channel stopper layer, and an n-type epitaxial growth layer were indispensable, according to the present invention, they are all unnecessary, and not only can the manufacturing cost and construction period of bipolar LSIs be significantly reduced, but also the manufacturing yield can be improved. Significant improvements can also be made.

Furthermore, the collector saturation resistance r3o of conventional bipolar LSIs could only be lowered to several tens of ohms at most, but in the present invention, by forming a platinum silicide layer, the collector saturation resistance r3o can be reduced to several ohms, which is less than 1/10 of the conventional value. rso
can be realized. As described above, the present invention has a remarkable effect on realizing a bipolar LSI with high performance and high yield.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are vertical cross-sectional views of a pellet shown in order of steps to explain an embodiment of the present invention and its manufacturing method, and FIG. 2 is a vertical cross-sectional view of an example of a conventional semiconductor integrated circuit device. It is a front view. 1.11.2O---8i substrate, 2a, 2b・-n'' buried layer, 3... Channel stopper layer, 4... Epitaxial layer, 5.15... Base region, 6, 16...・
・Emitter region, 7, 12... Oxide film for element isolation, 8
゜13...Surface protection oxide film, 9.14...N+ diffusion layer, 10a, 10b, 10c, 17a, 17b, 17C
... Electrode wiring, 18... Element protective film, 19.23.
...Polyimide, 21...Platinum film, 22...Platinum Shirisai 13 Noodle statue 4 [top ((+ Child 1 Cut beef l Eye 2nd figure)

Claims (1)

[Claims] 1. A semiconductor integrated circuit device, wherein side walls and a bottom surface of an island-shaped element region are all surrounded by an insulating material, and a metal silicide layer is provided on the bottom surface of the island-shaped element region.