JPH0462847A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a collector capacitance and make a transistor operable at a high speed, by forming, the parts corresponding to at least the part to come into an active region of a semiconductor device, into non-insulating regions, and forming the other parts into insulating regions, on the non-insulating region of a substrate, and by sticking on the surface thereof a different substrate from the foregoing substrate to form the complete semiconductor device. CONSTITUTION:On a P<->-type single crystal silicon substrate 11, a silicon oxide film 12, an N<+>-type polycrystalline silicon film 13, and a silicon oxide film 14 are formed in succession. On the predetermined part thereof, a window 14a is formed, and an N<+>-type polycrystalline silicon film 15 is so formed as to be buried therein. Then, while the foregoing is referred to as a substrate 16, the N<+>-type polycrystalline silicon film 15 is left only in the window 14a. On the other hand, an N<->-type single crystal silicon substrate 17 is prepared, and is stuck on the substrate 16. Caused by annealing when sticking, an N<+>-type collector diffusion layer 18 is formed in the part of the single crystal silicon substrate 17, which exists just over the N<+>-type polycrystalline silicon film 15. Thereby, a buried collector is formed with the N<+>-type polycrystalline silicon films 13, 15 and N<+>-type collector diffusion layer 18. Then, an N<->-type epitaxial layer 19 is grown on the surface of the substrate 17.

Description

[Detailed Description of the Invention] [Summary] S OI (Silicon on Insulato)
r) Regarding a semiconductor device having a structure and its manufacturing method, for the purpose of reducing the collector capacitance and increasing the speed, a first non-insulating region is formed under the element active region, and a first non-insulating region is formed under the element active region, and a collector electrode is connected to the first non-insulating region. a second non-insulating region electrically connected to the second non-insulating region, the first and second non-insulating regions constitute a buried collector, and the second non-insulating region is in contact with the first non-insulating region; An insulating region is formed between the non-insulating region and the non-insulating region constituting the element active region. In addition, during manufacturing, there is a step of forming a non-insulating region on the substrate via an insulating region, and a second step is to form a non-insulating region on the substrate via an insulating region. The method includes the steps of forming an insulating region and bonding another semiconductor substrate to the surface.

[Industrial application field]

The present invention relates to a semiconductor device having an SOI structure and a method for manufacturing the same.

SOT refers to a substrate structure in which a silicon film is provided as an insulating film on a substrate, especially a silicon substrate. It is also possible to form transistors on the underlying silicon substrate, and it has the potential to integrate multiple transistor layers. Because of this, it has been actively researched in recent years. Here, in the SOI l-transistor in which an embedded collector is formed, an increase in the collector capacitance becomes a problem as will be described later, and there is a demand for how to reduce this and increase the speed.

[Conventional technology]

FIG. 2 shows a structural diagram of a conventional example. In the figure, l is a P-type silicon substrate, 2 is a silicon oxide insulating film, 3 is a silicon layer, and the silicon layer 3 has a buried collector 4. with a high concentration (N+). Low concentration (N-) collector5. Base (P
)6. An emitter (N+) 7 is formed. In addition, 8
9 is a collector electrode, 9 is an emitter electrode, and 10 is a base electrode. As is well known, the embedded collector 4. Collector 5.
A channel region is formed by the base 6 and emitter 7, and a current flows, for example, in the direction of the arrow.

[Problem to be solved by the invention]

In the conventional example shown in FIG. 2, the N+ buried collector 4 extends below the collector electrode 8, and the contact interface between the N+ buried collector 4 and the N- collector 5 is large, and the concentration difference between them is reduced in this part. The capacitance formed by the transistor (collector capacitance) is large, which poses a problem that impedes high-speed transistor operation. Furthermore, the collector potential distribution becomes non-uniform due to the resistance of the buried collector 4, which also poses a problem in that high-speed transistor operation is hindered. In this case, it is conceivable to form the embedded collector 4 thickly in order to reduce the collector resistance, or there is a problem that the collector capacitance increases if this is done.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can reduce collector capacitance and increase speed, and a method for manufacturing the same.

[Means to solve the problem]

The above problem is solved by forming a first non-insulating region under the element active region, forming a second non-insulating region electrically connecting the first non-insulating region and the collector electrode, and The first and second non-insulating regions constitute a buried collector, and there is insulation between the portion of the second non-insulating region that does not contact the first non-insulating region and the non-insulating region forming the element active region. The problem is solved by a semiconductor device characterized by forming regions. Alternatively, a step of forming a non-insulating region on the substrate via an insulating region, and forming a non-insulating region on the non-insulating region at least in a portion corresponding to a portion that will become an element active region, and forming an insulating region in other portions. The problem is solved by a method for manufacturing a semiconductor device, which includes a step of bonding a semiconductor substrate other than the above-described substrate to the surface thereof.

[Effect]

In the present invention, the first non-insulating region is formed only under the element active region, and the second non-insulating region is insulated between a portion of the second non-insulating region that is not in contact with the first non-insulating region and the low concentration region. Since the contact area between the areas with a difference in concentration (the first non-insulated area and the low concentration area) is smaller than in the conventional example, the collector capacitance is reduced and the transistor operates at high speed. can be converted into

〔Example〕 FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention.

In the same figure (A), P<100>10Ω' cm
- A silicon oxide film 12 with a thickness of 1 μm is formed on the single crystal silicon substrate 11 by wet oxidation treatment at 1100°C, and a 130.5 μm N+ polycrystalline silicon pattern film with resistivity ρ5=10Ω10 is further formed on the surface. It is formed thick and doped with antimony (Sb). Next, CVD
A silicon oxide film 14 is formed to a thickness of 1 μm using a method, and a predetermined portion of the silicon oxide film 14 is patterned and removed to form a window 14a.
An N+ polycrystalline silicon pattern film 15 is buried in the window 14a to a thickness of 1 μm, the same as the silicon oxide film 14, and antimony is doped therein. Next, the surface is polished to leave the polycrystalline silicon film 15 only within the window 14a. The substrate manufactured through the above steps is referred to as the substrate 16.

On the other hand, an N-single-crystal silicon substrate 17 of N<100>10Ω' Cm with a thickness of 600 μm is prepared, the substrate 16 and the substrate 17 are bonded together as shown in the same figure (B), and the surface of the substrate 17 is polished. to a thickness of 0.5 μm. In this bonding step, an N+ collector diffusion layer 18 is formed on the single crystal silicon substrate 17 on the polycrystalline silicon film 15 by annealing performed to increase the bonding strength. N+ polycrystalline silicon pattern film 1315. The N+ collector diffusion layer 18 constitutes a buried collector. Next, in the same figure (B), an N-epitaxial layer (0.5 Ω·cm) 19 is grown on the surface of the substrate 17 to a thickness of 2 μm.

Next, in the same figure (C), a field oxide film 20 with a thickness of 0.5 μm is formed on the surface of the epitaxial layer 19,
Thereafter, a U-groove 21 reaching the polycrystalline silicon film 13 is formed, a silicon oxide film 22 is formed on the side, and the U-groove 21 is formed.
A polycrystalline silicon layer 23 is filled inside and N+ doping is performed. Next, Pace (P) 24. pace contact I
・Part (P") 25. Emitter (N") 26 is formed, collector electrode 27. Emitter electrode 28. A base electrode 29 is formed.

As is clear from the same figure (C), the N+ collector diffusion layer 18
is formed only under the element active region 30, and N+
Since the polycrystalline silicon pattern film 1513 is in contact with the silicon oxide film 14, as shown in FIG.
Compared to the conventional structure in which the buried collector 4 extends below the collector electrode 8 and the N+ buried collector 4 is in contact with the N- collector 5, there is a difference in concentration (N+ and N
-) The contact interface is small, thereby reducing the collector capacitance and increasing the speed of the transistor operation. or,
Since the N+ polycrystalline silicon pattern film 13 is used, the resistance can be lowered compared to the conventional example using the N+ buried collector 4 of single crystal silicon.This makes the collector potential distribution uniform, and from this point of view as well. )・Can speed up transistor operation.

〔Effect of the invention〕

As described above, according to the present invention, the contact interface at the portion with a concentration difference is smaller than that of the conventional example, thereby reducing the collector capacitance and increasing the speed of transistor operation.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention, and FIG. 2 is a structural diagram of a conventional example. In the figure, 11 is a P-single crystal silicon substrate (-conductive type semiconductor substrate)
, 12.14 is a silicon oxide film (insulating region), 13 is N+
+ crystalline silicon film (second non-insulating region), 15 is N++ crystal silicon film (first non-insulating region), 17 is N- single crystal silicon substrate (low concentration region), 18 is N+ collector diffusion layer (first non-insulating region). 1 (non-insulating region), 19 is an N-epitaxial layer (low concentration region), 23 is a polycrystalline silicon layer 24 is a base, 26 is an emitter, 27 is a collector electrode, and 30 is a device active region. (Second non-insulated area)

Claims (1)

[Claims] (1) SO formed with embedded collectors (13, 15)
In a semiconductor device having an I substrate, a first non-insulating region (15) is formed under the element active region (30), and the first non-insulating region (15) and the collector electrode (27) are electrically connected. a second non-insulated region (
13, 23), the first and second non-insulating regions constitute the buried collector (13, 15), and the second non-insulating region (13) includes the first non-insulating region (13); A portion not in contact with the region (15) and the element active region (30)
) and non-insulating regions (17, 19) forming an insulating region (14). (2) SO formed with embedded collectors (13, 15)
A method of manufacturing a semiconductor device having an I-substrate includes the steps of: forming a non-insulating region (13) on a substrate (11) via an insulating region (12); and forming at least an element active region on the non-insulating region (13). (
30) is the non-insulated area (15).
, and the other parts include a step of forming an insulating region (14), and a semiconductor substrate (17) different from the substrate (11) on the surface.
A method for manufacturing a semiconductor device, comprising the step of bonding.