JPS6163057A - Manufacture of misfet - Google Patents

Abstract

PURPOSE:To make an FET with no shortcircuit between electrodes and substrate while reducing parasitic resistance and capacity in source and drain regions by a method wherein these regions constituting a MISFET are encircled by insulating film to be buried in a semiconductor substrate at specific gap. CONSTITUTION:N type regions 2' and 21' are diffusion-formed at the ends of source and drain regions 11 to be formed on the surface layer of a P type Si substrate 1. Next recessions with specified depth and dimension exposing the regions 2' and 21' are made in the substrate 1 to bury N type conductors therein respectively as a source region and a drain region 11. Later a gate electrode 4 is mounted between the regions 2' and 21' through the intermediary of a gate film 51 and then field insulating films 7 covering the regions 11 and interlayer insulating film 5 covering overall surface are provided with openings to mount electrodes 7 and 6 on respective regions 11. Through these procedures, depletion layers 3' and 31' may be formed below the regions 2' and 21' to reduce the mutual conductance.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention reduces the resistance of source/drain regions, reduces the capacitance between the source/drain regions and a semiconductor substrate, and reduces the capacitance between an aluminum electrode and a semiconductor substrate. The present invention relates to an MI8FET designed to prevent short circuits and a method of manufacturing the same.

(Conventional technology) The conventional structure will be explained using FIG. 5.

For example, an n-channel MO8FET will be explained, but a p-channel MO8FET can be considered by replacing the n-type with the p-type and the p-type with the n-type of the conductive layer described below. FIG. 5 shows the Urrki in the channel direction. Conventionally, source/drain regions are formed in a p-type semiconductor substrate 1,
Using the gate electrode 4 as a mask, arsenic or phosphorus is ion-implanted to form an n-type source region 2 and drain region 21. In order to shorten the channel length of the MOSFET and reduce the short channel effect, regions 2 and 2 of the n-type layer
It is necessary to make the depth xj) shallow and to increase the concentration near the substrate surface where the channel is formed by doping the channel with poron.

(Problems to be Solved by the Invention) The above configuration causes the following problems. First, if the regions 2 and 21 of the n-type layer are made shallow, (1)
Since the sheet resistance of the n-type layer increases, the parasitic resistance R between the source and drain ends to the aluminum electrode 6 increases.
When is large, the mutual conductance (gm) of MO81+'ET decreases. (2) Due to the reaction between the aluminum electrode 6 and silicon), the reaction portion 8 of aluminum and silicon reaches the substrate, causing a problem that the aluminum electrode 6 and the substrate l are short-circuited. Furthermore, when the boron concentration near the substrate surface is increased, the widths of the depletion layers 3 and 31 formed between the n-type source region 2 and n-type drain region 21 and the substrate, respectively, decrease, and the nitrogen depletion layer capacity ψC, , a , becomes large. In Figure R, 5 is the insulating film between the eyebrows.

7 is a field insulating film, and 51 is a gate oxide film.

(Means for Solving the Problems) The present invention was proposed to solve these problems.
Surround the drain region with an insulator.

It is characterized by being buried in the substrate, and its purpose is to reduce source/drain parasitic resistance, reduce source/drain parasitic capacitance, and prevent aluminum from penetrating into the substrate.

In order to achieve the above object, the present invention provides that the main source/drain regions are formed of a conductor embedded in a semiconductor substrate, and that the conductor and the semiconductor substrate, except for the vicinity of the source end and the drain end, are formed by a conductor embedded in a semiconductor substrate. An insulator is formed between -
The gist of the invention is an M-type 9FET characterized by the following characteristics.

Furthermore, the present invention 16. A step of etching the surface of the semiconductor substrate where the source/drain regions of M1378 are formed to form a recess, a step of forming an insulator on the surface of the recess, and a step of forming the insulator near the source end and the drain end of the channel. The gist of the invention is a method for manufacturing an M-type 5FET, which is characterized by comprising a step of removing the body and a step of filling the recess with a conductor.

Next, the present invention will be explained in detail. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

The first embodiment of the present invention is applied to an n-channel MO8FET.
This will be explained in detail using FIGS.

(Embodiment 1) Figure 1 shows the first embodiment of the present invention.
are p-type semiconductor substrates, 2' and 21' are n-type layers near the source and drain ends, respectively, 3' and 31' are depletion layers formed at the source and drain ends (supports), 4 is a gate electrode, and 5 is an insulating film between the eyebrows, 6 is an aluminum electrode,
7 is a field insulating film, 9 is an insulating film formed between the source and drain regions and the substrate, 10 is a window opened in the insulating film 9 near the source end and the drain end, and a conductor filled with 121N. That is, in the figure, an insulating film 9 is formed in a p-type semiconductor substrate l so as to sandwich a source region and a drain region, a conductor 11 is formed in each insulating film 9, and the two insulating films 9 are opposite to each other. There is a window at the top of the side
n-type layers 2', 21' are formed in this window portion, and gate oxide M5N is formed by removing these n-type layers 2', 21'. Further, a gate electrode 4 is formed on the center upper edge of this gate oxide film. An interlayer fiM5 is formed covering the gate electrode and source/drain regions. The aluminum two poles 6 are lead terminals for the source and drain regions, respectively. With this structure, the IF raw resistance R' can be reduced by increasing the depth Xj of the recess and reducing the resistivity of the conductor 11, and by increasing the thickness of the insulating film 9. By doing so, the parasitic capacitance of the source and drain can be reduced. A short circuit between the aluminum electrode and the substrate does not occur because the insulating film 9 is formed.

(Implementation?! 12) FIG. 2 shows a second embodiment of the present invention. Except for the channel doped layer 12, the numbering of each layer is the same as in FIG. 1, so a description thereof will be omitted. When the channel doped layer 12 is formed only in the center of the channel, the MO8F]1fiT characteristics are determined by the width L' of this channel doped layer and are almost independent of the distance between the source and drain, so even if the channel length is long, the transconductance remains constant. can be made larger. Further, since the substrate concentration near the source end and drain end is low, the drain breakdown voltage is also improved. It goes without saying that channel doping may be performed by a combination of deep ion implantation and shallow ion implantation.

(Example 3) Next, MO8F1 of the present invention! ! An example of a manufacturing method for realizing T will be described with reference to FIGS. 3(h) to (Q,).

A laminated film A consisting of a pad oxide film 40 of 300X to toooX, a silicon nitride film 41 of 100OX to 200X, and a phosphosilicate glass film (hereinafter referred to as PS() film) 42 of 1000 to 2000 A is formed on the surface of a p-type silicon substrate. Then, using the stamped resist film 43 as a mask, the laminated film A is etched and removed. CF4 etching
Processing without side etching can be achieved by a reactive ion etching method (hereinafter referred to as RIM method) using gas, H, and gas. Thereafter, a region 44 with a high boron concentration is formed on the substrate surface by implanting boron ions for channel stop (FIG. 3A). Thereafter, the resist film 43 is removed and a RO000A-1,2μ
A field insulating film 7 having a thickness of m is formed. A channel stop region 44' is formed under the field insulating film 7 (FIG. 3B).

Next, using the resist arm 4a' patterned to be about 0.2μ thinner on one side than the gate electrode as a mask, the product remaining on the active region is measured. The i-film A is removed by etching, and the exposed silicon substrate is further etched by about 0.3 μm by RIE using aC gas to form a recess 45 (FIG. 3C).

Next, the resist film 43' is removed, and a silicon oxide film 46 of approximately 30 OA is formed on the silicon surface layer of the recess by thermal oxidation, and then silicon oxide is further formed on the silicon oxide film 46 by chemical vapor deposition (hereinafter referred to as CVD method). Forming a film 47 (FIG. 3D)
.

After that, a resist film 43 is battened to cover the side surface of the MO8FICT on which the channel will be formed.
Using this as a mask, the silicon nitride film 47 is etched by an isodirectional plasma etching method using CF4 gas (FIG. 3E).

Next, the resist film 43' is removed, and the silicon nitride film 47 on the bottom of the recess and the surface of the laminated film A is removed by RIE (FIG. 3F). A plan view in this state is shown in FIG. 3G. The silicon nitride film 47 also remains on the side surfaces parallel to the channel direction of the recess that were covered with the resist film 43'.

Next, the silicon substrate is further etched by the RIE method described above using the silicon oxide film 46, silicon nitride film 47, and field insulating group 7 remaining on the side surfaces of the laminated film A and the recess as masks, and the recess is approximately 0.6 μm deep. form 45' (
Figure 3H).

Next, the silicon surface of the concave portion that is not covered with the silicon nitride film 47 is thermally oxidized at a fi of 2000 to 3000.
Form a silicon oxide film 48 (a! 3)
.

Thereafter, the silicon nitride film 47 is etched with a hot phosphoric acid solution of 160 Cj -180'C, and then PS (
) Etching the film 42 with a hydrofluoric acid solution. At this time, the silicon oxide film 46 is also etched at the same time (FIG. 3J).

Next, a polycrystalline silicon film doped with phosphorus at a degree of C of approximately 2 x 10"7cm" is formed by CVD, and polycrystalline silicon f, H, s is added only in the concave portions by an etch-back method.
Leave 9. Apply silicone film to the recess! In addition to this, a bias sputtering method may be used as a method for depositing the film. Alternatively, phosphorus may be added after a silicon film is dug into the recess. Furthermore, arsenic may be added instead of phosphorus. Phosphorus is thermally diffused from the embedded silicon film to form an n-type layer 2',
21' (Fig. 3K).

Next, the upper surface of the silicon film 49 is thermally oxidized to a temperature of 1500 K.
A silicon oxide film 50 of ~2500^ is formed (FIG. 3L).

Subsequently, the silicon nitride film 41 is etched using the aforementioned hot phosphoric acid, and the pad oxide film 40 is further etched using a hydrofluoric acid solution. Then, a gate oxide film 451 is formed, and boron ions are implanted to form a channel doped layer 52 (FIG. 3M).

Thereafter, the gate oxide film 51° gate electrode 4. After forming the interlayer insulating film 5 and forming the contact holes, an aluminum electrode 6 is formed (FIG. 3N).
.

(Example 4) Next, an example of a manufacturing method in which a channel doped layer is formed only in the center of the channel region will be described.

After the process shown in FIG. 3 described in implementation ylJ3, tungsten #1 is deposited on each crystalline silicon film 49 using WF and gas.
53 to approximately 5000λ (FIG. 4A).

After that, a fi PSG film is formed by CVD method, and OF4
PSAB is etch-packed by RIE using gas and H2 gas, and P8 is applied only to the side area of the tungsten film 53.
The G film 42' is left. Boron ions are then implanted using the PSG film 42' as a mask to form the channel doped layer 12 only in the center of the channel region. Poron ion magnificence may be performed several times by changing the implantation energy (Fig. 4B)
).

Thereafter, the PBCk film 42' is etched using a hydrofluoric acid solution, and the tungsten 853 is further etched using a mixed solution of sulfuric acid and hydrogen peroxide. The subsequent steps are the same as those described in Example 3 from FIG. 3(L) onwards, and will therefore be omitted.

(Effects of the Invention) As explained above, according to the present invention, the main source/drain regions are surrounded by an insulator and deeply buried in the semiconductor substrate, so that the parasitic resistance and capacitance of the source/drain are small. , and there is no short termination between the aluminum electrode and the semiconductor substrate, making it a high-speed and highly reliable MOBFE.
It has the advantage that T can be realized.

In addition, by forming the channel doped layer only in the center of the channel region, the effective channel length is not defined by the gate length and source/drain junction depth as in conventional MOBFETs, and the channel doped layer is Since the effective channel length is determined by the width of the high concentration region, a high gain MOBFET can be realized even if a loose batten rule is used. Further, in this case, since the substrate concentration near the drain is low, the drain breakdown voltage is also improved, and there is also an advantage that the stability of the MOBFET is less likely to deteriorate due to hot electrons.

Although the above explanation is about MO8F3CT, it goes without saying that it can be broadly applied to M5FET as well.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a second embodiment of the present invention.
implementation? 3 is a sectional view of the third embodiment, FIG. 4 is a sectional view of the fourth embodiment, and FIG. 5 is a conventional MOBFE.
A cross-sectional view of T in the channel direction is shown.

Claims (4)

[Claims] (1) The main source/drain regions are formed by a conductor embedded in a semiconductor substrate, and an insulator is formed between the conductor and the semiconductor substrate except near the source end and drain end. MISIF characterized by
E.T. (2) The MISFET according to claim 1, wherein a channel doped layer is formed only in the center of the channel region. (3) A step of etching the surface of the semiconductor substrate where the source/drain regions of the MISFET will be formed to form a recess, a step of forming an insulator on the surface of the recess, and a step of forming a recess near the source end and a drain end of the channel. A method for manufacturing a MISFET, comprising the steps of removing the insulator and filling the recess with a conductor. (4) A step of etching the surface of the semiconductor substrate where the source/drain regions of the MISFET will be formed to form a recess, a step of forming an insulator on the surface of the recess, and a step of forming a recess near the source end and a drain end of the channel. a step of removing the insulator; a step of filling the recess with a conductor; a step of selectively forming a first thin film only on the conductor; and channel doping only on the side surfaces of the thin film. Manufacturing a MISFET according to claim 3, comprising the steps of forming a second thin film leaving a gap, and performing channel doping using the first and second thin films as masks. Method.