JPS6041876B2 - Manufacturing method of insulated gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-output insulated gate field effect transistor (hereinafter referred to as MOSFET).

Traditionally, the output of MOSFETs, in particular the current, has been increased. In the figure, 1 is a drain substrate, 2 is a channel substrate,
3 is a drain region, 4 is a source region, 5 is a gate electrode,
6 is a silicon oxide film for a gate; 7, 8, and 9 are source, drain, and gate extraction electrodes, respectively; and 10 is a protective insulating film. A feature of this structure is that the electrode of the drain region 3 is taken out from the back surface of the drain substrate 1, and current can flow from the front surface to the back surface of the device.

As a result, compared to a normal MOSFET where the source and drain electrodes are placed on the same surface of the device,
Current can be easily taken out, and the effective channel area (width) can be increased with the same chip size, making it suitable as a large current device. Furthermore, as an element with an improved structure, as shown in FIG.
It has been proposed to provide a low concentration impurity layer 11 of the same conductivity type.

This is effective for improving the punch-through breakdown voltage between the source region 4 and the drain substrate 1 when the depth of the drain region 3 is limited due to the degree of integration or the like. - 1 However, in MOSFETs with the above structure, 2, 3 and 1
The region 1 is a layer (Ep layer) usually formed by epitaxial vapor growth, and has a structure in which the drain electric field is particularly concentrated at the boundary between the Ep layer 2 and the drain substrate 1 or the low impurity concentration layer 11. Therefore, the yield of drain breakdown voltage was low.

The reason for this is that crystal defects are likely to occur during the formation of the Ep layer, particularly at the initial stage of its formation. Therefore, as the chip area increases, the Ep
As the number of growth increases, the yield tends to decrease significantly. As mentioned above, Figures 1 and 2
The MOSFET shown in the figure has a drawback of low voltage yield. An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a method for manufacturing a MOSFET with good voltage resistance yield.

In order to achieve the above object, a MOSFET is manufactured in which a channel region is formed near the surface of a drain substrate by ion implantation or diffusion, and a portion of the substrate extends to the surface of the substrate as a drain region. Suggest a method.

Hereinafter, the present invention will be explained in detail using examples.

FIG. 3 shows a cross-sectional view of an embodiment of a MOSFET obtained by the present invention.

For example, the drain substrate 1 is of P type and has an acceptor impurity concentration NA of 1×1015 cm4, and the channel substrate 2 is of N type and has a donor impurity concentration ND of 3015 cm4.
-3, its thickness is 10 μm.

The drain region 3 is of P type and has a surface impurity concentration NA of 1.
01'7 cm-3, 1.5 μm deep, and 1 drain group. The plate is connected to the surface of the substrate, and taken out from the back electrode 8. The source region 4 is P type and has an impurity concentration NA
is 1019 cm-3 or more and is taken out from the surface source electrode 7. 5 is a gate electrode, 6 is an insulating film for gate,
9 is an extraction electrode of the gate electrode 5. Ru.

In the above structure, it is important that the channel region 2 and the drain region 3 are formed by ion implantation, diffusion, or a combination thereof, and do not use E-growth.

As a result, Chippsa is 5? It has now become possible to manufacture power MOSFETs with a withstand voltage of 100 µm and a current of 10 A with a yield of over 50%. Note that the breakdown voltage yield of MOFET using conventional Ep growth was about 10%.
Furthermore, in the structure of FIG. 3, the value of the impurity concentration NA on the surface of the drain region 3 is 1017C77! -3 or less is useful for increasing the breakdown voltage of the MOSFET. Next, the MO obtained by another embodiment according to the present invention
SEFT will be explained using FIG. 4. In this case, instead of the drain substrate 1 shown in FIG. 3, a substrate having a high concentration drain substrate 1 and a low impurity concentration layer 11 formed thereon is used, and in the low impurity concentration layer 11, the drain substrate 1 shown in FIG. A channel substrate 2, a drain region 3, and a source region 4 are formed in the same manner as in FIG. Here, the drain substrate 1 is, for example, of P type and has an impurity concentration NA of 5×10 18c.
jn-3, the low impurity concentration layer 11 is of P type and has an impurity concentration NA of 1015cTt-3. In this case, low impurity.
Even if the impurity concentration layer 11 is Ep, the boundary between the channel substrate 2 and the low impurity concentration layer 11 is a junction formed by ion implantation, diffusion, or a combination thereof, so there are few crystal defects. The yield of drain breakdown voltage was improved, and according to experiments, it was significantly improved compared to the two-layer Ep structure shown in FIG. 2, as in the case of FIG. 3. Next, the manufacturing process of an N-channel MOSFET according to an embodiment of the present invention will be explained using FIG. 5A-1.

A thermal oxide film 17 is deposited at approximately 6000 Å on the surface of a P-type silicon substrate 1 with an acceptor impurity concentration NA of 1015 cm-3.
After selectively removing the thermal oxide film 17 on the channel substrate formation region of the substrate 1 (FIG. A), the sample is irradiated with phosphorus ions 12.

The ion implantation energy E was 50 ke and the implantation amount NDT was 5 x 1013 cm-3. After ion implantation, heat treatment was performed at 1200'C for 3 hours in humidified oxygen. As a result, an N-type doped layer that would become the channel substrate 2 was formed with a depth of 8 μm. At this time, a thin thermal oxide film 17'' is again formed on the channel substrate 2 (Figure B).Next, a predetermined portion of the thermal oxide film 17'' is selectively removed, and the film is heated at 1050'C through this window. , high impurity concentration region 1 for substrate contact is performed by performing high concentration phosphorus diffusion using POCl3.
3 was formed. At this time as well, a thin oxide film is formed on the window portion (Figure C). Next, the oxide film on the surface is selectively removed leaving a predetermined portion, and then thermally oxidized to form a gate insulating oxide film 6 with a thickness of about 1000 Å. At this time, the remaining portion 19 of the oxide film becomes thicker. A polycrystalline silicon film 5'' is formed thereon to a thickness of approximately 5000A (Figure D), and at this time, the silicon film 5'' is selectively removed to form a gate electrode 5.
After forming, the sample is irradiated with boron ions 14. The energy E of this ion is Kevl implantation amount NDT is 4×
1012c1n-3. As a result, a drain region 3 with a low impurity concentration, which is useful for increasing the breakdown voltage of the MOSFET, is formed between the gate electrodes 5, and a region 4'' with a similar concentration is formed around the high impurity concentration region 13 (FIG. E). continuation,
A silicon oxide film 16 with a thickness of about 4000 A is formed thereon by CVD (chemical vapor deposition), the oxide film 16 on the region 4'' is selectively removed, and boron is diffused using this as a window. The source region 4 has a surface impurity concentration NA of 10
19crft-3 or more and a depth of 1.5 μm (
Figure F). Next, a phosphorus glass film 10 with a phosphorus molar concentration ratio of 4 mol % is formed on the entire surface to a thickness of approximately 9,000 mm using the CVD method, and after heat treatment in nitrogen at 1,050° C. for 5 hours, the electrode is heated. Holes for contacts were etched (Figure G)
). After that, aluminum is vacuum-deposited on the entire surface.
After depositing to a thickness of about 1.5 μm, a source electrode 7 and a gate lead-out electrode (not shown) were formed by etching (Figure H). After completing the above steps, the back surface of the substrate 1 was removed by etching to a thickness of 100 PTL, and then gold was formed to a thickness of 2000 A by vacuum evaporation and alloyed at 400° C. to form the drain 5 electrode 8 (Fig. 1 ). During this process, (
Although the N-type high impurity concentration region 13 shown in FIG.
It is effective for establishing an ohmic connection with the board 1,
As a result, the substrate 1 and the source region are completely electrically connected, and the stability of the MOSFET characteristics is greatly improved. Furthermore, other manufacturing steps for the P-channel MOSFET according to the present invention are shown in FIGS. 6A-D.

A thermal oxide film 17 is formed on one surface of an N-type silicon substrate 1 with a donor impurity concentration ND of 2×10 15 cm −3 at a thickness of approximately 6000 Å.
After selectively removing a predetermined portion leaving a predetermined portion, the sample is irradiated with boron ions 12.

The implantation energy E of this ion is 100keV1 implantation 4
The amount NDT was about 1013 cm-3. After ion implantation, heat treatment was performed at 1200° C. for 16 hours in dry oxygen. As a result, a P-type doped layer, which will become the channel substrate 2, was formed to a depth of 6 μm (Figure A). Next, the oxide film is selectively removed and thermally oxidized to form a gate insulating oxide film 18 having a thickness of about 1300 Å. The remaining portion 19 of the oxide film becomes that much thicker. Furthermore, a polycrystalline silicon film 5'' is formed to a thickness of approximately 5000A on the oxide film (Figure B).
), this silicon film 5'' is selectively removed to form the gate electrode 5, and then the sample is irradiated with phosphorus ions 14.The ion implantation energy E is 50 keV1 the implantation amount N
. It was set as T2×1014crf1-3. As a result, drain region 3 and region 4'' with low impurity concentration l are formed (Figure C).
A silicon oxide film 16 is formed to a thickness of 00A, a window is formed in the silicon oxide films 16 and 18 that reaches the surface of the central part of the region 4'', and N reaches the channel substrate 2 by boron diffusion.
A type high impurity concentration region 13 is formed. At this time, a thin oxide film is formed on region 13 (FIG. D). Next, the oxide film 18 is removed by etching, and C is deposited on the entire surface of the sample.
After covering the silicon oxide film 16 by the VD method, a window is opened in the oxide film 16 that passes through the region 4'', and phosphorus is diffused through this window to form the source region 4 (Figure E).
After removing the oxide film on the sample surface by etching, the sample surface is lightly oxidized, a phosphorus glass film 10 is deposited on the entire surface, and a high impurity region 13 is formed on the phosphorus glass film 10 and the oxide film below it.
After opening a window reaching the source region 4 and the gate electrode (Figure F) and vacuum-depositing aluminum over the entire surface of the sample,
A resource electrode 7 and a gate lead-out electrode (not shown) were formed by etching, and then, after etching the surface of the substrate 1, a drain lead-out electrode 8 was formed by vacuum deposition (Figure G). In this way, a MOSFET having a structure similar to that shown in FIG. 5 is obtained. Furthermore, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the technical idea of the present invention. As is clear from the above explanation, according to the present invention, MOSFETs with good characteristics can be manufactured at a high yield.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views of conventional MOSFETs,
3 and 4 are cross-sectional views of a MOSFET according to the present invention, and FIGS. 5 and 6 are cross-sectional views of a MOSFET according to the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of the FET. In the figure, 1... drain substrate, 2...
...Channel substrate, 3...Drain region, 4.
...Source region, 5...Gate electrode, 6
...Silicon oxide film for gate, 7, 8, 9...
...Extraction electrode, 10...Protective insulating film, 1
1...Low impurity concentration layer, 12, 14...Ion beam, 13...High impurity concentration region, 16
, 17, 18... Silicon oxide film.

Claims (1)

[Scope of Claims] 1. A method for manufacturing an insulated gate field effect transistor, comprising the following steps. (i) a second conductivity type in a predetermined surface area of the semiconductor substrate of the first conductivity type;
forming a conductive type semiconductor region, (ii) the second
(iii) forming a gate electrode at a predetermined position on the surface of the semiconductor region of the conductivity type via an insulating film; (iii) using the gate electrode as a mask, the surface region of the semiconductor substrate of the first conductivity type and the second conductivity type; (iv) forming a first impurity region of the first conductivity type in the semiconductor region of the second conductivity type by ion implantation across the surface region of the semiconductor region; (v) forming a source electrode (or drain electrode) on the second impurity region; (vi) forming a drain electrode (or source electrode) on the back surface of the semiconductor substrate. The process of doing.