JPS6135710B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having an improved structure, and more particularly to a method of manufacturing a semiconductor device including an improved semiconductor memory device.

The present applicant previously proposed a new method for manufacturing a semiconductor memory in the specification of Patent Application No. 84833 (filing date: July 14, 1972). The device according to the proposed manufacturing method includes a first gate insulating film on the main plane of a predetermined semiconductor substrate, a floating gate electrode made of a conductor or a semiconductor on top of this, a second gate insulating film on top of this, and a floating gate electrode made of a conductor or semiconductor on top of this. It has an external gate electrode made of a conductor or a semiconductor on top, and the floating gate electrode is shaped in a self-aligned manner with respect to the external gate electrode, and is self-aligned with both the external gate electrode and the floating gate electrode. a region near the surface of the substrate doped with an impurity of the same type as the substrate and at a higher concentration; a pair of sources having opposite conductivity types; It has a drain region. With a structure such as that described above, various favorable results are obtained since the seemingly mutually contradictory requirements of high conductance and small device size of the memory transistor are successfully achieved compared to previous similar memory devices. However, even though the invention of the above-mentioned application has various excellent properties, there is still room for improvement.

An object of the present invention is to significantly reduce the device size and to obtain particularly favorable properties in terms of integration, manufacturing yield, reliability, etc., without impairing the various advantages of the semiconductor memory according to the above-mentioned application. An object of the present invention is to provide a method for manufacturing a semiconductor device equipped with the above.

A feature of the present invention is that at least one pair of source and drain regions having conductivity types opposite to the substrate are provided near the surface of the semiconductor substrate at a distance from each other, and the substrate is in contact with at least one of the two regions. a region doped with impurities of the same type and higher concentration than the substrate; a first gate insulating film on the surface of the substrate between the source and drain regions;
a floating gate electrode made of a conductor or semiconductor on the first gate insulating film; and a second floating gate electrode on the floating gate electrode.
A semiconductor memory comprising a gate insulating film and a control gate electrode made of a conductor or semiconductor on the second gate insulating film is provided in at least a part of the active region, and In a method of manufacturing a semiconductor device having a field insulating film thicker than a first gate insulating film, a material for forming the first gate insulating film and the floating gate electrode are formed on the active region of the semiconductor substrate. forming the thick field insulating film by laminating a material and a silicon nitride film and performing thermal oxidation using the silicon nitride film as a mask, and forming the second gate insulating film on the thick field insulating film. forming the control gate electrode over the material forming the floating gate electrode on the active region through a material that forms the floating gate electrode; and forming the second gate insulator using the control gate electrode and the thick field insulating film as a mask. forming the shape of the floating gate electrode in a self-aligned manner with respect to the control gate electrode by sequentially selectively removing a material forming the film and a material forming the floating gate electrode; and forming the highly-concentrated impurity doped region by introducing impurities of the same type as the substrate into the active region of the semiconductor substrate using the structure having the floating gate electrode as part of a mask; and forming the source and drain regions by introducing impurities of a conductivity type opposite to that of the substrate into the active region of the semiconductor substrate using the thick field insulating film as a mask, thereby increasing the width of the floating gate electrode. , the width of the channel region and the width of the portion of the source and drain regions in contact with the channel region are substantially the same in planar shape, and
These end portions in the width direction substantially coincide with a part of the end portion of the field insulating film in plan view, and the control gate electrode extends from above the field insulating film onto the second gate insulating film, and the ends of the channel region of the floating gate electrode in the length direction and the ends of the source and drain regions in contact with the channel region substantially match the edge of the control gate electrode in plan shape, and have the same shape as the substrate. The present invention is also a method of manufacturing a semiconductor device for forming a semiconductor memory device in which a region doped with impurities at a higher concentration than a substrate is island-shaped and is formed almost entirely inside an element region.

The novel method for manufacturing a semiconductor device of the present invention enables a significant reduction in device dimensions;
In particular, an integrated circuit to which this device is applied can be stably and easily realized with a small chip area, high manufacturing yield, and high reliability. This is because in the device of the present invention, the dimensions of the floating gate electrode are minimized by introducing a new device structure, and special attention must be paid to this point.

Next, in order to make the features of the present invention easier to understand, several embodiments will be described in detail with reference to the drawings.

(Example 1): FIG. 1 is a plan view model diagram of a semiconductor memory device obtained by a manufacturing method according to an embodiment of the present invention, and FIG.
~N is a cross-sectional model diagram at various manufacturing steps along the a-a' cross section in Figure 1, and Figures 3 A-I are cross-sectional models at various manufacturing steps at the b-b' cross section in Figure 1. 4A, B, C, and D are plan view diagrams showing various manufacturing steps in FIG. 1. In these figures, identical parts of the device are designated with identical numbers. In FIG. 2A, a SiO ₂ film 3 with a thickness of about 1000 Å is grown on the main surface 2 of a P-type Si semiconductor 1 with a specific resistance of about 100 Ω-cm by thermal oxidation, and then N ₂ of SiH ₄ is grown on this film. PolySi film 4 with a thickness of about 2000 Å is formed by thermal decomposition inside
approximately 1000 Å thick by SiH ₄ + NH ₃ based vapor phase growth method.
Si ₃ N ₄ films 5 were sequentially formed. Next, Figure 2 B, 3
In Figures A and 4A, parts of the films 3, 4, and 5 are selectively removed using standard photolithography (PR) technology, and in Figures 2C and 3B, a thermal oxidation method at high temperature is used to prevent oxidation. Using the Si ₃ N ₄ film 5 as a mask, a thick field SiO ₂ 6 of about 1 μm was selectively grown. Next, Figure 2D,
In FIG. 3C, after removing the Si ₃ N ₄ film 5, a SiO ₂ film 7 with a thickness of about 1000 Å is grown on the PolySi film 4 by thermal oxidation, and in FIGS. 2E and 3D, SiH ₄ is grown. A PolySi film 8 having a thickness of about 0.5 μm was formed by thermal decomposition in N ₂ . Next, in FIG. 2F, FIG. 3E, and FIG. 4B, the poly.Si film 8 is patterned using standard PR technology, and in FIG. 2G, the poly.Si film 8 whose shape has been determined is
The portions of the SiO ₂ film 7, the Poly.Si film 4, and the SiO ₂ film 3 that were not covered were sequentially and selectively removed to expose a part of the substrate surface. Next, in Figure 2 H, the standard
After covering a part of the exposed substrate surface with a resist film 9 using the PR technique and selectively drilling holes, energy E is emitted from the exposed substrate surface in FIGS.
After boron ion implantation at a dose of =50Kev φ=4×10 ¹³ , the resist film 9 was removed and the temperature was 1100°C and N ₂
The P.sup ^.+ type region 10 was formed in a self-aligned manner on both the Poly.Si films 4 and 8 by pressing for 3 hours. Next, in Figure 2 J, phosphorus is diffused from the exposed substrate surface,
N ⁺ type regions 11 and 12 were formed. Not only are the N ⁺ type regions 11 and 12 self-aligned with the Poly.Si films 4 and 8, but the region 12 is also positioned self-aligned with the P ⁺ type region 10. . Next, in Figure 2 K and Figure 3 F, the thickness is approximately 1μ on the entire surface.
Contact holes 14 _, 15, 1 are formed in the SiO ₂ film 13 using standard PR technology as shown in FIG. 2L, FIG. 3G, and FIG. 4D.
6, and in FIGS. 2M and 3H, an AI film 17 having a thickness of about 1 μm was deposited on the entire surface by vacuum evaporation.
In FIGS. 2N and 3I, the AI film 17 was patterned using standard PR technology to form extraction electrodes 18, 19, and 20, and the installation was completed.
In these drawings, the N ⁺ type region 11,
12 is the source region, SiO ₂ film 3 is the first gate insulating film, poly.Si film 4 is the floating gate electrode, SiO ₂
The film 7 serves as a second gate insulating film, the Poly.Si film 8 serves as a control gate electrode, and the Al films 18, 19, and 20 serve as source, drain, and control gate extraction electrodes, respectively. In this memory device, the initial threshold voltage seen from the control gate lead-out electrode 20 at the manufacturing stage is about 2V. For example, if 25V is applied to the control gate extraction electrode 20 and 10V is applied to the drain extraction electrode 19 with the source extraction electrode 18 grounded, electrons accelerated by the electric field in the channel and become hot will float in the so-called channel injection mode. The threshold voltage injected into the gate electrode 4 is shifted to about 10V, thus writing takes place. Erasing in this memory device can be done either optically or electrically. Optical erasure is performed at wavelength λ = 2500 Å, for example.
This is done by irradiating a certain amount of ultraviolet rays to excite the energy of the injected electrons in the floating gate electrode and emit them to the substrate, thereby returning the threshold voltage to its initial value. Electrical erasing can be achieved by, for example, grounding the control gate lead-out electrode 20 or setting it to a negative potential, and applying a positive high voltage to the source lead-out electrode 18 to break down the PN junction between the source region 11 and the substrate 1. Of the hot electron-hole pairs generated at the time, only the holes are selectively injected into the floating gate electrode 4 depending on the direction of the electric field existing in the first gate SiO ₂ film 3, and the negative charge of the already injected electrons is removed. This is done by canceling and returning the threshold voltage to its initial value. In the semiconductor device of this example, as clearly shown in FIG.
The shape of the floating gate electrode 4 is determined in a self-aligned manner with the control gate electrode 8 along the a-a' direction, and with the thick field insulating film part along the b-b' direction, and its dimensions are determined. I understand that it is the minimum necessary. Therefore, for example, this semiconductor device can be applied to create a PROM (programmable memory) with a large storage capacity.
When realizing ICs such as Read Only Memory (Read Only Memory), the floating gate electrode is not a limiting factor in device size at all, and the maximum degree of integration is achieved.

(Embodiment 2): FIG. 5 is a plan view showing another example of the semiconductor device of the present invention. In comparison with FIG. 1, the same device parts are given the same numbers. In the device shown in FIG. 5, the high concentration region 10 of the same type as the substrate is formed not only with respect to the drain region 12 but also with the source region 11 in a self-aligned manner.

(Embodiment 3): FIG. 6 is a plan view showing still another example of the semiconductor device of the present invention. In this device, the floating gate electrode 4 is formed in self-alignment with respect to the thick field insulating film portion, but is formed in self-alignment with respect to the control gate electrode 8 only on the drain side.

It is clear from the above description that the several embodiments described above are merely for illustrative purposes and the present invention is not limited thereto. For example, it is possible to change the material, dimensions, and manufacturing method of each part of the device, and it is also possible to change the conductivity type and type of impurity.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a first embodiment of the semiconductor device of the present invention. Figures 2A to 2N are cross-sectional model views taken along cutting line a-a' in Figure 1 and viewed in the direction of the arrow, showing the manufacturing process of the first embodiment in the order of steps. It is something. Figure 3 A to 3
Figure I is a cross-sectional model diagram of Figure 1 taken along cutting line b-b' and viewed in the direction of the arrow, and Figure 2 is a cross-sectional model diagram of B, C, D, E, F, K, L, M, respectively. and N are shown corresponding to the manufacturing process. Figure 4 A, B, C and D are respectively Figure 2 B, F, I
and FIG. 4 is a plan view showing the manufacturing process of L. FIG. 5 and FIG. 6 are plan model views showing a second embodiment and a third embodiment of the present invention, respectively. In the figure, 1...P-type Si semiconductor, 2...
Main surface of 1, 3, 7... gate SiO ₂ film, 4...
Floating gate electrode, 5... Si ₃ N ₄ film, 6... Field SiO ₂ film, 8... Control gate electrode, 9... Photoresist film, 10... P ⁺ type region, 11, 1
2... Source, drain N ⁺ type region, 13... SiO ₂ film containing phosphorus, 14, 15, 16... Contact hole, 17... Al vapor deposited film, 18, 19, 2
0... Source, drain, control gate extraction electrode.

Claims (1)

[Claims] 1 At least one pair of source and drain regions having conductivity types opposite to that of the substrate, provided near the surface of the semiconductor substrate at a distance from each other; a first gate insulating film on the substrate surface between the source and drain regions; a floating gate electrode made of a conductor or a semiconductor on the first gate insulating film; and a floating gate electrode on the floating gate electrode. A semiconductor memory comprising a second gate insulating film and a control gate electrode made of a conductor or semiconductor on the second gate insulating film is provided in at least a part of the active region, and In the method of manufacturing a semiconductor device having a field insulating film thicker than the first gate insulating film, a material for forming the first gate insulating film on the active region of the semiconductor substrate, a material for forming the first gate insulating film on the active region of the semiconductor substrate, and the floating gate. forming the thick field insulating film by laminating a material for forming an electrode and a silicon nitride film and performing thermal oxidation using the silicon nitride film as a mask; and depositing the second gate insulating film on the thick field insulating film. shaping the control gate electrode over the material forming the floating gate electrode on the active region through a material forming the film; and using the control gate electrode and the thick field insulating film as a mask. forming the shape of the floating gate electrode in a self-aligned manner with respect to the control gate electrode by sequentially selectively removing the material forming the gate insulating film and the material forming the floating gate electrode; forming the highly doped region by introducing impurities of the same type as the substrate into the active region of the semiconductor substrate using the control gate electrode and the gate structure having the floating gate electrode as part of a mask; forming the source and drain regions by introducing impurities of a conductivity type opposite to that of the substrate into the active region of the semiconductor substrate using the gate structure and the thick field insulating film as a mask; The width of the gate electrode, the width of the channel region, the source,
The widths of the portions of the drain region in contact with the channel region are substantially the same in plan view, and the ends of these widths are substantially the same as part of the end portions of the field insulating film in plan view, and extends from above the field insulating film onto the second gate insulating film, and the lengthwise ends of the channel region of the floating gate electrode and the ends of the source and drain regions in contact with the channel region are connected to the second gate insulating film. A semiconductor memory device in which the planar shape of the control gate electrode substantially coincides with the edge of the control gate electrode, the region having the same shape as the substrate and doped with impurities at a higher concentration than the substrate is island-shaped and is formed almost entirely inside the element region. 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device.