JP2956143B2 - Method of manufacturing insulated gate field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing an insulated gate field effect transistor suitable for forming an VLSI (Large Scale Integrated Circuit).

[Related Art] Insulated gate field effect transistors (hereinafter referred to as MISFETs) used in VLSIs tend to have shorter channels as semiconductor devices become more highly integrated.

Conventionally, in the case of a MISFET having a channel length of about 1 μm, a so-called LDD (Lightly-Diffused) in which a low-concentration source / drain region is disposed between a high-concentration source / drain region and a channel region.
By adopting a Doped Drain (Drain) structure, the withstand voltage characteristics are improved and the operation speed is increased. However, in a MISFET having a much shorter channel length of about 0.5 μm, a sufficient breakdown voltage characteristic and high speed cannot be obtained with the conventional LDD structure. For this reason, MISFETs suitable for shortening the channel have been proposed. "High voltage, high speed 5V operation submicron device GOLD", p. 31-36, IEICE Technical Report (SD
M87-157), published in 1988.

FIG. 3 is a cross-sectional view showing a MISFET suitable for shortening the channel described above.

On the surface of the semiconductor substrate 11, a pair of n ⁺ layers 19 into which n-type impurities are introduced at a high concentration are formed at an appropriate interval from each other. At the end of each n ⁺ layer 19 on the side facing each other,
Each has an n ⁻ layer 17 into which n-type impurities are introduced at a low concentration.

On the substrate 11, a gate oxide film 12 is formed. A first polysilicon electrode 13 is formed on the gate oxide film 12 between the n ⁺ layers 19 by patterning. On the first polysilicon electrode 13, a second polysilicon electrode 15 is formed via a natural oxide film 14. The width of the second polysilicon electrode 15 is smaller than the width of the first polysilicon electrode 13, and the width of the upper surface of the second polysilicon electrode 15 is smaller than the width of the lower surface. . On this second polysilicon electrode 15, a first oxide film 16 is formed. The width of the first oxide film 16 is formed slightly wider than the width of the upper surface of the second polysilicon electrode 15.

On both sides of the first and second polysilicon electrodes 13, 15 and the first oxide film 16, a second oxide film 18 is formed.

In the MISFET thus configured, the gate electrode (first polysilicon film 13) and the n ⁻ layer 17 overlap in a plan view in a region indicated by a dashed circle in the drawing. Therefore, the potential of n ⁻ layer 17 is affected by the potential of gate electrode (first polysilicon film 13). In this case, by optimizing the width of the overlap and the impurity concentration of the n ⁻ layer 17, a MISFET having a channel length of about 0.5 μm and having excellent withstand voltage characteristics and high-speed characteristics can be realized. In this MISFET, since the hot carrier injection region is an overlap region separated from the side wall spacer (second oxide film 18), the number of carriers trapped in the spacer oxide film is small, and the hot carrier resistance of the MISFET is small. Is high.

 Next, a method for manufacturing the above-described MISFET will be described.

4 (a) to 4 (d) are cross-sectional views showing a method of manufacturing the MISFET described above in the order of steps.

First, as shown in FIG. 4A, a gate oxide film 12 is formed on a silicon substrate 11, and a first polysilicon electrode 13 is formed on the gate oxide film 12 to a thickness of, for example, 50 nm. Then, by exposing the surface of the first polysilicon electrode 13 to air, a natural oxide film 14 having a thickness of about 1 nm is formed on the surface of the polysilicon electrode 13. Thereafter, a second polysilicon electrode 15 is deposited on the natural oxide film 14.

Next, after a first oxide film 16 is formed on the entire surface of the second polysilicon electrode 15, the first oxide film 16 is patterned into a predetermined shape.

Next, as shown in FIG. 4 (b), the second polysilicon electrode 15 is subjected to high selective dry etching using the first oxide film 16 as a mask. This etching is completed when the native oxide film 14 is exposed. In this case, the second polysilicon electrode 15 below the first oxide film 16 is slightly side-etched, and an inclined surface is formed on the side of the second polysilicon electrode 15. Thereafter, the first oxide film 16 is masked, and phosphorus is ion-implanted into the surface of the substrate 11 through the natural oxide film 14, the first polysilicon electrode 13 and the gate oxide film 12, so that the impurity concentration is reduced. The low n ^- layer 17 is formed in a self-aligned manner.

Next, as shown in FIG. 4 (c), after depositing a second oxide film 18 on the entire surface, etching back is performed to form a first oxide film 18.
The second oxide film 18 is left only on the side of the oxide film 16 and the second polysilicon electrode 15. Then, portions of the natural oxide film 14, the first polysilicon electrode 13 and the gate oxide film 12 which are not covered with the second oxide film 18 are removed.

Next, as shown in FIG. 4 (d), after oxidizing under a wet oxidation condition at a temperature of 800 ° C., arsenic is deposited on the surface of the substrate 11 by using the first and second oxide films 16 and 18 as a mask. By ion implantation, an n ⁺ layer 19 having a high impurity concentration is formed. Thus, the above-described MISFET can be manufactured.

[Problems to be Solved by the Invention] However, the above-mentioned conventional MISFET has the following problems.

In other words, the overlap region between the gate electrode and the n ⁻ layer 17 indicated by the dashed circle in FIG. 3 is also a region into which hot carriers are injected during operation. Therefore, the gate oxide film 12 near this region needs to have a low carrier trap density. However, when the MISFET is manufactured by the above-described manufacturing method, the gate oxide film 12 is formed in the step of forming the n ⁻ layer 17.
Is damaged by the phosphorus ion implantation and the gate oxide film 12
Carrier trap density increases. For this reason,
The MISFET has a problem that, for example, hot carrier resistance cannot be ensured at the time of 5V operation.

The present invention has been made in view of such a problem, and has a low carrier trap density of a gate oxide film in a region into which hot carriers are injected, has excellent withstand voltage characteristics and high-speed performance, and can be highly integrated. It is an object of the present invention to provide a simple insulated gate field effect transistor and a method for manufacturing the same.

[Means for Solving the Problems] A method of manufacturing an insulated gate field effect transistor according to the present invention includes a step of forming a first gate insulating film on a semiconductor substrate, and a step of forming a predetermined gate insulating film on the first gate insulating film. Forming a first gate electrode in a pattern, and forming a low-concentration impurity region by introducing an impurity at a low concentration to the substrate surface through the first gate insulating film using the first gate electrode as a mask; Etching the first gate insulating film using the first gate electrode as a mask; and forming a second gate insulating film on a side portion of the first gate electrode and on the low concentration impurity region. And selectively forming a second gate electrode on the side of the first gate electrode with the second gate insulating film interposed therebetween, and masking the first and second gate electrodes. As the above Forming a high-concentration impurity region by introducing an impurity of the same conductivity type as that of the low-concentration impurity region into the surface of the substrate through a second gate insulating film at a high concentration.

In the present invention, a source / drain region is formed on a surface of a semiconductor substrate with a channel region interposed therebetween, and the source / drain region is formed on a side of a first gate electrode insulated from the channel region. An insulated second gate electrode is formed in both the region and the first gate electrode. That is, the second gate electrode is disposed insulated from the end of the source / drain region on the channel side. Therefore, the potential of the end portion of the source / drain region is affected by the potential of the second gate electrode due to capacitive coupling. On the other hand, the potential of the second gate electrode is affected by the potential of the first gate electrode due to capacitive coupling. Therefore, the potential of the region at the end portion of the source / drain region on the channel side changes according to the potential of the first gate electrode. Accordingly, the withstand voltage characteristics of the transistor can be improved, and the transistor can operate at high speed.

In the method of the present invention, a first gate electrode is formed on a semiconductor substrate via a first insulating film. And
Using the first gate electrode as a mask, a low-concentration impurity region is formed by introducing impurities at a low concentration into the substrate surface.
At the time of the impurity introduction, the first gate insulating film in a region except immediately below the first gate electrode is damaged by the impurity ions. Next, the first gate insulating film is etched away using the first gate electrode as a mask. Thereby, the first gate insulating film damaged at the time of impurity introduction is removed. Next, after forming a second gate insulating film on the side of the first gate electrode and on the substrate,
A second gate electrode is formed on the side of the gate electrode. Next, using the first and second gate electrodes as a mask, a high concentration impurity is introduced into the substrate surface to form a high concentration impurity region.

In the method of the present invention, since the transistor is manufactured in this manner, the insulated gate field effect transistor having the above-described structure can be easily manufactured. Further, according to the method of the present invention, the second gate insulating film on the low-concentration impurity region is not damaged by the impurity ions, so that the carrier trap density in this region is extremely low. Thus, a transistor having a short channel length, excellent withstand voltage characteristics and high speed characteristics, and having high hot carrier resistance can be obtained.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an insulated gate field effect transistor according to an embodiment of the present invention.

On the surface of the silicon substrate 1, a pair of
An n ⁺ layer 7 is formed, and n ⁻ layers 4 are formed at opposite ends of the n ⁺ layer 7, respectively. A first gate oxide film 2 having a thickness of, for example, 100 ° is formed on the substrate 1 between the n ⁻ layers 4, and a first gate oxide film 2 is formed on the first gate oxide film 2.
Gate electrode 3 is formed. Further, on the side portions of the first gate electrode 3 and on the n ⁻ layer 4 and the n ⁺ layer 7, the second
The gate oxide film 5 is formed with a thickness of, for example, 100 °. Then, a second gate electrode 6 is formed above n ⁻ layer 4 with this second gate oxide film 5 interposed therebetween.

In the present embodiment, as described above, the second gate electrode 6 is formed on both sides of the first gate electrode 3 with the second gate oxide film 5 interposed therebetween. An n ⁻ layer 4 is formed below via a second gate oxide film 5. The potential of the n ⁻ layer 4 is changed to the second gate oxide 5
Is affected by the potential of the second gate electrode 6. The potential of the second gate electrode 6 is affected by the potential of the first gate electrode 3 by capacitive coupling via the second gate oxide film 5. That is,
The potential of n ⁻ layer 4 is affected by the potential of first gate electrode 3. Therefore, similarly to the conventional MISFET shown in FIG. 3, the withstand voltage characteristic can be appropriately selected by appropriately selecting the width of the overlap between the second gate electrode 6 and the n ⁻ layer 4 and the impurity concentration of the n ⁻ layer 4. In addition, a MISFET excellent in high speed can be realized. For example, when it is desired to increase the capacitive coupling between the first gate electrode 3 and the n ⁻ layer 4, the thickness of the second gate oxide film 5 may be reduced to, for example, about 50 °. On the other hand, when it is desired to weaken the capacitive coupling between first gate electrode 3 and n ⁻ layer 4, the thickness of second gate oxide film 5 may be increased, for example, to about 200 °. In this manner, the potential of the n ⁻ layer 4 during operation can be optimized, and a MISFET having excellent withstand voltage characteristics and high-speed characteristics can be realized.

2 (a) to 2 (f) are cross-sectional views showing a method for manufacturing the MISFET described above in the order of steps.

First, as shown in FIG. 2A, a first gate oxide film 2 is formed on a silicon substrate 1 to a thickness of, for example, 100 °. Then, a first gate electrode 3 is formed on the first gate oxide film 2 in a predetermined pattern.

Next, as shown in FIG. 2 (b), using the first gate electrode 3 as a mask, phosphorus is ion-implanted at a low concentration on the surface of the substrate 1 to form the n ⁻ layer 4 in a self-aligned manner. . During this ion implantation, the gate oxide film 2 in a region other than a region immediately below the first gate electrode 3 is damaged.

Next, as shown in FIG. 2C, using the first gate electrode 3 as a mask, the first gate oxide film 2 is removed by, for example, a diluted HF solution. In this case, the gate oxide film 2 below the first gate electrode 3 is slightly side-etched, so that a space is formed below the lower edge of the gate electrode 3.

Next, as shown in FIG. 2 (d), the second surface is formed on the peripheral surface of the gate electrode 3 and the n ⁻ layer 4 by high-temperature CVD (vapor phase growth).
Is formed with a thickness of, for example, 100 °.

Next, as shown in FIG. 2 (e), a polysilicon film is deposited on the entire surface, and this polysilicon film is subjected to etching back so that a second gate is formed on the side of the first gate electrode 3. An electrode 6 is formed.

Next, as shown in FIG. 2F, arsenic is ion-implanted into the surface of the silicon substrate 1 using the first and second gate electrodes 3 and 6 as a mask, so that the n ⁺ layer 7 is self-aligned. To form Thus, the insulated gate field effect transistor according to the present embodiment can be manufactured.

According to the method of the present embodiment, the gate oxide film 5 in the hot carrier injection region indicated by the dashed circle in FIG. 1 is not damaged by ion implantation, so that the carrier trap density in this region is extremely low. As a result, MISF has high hot carrier resistance, excellent resistance characteristics, and can operate at high speed.
You can get ET.

Note that the second gate oxide film 5 may be formed by thermally oxidizing the surfaces of the gate electrode 3 and the n ⁻ layer 4 instead of the high-temperature CVD described above. In this case, the oxide film that insulates first gate electrode 3 and second gate electrode 6 and the oxide film that insulates second gate electrode 6 and n ⁻ layer 4 have different thicknesses. However, also in this case, the potential of the n ⁻ layer 4 can be optimized as in the above-described embodiment.

According to the method of the present invention, the first gate electrode formed on the substrate via the first gate insulating film is used as a mask to form a low-concentration impurity region on the substrate surface. After the first gate insulating film is removed using the gate electrode as a mask, a second gate insulating film is formed on the low-concentration impurity region and on the side of the first gate electrode. Is not damaged by ion implantation. Thereby, it has the above-mentioned structure,
An insulated gate field effect transistor having a very low carrier trap density in the hot carrier injection region can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an insulated gate field effect transistor according to an embodiment of the present invention, FIGS. 2 (a) to 2 (f) are sectional views showing a method of manufacturing the same in the order of steps, and FIG. FIGS. 4 (a) to 4 (d) are cross-sectional views showing a gate field-effect transistor, similarly showing a method of manufacturing the same in order of steps. 1,11; silicon substrate, 2,5,12; gate oxide film, 3,6; gate electrode, 4,17; n ^- layer, 7,19; n ⁺ layer, 13,15; polysilicon layer,
14; natural oxide film, 16, 18; oxide film

Claims (1)

(57) [Claims] A step of forming a first gate insulating film on a semiconductor substrate; a step of forming a first gate electrode in a predetermined pattern on the first gate insulating film; Forming a low-concentration impurity region by introducing an impurity at a low concentration to the substrate surface through the first gate insulating film using an electrode as a mask; and forming the first gate insulating film using the first gate electrode as a mask. Etching; removing a second gate insulating film on a side portion of the first gate electrode and the low-concentration impurity region; and forming a second gate insulating film on a side of the first gate electrode. Selectively forming a second gate electrode via a gate insulating film; and forming the low concentration impurity region on the substrate surface through the second gate insulating film using the first and second gate electrodes as a mask. Of the same conductivity type Method of manufacturing an insulated gate field effect transistor, characterized by a step of forming a high-concentration impurity regions by introducing a pure object at a high concentration.