JPH0458537A - Insulated-gate field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make a channel length short, to be excellent in a breakdown-strength characteristic and a high-speed property and to realize a high integration by a method wherein a source region, a drain region, a first gate electrode and a second gate electrode in respectively specific shapes are formed on the surface of a semiconductor substrate. CONSTITUTION:A source region and a drain region are formed on the surface of a semiconductor substrate 1 so as to sandwich a channel region. Second gate electrodes 6 which are insulated from the source region, the drain region and a first gate electrode 3 are formed on-the side faces of the first gate electrode 3 which is insulated from the channel region. As a result, a potential at the end parts of the source region and the drain region is influenced by a potential of the second gate electrodes 6 due to a capacitive coupling action. On the other hand, the potential of the second gate electrodes 6 is influenced by a potential of the first gate electrode 3 due to a capacitive coupling action. Consequently, a potential in regions at the end parts on the channel side of the source region and the drain region is changed according to the potential of the first gate electrode 3. Thereby, it is possible to enhance the breakdown-strength characteristic of a transistor and to realize a high-speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor suitable for constructing a very large scale integrated circuit (LSI) and a method for manufacturing the same.

[Prior Art] Insulated gate field effect transistors (hereinafter referred to as MI 5FETs) used in VLSIs tend to have shorter channels as semiconductor devices become more highly integrated.

Conventionally, in the case of a MISFET with a channel length of about 1 μm, a low concentration source/drain region is placed between a high concentration source/drain region and a channel region.
D (Lfghtly Doped Dratn)
The MI construction achieves improved voltage resistance and faster operation. However, the channel length is 0.
In the MI 5FET, which has become even shorter to about 5 μm, sufficient breakdown voltage characteristics and high speed cannot be obtained with the conventional LDD structure. For this reason, a MISFET suitable for shortening the channel has been proposed ("High breakdown voltage + 1 high speed 5V operation submicron device GOLD J, 31
~36 pages, IEICE Technical Report (SDM87-157), 1988
Published in 2013).

FIG. 3 is a sectional view showing a MISFET suitable for shortening the channel described above.

On the surface of the semiconductor substrate 11, a pair of n' layers 19 doped with n-type impurities at a high concentration are formed at an appropriate distance from each other. An n- layer 17 doped with n-type impurities at a low concentration is formed at the mutually opposing ends of each n'' layer 19.

A gate oxide film 12 is formed on the substrate 11 . A first polysilicon electrode 13 is patterned on the gate oxide film 12 between the n' layers 19. Also,
A natural oxide film 1 is formed on this first polysilicon electrode 13.
4, a second polysilicon electrode 15 is formed. The width of this second polysilicon electrode 15 is narrower than the width of the first polysilicon electrode 13, and the width of the upper surface of this second polysilicon electrode 15 is narrower than the width of its lower surface. There is. This second polysilicon electrode 15
A first oxide film 16 is formed thereon. The width of this first oxide film 16 is made slightly wider than the width of the upper surface of second polysilicon electrode 15 .

A second oxide film 18 is formed on both sides of the first and second polysilicon electrodes 13 15 and the first oxide film 16 .

In the MISFET configured in this manner, the gate electrode (first polysilicon film 13) and the n- layer 17 overlap in a plan view in the region indicated by the broken line circle in the figure. Therefore, the potential of the 0 layer 17 is the gate electrode (
It is influenced by the potential of the first polysilicon film 13). In this case, by optimizing the overlap width and the impurity concentration of the n-layer 17, the channel length can be reduced to approximately 0.5 μm.
MI 5FET with excellent voltage resistance and high speed performance
can be realized. In addition, in this MI 5FET, since the hot carrier injection region is an overlap region separated from the sidewall spacer (second oxide film 18), the number of carriers trapped in the spacer oxide film is small, and the hot carrier resistance of the MISFET is is high.

Next, a method for manufacturing the above-mentioned MrSFET will be explained.

FIGS. 4(a) to 4(d) are cross-sectional views showing the method for manufacturing the above-mentioned MISFET in order of steps.

First, as shown in FIG. 4(a), a gate oxide film 12 is formed on a substrate 11, and a first polysilicon electrode 13 is formed on the gate oxide film 12 to a thickness of, for example, 50 nm. Then, this first polysilicon electrode 13
By exposing the surface of the polysilicon electrode 13 to air,
A natural oxide film 14 having a thickness of about 1 nm is formed on the surface of the substrate.

Thereafter, a second polysilicon electrode 15 is deposited on this natural oxide film 14.

Next, a first oxide film 16 is formed on the entire surface of the second polysilicon electrode 15, and then the first oxide film 16 is buttered and molded into a predetermined shape.

Next, as shown in FIG. 4(b), the second poly7 silicon electrode 15 is subjected to highly selective dry etching using the first oxide film 16 as a mask. This etching ends when the native oxide film 14 is exposed.

In this case, the second polysilicon electrode 15 below the first oxide film process 6 is slightly side-etched, and an inclined surface is formed on the side of the second polysilicon electrode 15. Thereafter, using the first oxide film 16 as a mask, phosphorus is ion-implanted into the surface of the substrate 11 through the natural oxide film 14, the first polysilicon electrode 13, and the gate oxide film 12, thereby increasing the impurity concentration. The n-layer 17 having a low n-layer is formed in a self-aligned manner.

Next, as shown in FIG. 4(C), after depositing a second oxide film 18 on the entire surface, etching back is performed to remove the first oxide film 18.
The second oxide film 18 is left only on the sides of the oxide film 16 and the second polysilicon electrode 15. And this second
The natural oxide film 14 in the part not covered with the oxide film 18,
First polysilicon electrode 13 and gate oxide film 12 are removed.

Then, as shown in FIG. 4(d), the temperature was increased to 800°C.
After performing oxidation under wet oxidation conditions, the first and second
Using the oxide films ie and is as masks, arsenic ions are implanted into the surface of the substrate 11 to form an n+ layer 19 having a high impurity concentration. In this way, the MI 5FET described above can be manufactured.

[Problems to be Solved by the Invention] However, the conventional MI 5FET described above has the following problems.

That is, the gate electrode and the n-layer 17 shown by the dashed circle in FIG.
The overlapping region with the 3D is also the region where hot carriers are injected during operation. Therefore, it is necessary that the gate oxide film 12 near this region has a low carrier trap density. However, due to the above-mentioned manufacturing method, MI 5F
When an ET is manufactured, the gate oxide film 12 is damaged by phosphorus ion implantation in the process of forming the n- layer 17, and the carrier trap density of the gate oxide film 12 becomes high. For this reason, the conventional MISFET has a problem in that hot carrier resistance cannot be ensured during, for example, 5V operation.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide an insulated gate field effect transistor that has a low carrier trap density in a gate oxide film in a region where hot carriers are injected, has excellent breakdown voltage characteristics and high speed, and can be highly integrated, and a method for manufacturing the same. shall be.

[Means for Solving the Problems] An insulated gate field effect transistor according to the present invention includes a semiconductor substrate, a source/drain region formed on the surface of the semiconductor substrate with a channel region sandwiched therebetween, and a first gate electrode formed insulated;
A second gate electrode is provided on the side of the first gate electrode and is insulated from the first gate electrode and the source/drain region.

The method for manufacturing an insulated gate field effect transistor according to the present invention includes the steps of forming a first gate insulating film on a semiconductor substrate, and forming a first gate electrode in a predetermined pattern on the first gate insulating film. a step of introducing impurities into the substrate surface at a low concentration using the first gate electrode as a mask to form a low concentration impurity region; and a step of introducing the first gate insulating region using the first gate electrode as a mask. a step of etching away the film; a step of forming a second gate insulating film on the sides of the first gate electrode and the low concentration impurity region; selectively forming a second gate electrode through a gate insulating film, and doping impurities of the same conductivity type as the low concentration impurity region on the substrate surface using the first and second gate electrodes as masks. The method is characterized by comprising a step of forming a high concentration impurity region by introducing the impurity at a high concentration.

[Function] In the present invention, source/drain regions are formed on the surface of a semiconductor substrate sandwiching a channel region, and the source/drain regions are formed on the side of a first gate electrode insulated with respect to the channel region. An insulated second gate electrode is formed on both the region and the first gate electrode. That is, the second gate electrode is arranged insulated from the end portion of the source/drain region on the channel side.

Therefore, the potential of the end portions of the source/drain regions is influenced by the potential of the second gate electrode due to capacitive coupling. On the other hand, the potential of the second gate electrode is influenced by the potential of the first gate electrode due to capacitive coupling. Therefore, the potential of the end portion of the source-)'' rain region on the channel side changes depending on the potential of the first gate electrode.

As a result, the breakdown voltage characteristics of the transistor can be improved, and the transistor can operate at high speed.

Further, in the method of the present invention, a first gate electrode is formed on the semiconductor substrate with a first insulating film interposed therebetween. Then, using this first gate electrode as a mask, impurities are introduced into the substrate surface at a low concentration to form a low concentration impurity region. At the time of introducing the impurity, the first gate insulating film in a region other than the region directly under the first gate electrode is damaged by the impurity ions.

Next, using the first gate electrode as a mask, the third gate insulating film is removed by etching. As a result, the first gate insulating film that was damaged during the introduction of impurities is removed. Next, a second gate insulating film is formed on the sides of the first gate electrode and on the substrate, and then a second gate electrode is formed on the sides of the first gate electrode. Next, using the first and second gate electrodes as masks, impurities are introduced into the substrate surface at a high concentration to form a high concentration impurity region.

In the method of the present invention, since the transistor is manufactured in this manner, an insulated gate field effect transistor having the above-described structure can be easily manufactured. Furthermore, according to the method of the present invention, the second gate insulating film on the low-degree impurity region is not damaged by impurity ions, so the carrier trap density in this region is extremely low. This makes it possible to obtain a transistor with a short channel length, excellent breakdown voltage characteristics and high speed, and high hot carrier resistance.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an insulated gate field effect transistor according to an embodiment of the present invention.

On the surface of the silicon substrate 1, a pair of n
A first gate oxide layer 7 is formed on the substrate 1 between the n-layers 4, and an n-layer 4 is formed at the opposite end of the n''-layer 7. A film 2 is formed to have a thickness of, for example, 100 nm, and a first gate electrode 3 is formed on this first gate oxide film 2. and n-layer 4 and n4 layer 7
A second gate oxide film 5 is formed thereon to a thickness of, for example, 100 nm. A second gate electrode 6 is formed above the n- layer 4 with this second gate oxide film 5 interposed therebetween.

In this embodiment, as described above, the first gate electrode 3
A second gate electrode 6 is formed on both sides of the gate via a second gate oxide film 5, and an n- layer is formed below the second gate electrode 6 via a second gate oxide film 5. 4 is formed. The potential of this 0 layer 4 is the same as that of the second gate oxide film 5.
It is affected by the potential of the second gate electrode 6 due to capacitive coupling via. The potential of the second gate electrode 6 is influenced by the potential of the first gate electrode 3 due to capacitive coupling via the second gate oxide film 5. That is, n
- The potential of the layer 4 will be influenced by the potential of the first gate electrode 3. Therefore, the conventional MISF shown in FIG.
Similar to ET, by appropriately selecting the overlamp width between the second gate electrode 6 and the n-layer 4, the impurity concentration of the n-layer 4, etc., an MIS with excellent breakdown voltage characteristics and high speed can be achieved.
It is possible to realize FET. For example, if it is desired to strengthen the capacitive coupling between the first gate electrode 3 and the n- layer 4, the thickness of the second gate oxide film 5 may be reduced to, for example, about 50 layers. On the other hand, if it is desired to weaken the capacitive coupling between the first gate electrode 3 and the n- layer 4, the thickness of the second gate oxide film 5 may be increased to, for example, about 200λ. In this way, the potential of the n-layer 4 during operation can be optimized, and a MISFET with excellent breakdown voltage characteristics and high speed can be realized.

FIGS. 2(a) to 2(f) are cross-sectional views showing the above-mentioned MI 5FET manufacturing method in the order of steps.

First, as shown in FIG. 2(a), a first gate oxide film 2 is formed on a silicon substrate 1 to a thickness of, for example, 100 mm. Then, a first gate electrode 3 is formed on this first gate oxide film 2 in a predetermined pattern.

Next, as shown in FIG. 2(b), the first gate electrode 3
Using this as a mask, phosphorus is ion-implanted at a low concentration into the surface of the substrate 1 to form the n-layer 4 in a self-aligned manner. During this ion implantation, the gate oxide film 2 in the region other than the region directly under the first gate electrode 3 is damaged.

Next, as shown in FIG. 2(C), the first gate electrode 3
Using as a mask, the first gate oxide film 2 is removed using, for example, a diluted HF solution. In this case, the gate oxide film 2 below the first gate electrode 3 is slightly side etched so that a space is formed below the lower edge of the gate electrode 3.

Next, as shown in FIG. 2(d), a second gate oxide film 5 is formed to a thickness of, for example, 100 nm on the peripheral surface of the gate electrode 3 and the n-layer 4 by high-temperature CVD (vapor phase epitaxy). Now let's form.

Next, as shown in FIG. 2(e), a polysilicon film is deposited on the entire surface, and an etching pack is applied to this polysilicon film to form a second gate on the side of the first gate electrode 3. Electrode 6 is formed.

Next, as shown in FIG. 2(f), arsenic is ion-implanted into the surface of the silicon substrate 1 using the first and second gate electrodes 3 and 6 as masks, thereby forming an n layer 7 in a self-aligned manner. Form. In this way, the insulated gate field effect transistor according to this example can be manufactured.

According to the method of this embodiment, the gate oxide film 5 in the hot carrier injection region indicated by the broken line circle in FIG. 1 is not damaged by ion implantation, so the carrier trap density in this region is extremely low. As a result, MIS has high hot carrier resistance, excellent voltage resistance characteristics, and is capable of high-speed operation.
FET can be obtained.

Note that the second gate oxide film 5 may be formed by thermally oxidizing the surfaces of the gate electrode 3 and the n-ff 14 instead of the above-described high-temperature CVD. In this case, an oxide film insulating the first gate electrode 3 and the second gate electrode 6;
The oxide film that insulates the second gate electrode 6 and the n-layer 4 has a different thickness. However, in this case as well, it is possible to optimize the potential of the n-layer 4, as in the above embodiment.

[Effects of the Invention] As explained above, according to the present invention, the second gate electrode, which is insulated from both the first gate electrode and the source/drain region formed on the surface of the semiconductor substrate, is connected to the first gate electrode.
Since the first gate electrode is formed on the side of the first gate electrode, the potential of the channel-side end portion of the source/drain region is affected by the potential of the first gate electrode due to capacitive coupling. That is, the potential of the channel side end portions of the source/drain regions of the insulated gate field effect transistor changes depending on the potential of the gate electrode. This makes it possible to obtain an insulated gate field effect transistor that has excellent breakdown voltage characteristics, is capable of high-speed operation, and is suitable for high integration.

Further, according to the method of the present invention, a low concentration impurity region is formed on the surface of the substrate using the first gate electrode formed on the substrate via the first gate insulating film as a mask, and the first gate electrode After removing the first gate insulating film using the mask as a mask, a second gate insulating film is formed on the low-degree impurity region and on the sides of the first gate electrode, thereby insulating the hot carrier injection region. The membrane is not damaged by ion implantation. As a result, it is possible to manufacture an insulated gate field effect transistor having the above-described structure and having extremely low carrier trap density in the hot carrier injection region.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an insulated gate field effect transistor according to an embodiment of the present invention, FIGS. FIGS. 4(a) to 4(d) are cross-sectional views showing a gate field effect transistor, and are also cross-sectional views showing the manufacturing method thereof in the order of steps.

Claims (2)

[Claims] (1) a semiconductor substrate, a source/drain region formed on the surface of the semiconductor substrate sandwiching a channel region, a first gate electrode formed insulated from the channel region; An insulated gate field effect transistor comprising: a second gate electrode formed on a side of the gate electrode to be insulated from the first gate electrode and the source/drain region. (2) forming a first gate insulating film on the semiconductor substrate; forming a first gate electrode in a predetermined pattern on the first gate insulating film; forming a low concentration impurity region by introducing impurities into the surface of the substrate using the first gate electrode as a mask; etching away the first gate insulating film using the first gate electrode as a mask; forming a second gate insulating film on the side of the gate electrode and on the low concentration impurity region; and forming a second gate insulating film on the side of the first gate electrode via the second gate insulating film. A high concentration impurity region is formed by selectively forming electrodes and introducing impurities of the same conductivity type as the low concentration impurity region into the substrate surface at a high concentration using the first and second gate electrodes as masks. 1. A method of manufacturing an insulated gate field effect transistor, the method comprising: forming an insulated gate field effect transistor.