JPS62195176A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the deterioration of the device characteristics and improve current driving capability by a method wherein a 2nd conductivity type impurity is implanted with a low concentration by using a gate electrode formed on the part of a substrate surface which is to be a transistor region as a mask and high concentration ions are implanted from the source side to the drain direction. CONSTITUTION:After element isolation and formation of a gate oxide film 3 are carried out, polycrystalline silicon 4 and a CVD-SiO2 film 5 are deposited. After a resist pattern of a gate electrode is formed on the film 5 and etching is performed and the resist is removed, the polycrystalline silicon 4 is etched with the patterned SiO2 film 6 as a mask to form the polycrystalline silicon film 7. After 2nd conductivity type impurity ions are implanted with a low concentration and n<-> type ion implanted layers 8 are formed, a CVD-SiO2 film 9 is deposited and the film 9 on the flat parts are removed to leave SiO2 side walls 10 on the sides of the gate electrode. Then 2nd conductivity type impurity ions are implanted with a high concentration along the inclined direction parallel to the direction of a gate channel to form ion implanted layers 11 and a heat treatment is carried out to form asymmetrical source and drain regions 12-14.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device with high density and high speed.

Conventional technologySemiconductor integrated circuits are becoming denser and faster, but MO
In eight devices, the gate length is becoming shorter and uniform, and the punch-through breakdown voltage between the source and drain becomes one of the major problems. For that reason, L D D (light
ly doped drain) structure and DDD (do
Semiconductor processes have been considered in which improvements are made to the ion implantation and diffusion process for sources and drains, such as a (vble, diffvsed drain) structure. These are mainly intended to provide an implanted region with a lower concentration than the conventional source/drain implanted region near the electrode edge and to control electric field concentration in that region.

I think it can almost be said that the manufacturing process is a manufacturing process that adds a low concentration source/drain implantation process to the MO8FET 3 vane manufacturing process (normal LDDs are polysilicon gates) and a CVD-8i02 process (called sidewalls) on the gate sidewalls. It will be done. An example of the process will be described below with reference to FIG.

After passing through the element isolation process (LOGOS process here) and gate oxide film formation process, polysilicon 772
47! : 1st (7) CV D -5iO225'fl
Teho (Figure 3 (a)). Here, 21 is p-type (100
) A silicon substrate, 22 is an element isolation oxide film formed by the LOGOS process, and 23 is a gate oxide film. After patterning a gate electrode using resist on the CVD-8iOz film, for example, (HF3iOz)
CVD-8 using RIE (reactive ion etching)
iO2i etching, and using the CVD-8iO2 film as an etching mask, the polysilicon film is also etched by RIE (FIG. 3(b)). In FIG. 3(b), 26 is a GVD-8i02 film after etching, and 27 is a polysilicon film after etching. Next, in this case, low concentration phosphorus ion implantation is performed to form an n-layer 28 in the source and drain regions (FIG. 3(C)). After this, the second cv
D-8iOz29 was formed (Fig. 3(d)), and this was etched by RIE to form the second G V D - of the flat part.
The 5iOz layer is removed (FIG. 3(e)). This step leaves cvD-8i0230 called sidewall SiO2 on the sidewall of the gate electrode. The shape of this sidewall 5102 can be controlled by etching conditions such as etching gas and overetching time. Finally, in this case, high-concentration arsenic ion implantation is performed to completely form the n+ ion implantation layer 31, as shown in FIG. 3 (0), and heat treatment is performed. Become. Here, 32 and 33 are the n1 layer and the n+ layer, respectively [P, J, Tsun, S, Ograph Application of High Performance LDDFE
T's with Oxide Sidewall Spacer Technology "IEEE" Lands Action on Electron Devices (P, J TSUNG S, 0GURAF
Abrication of High-Performance
mance LDDFET'S5,-with Oxide Sidewall-8pace
r Technology”IEEK Transa
ction On Electron Devi
ces) Vol ED-29A4 (1982)
':].

Problems to be solved by the invention: The above-mentioned LDD structure alleviates electric field concentration near the drain, suppressing the deterioration of characteristics of MOSFETs with short gate lengths (177 m or less) accompanying the increase in density and speed of semiconductor integrated circuits. Now you can. However, since a high-resistance n-layer is inserted between the n+ source-drain layer and the inversion layer under the gate electrode, when the device is in the ON state, the voltage drop across this n-layer reduces the drive capacity of MO8F[T (Jm) It's a few tenths of a factor lower than MO8 [D, A, Bagley "Four Advance with Lightly Doped Drain Transistor] VLSI Circuit"
IKEE) Lands Action on Electron Devices (D, A.

Baglee Lightly Doped Drai
n Transistors for Advanced
VLSI 0ircvit // IEEE Trans
action On) C1ectron Device
es) Vol ED-31 Bian 5 (1986)].

Go to 6.

Means to Solve the Problem If we proceed structurally, it will be seen that electric field concentration occurs near the drain, and the n″′ layer on the source side is completely meaningless.

In the present invention, when forming an n single layer, ion implantation is performed at a nearly vertical implantation angle used in a normal process, and by performing ion implantation for forming an A4 single layer obliquely from the source side to the drain force direction, one side (source side) On the other hand, implantation is performed up to the edge of the gate electrode, and on one side (drain side), implantation is performed using the shadow of the gate electrode at a certain distance from the electrode edge determined by the implantation angle, etc., and the former is used as the source,
This problem is attempted to be overcome by applying the latter to the drain. Unfortunately, in this case, the profile of ion implantation for forming the n0 layer is limited from the perspective of device design, and if the ions are implanted to a certain depth, the n0 layer on the source side will be under the gate electrode. It is about to penetrate a certain distance. This increases the parasitic capacitance of the element and reduces the speed, so here, as with the 7...-7 LDD, sidewall CVD -3iOz'i is used in a shape that matches the ion implantation conditions for forming the next n0 layer. After the formation, the last n-layer forming ion implantation is performed obliquely to obtain a more ideal MO3F1i:T structure.

Effects of the present invention By the method described in "=", the present invention improves the decrease in current drive ability due to the presence of n layer in the conventional LDD structure while suppressing the deterioration of device characteristics due to electric field concentration on the drain side, which is the main problem of the LDD structure. It is something.

Embodiment FIG. 1 is a process sectional view showing an embodiment of the present invention. Similar to the LD D-MO8FET manufacturing process described above, after passing through the element isolation process (here, the LOGOS process) and the gate oxide film formation process, the polysilicon 4 and the first
A CVD-8iO2 film 5 is deposited (FIG. 1(a)).

Here, 1 is a p-type (100) silicon substrate, and 2 is h
Inter-element isolation oxide film formed by ocos process,
3 is a gate oxide film. After patterning the gate electrode with resist on the CVD-8i02 film, for example, CT (F3
The -5iOz film is etched, and after the resist is removed, polysilicon is etched using RIE as an etching mask for the entire patterned CVD-8iO2 film (FIG. 1(b)). In FIG. 1('b), 6 is a CVD-8iOz film after etching, and 7 is a polysilicon film after etching.

Next, in this case, phosphorus total 40Kev・11013Ato/
Ion implantation is performed at a low concentration of about 1.5 cm" to form an n- ion implantation layer 8 in the source/drain region (Fig. 1(C)).
). At the second stage (FIG. 1(d)) of depositing the DCV D -SiO2 film 9, this 3IO2 film 9'ff: (HF
, the second G V D-8iO2 film on the plane portion is removed by etching almost vertically by RIE using gas (FIG. 1(e)). As can be seen by comparing Figures i1 (d) and (e), sidewalls 5iOz10 remain on the side walls of the gate electrode due to the anisotropic etching of RIE. The shape of this sidewall 5102 is controlled by the second GVD-3iOz film thickness and the etching conditions at this time so that ions are not implanted directly under the electrode in the next implantation of oblique ions 9peno 100 (FIG. 3).

Finally, as shown in Figure 2, arsenic ion 100f: 8
Ion implantation was performed obliquely at an angle of 30° parallel to the gate channel at a high concentration of 0 KeV @ 5 X 10" A tom/C$ to form the n+ ion implantation layer 1.
1 (f'l) and heat treatment, a MOSFET having asymmetric source and drain diffusion regions as shown in FIG. 1(q) is manufactured. Here, 12, 13 and 14 are 9 to 10 layers and n10 layers, respectively. Note that 12 and 13 are drain regions, and 14 is a source region.゛Effects of the Invention The present invention enables MOSFETs with a gate length of 1 μm or less to be used in semiconductor integrated circuit technology, which is becoming increasingly dense and fast.
It has become possible to manufacture products that have good characteristics such as subthreshold characteristics and snoring characteristics, and also have good driving performance.

104, -7

[Brief explanation of drawings]

1A to 1Q are process cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing an ion implantation state in the middle of the process of FIG. figure(
a) to (q) are process cross-sectional views showing an example of a conventional LDD manufacturing process. 1...p-type (100) silicon substrate, 2...
...Inter-element isolation oxide film, 3...Gate oxide film, 6...OV D -SiO2 film, 7...
...Gate polysilicon, 1o...Side wall 0VD-8i02.12...-n-diffusion layer, 1
3.14...n10 diffusion layer. Name of agent: Patent attorney Toshi Nakao, 1 person, Jill: 3, Figure 3A

Claims (3)

[Claims] (1) After the gate oxide film process, a step of forming a gate electrode on a portion of the surface of the first conductivity type semiconductor substrate that will become a transistor region, and implanting a second conductivity type impurity at a low concentration using the gate electrode as a mask. A method of manufacturing a semiconductor device, comprising a first ion implantation step and a second ion implantation step of implanting impurities of a second conductivity type at a high concentration from the source side toward the drain using the gate electrode as a mask. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the second ion implantation is performed after forming a spacer on the side wall of the gate electrode. (3) The spacer is formed and the second ion implantation is performed so that the source side has a structure of only a second conductivity type high concentration impurity diffusion layer formed by the second ion implantation. 2. A method for manufacturing a semiconductor device according to item 2.