JPH02260564A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To optimize operating characteristic at each of first and second transistors by setting different forming widths of gate electrode sidewalls between the first and second transistors formed on a semiconductor substrate. CONSTITUTION:Stopper thin films 31 are respectively formed on gate electrodes 10 and 18 of memory and peripheral transistors Q1 and Q2. The films 31, 32 respectively protrude from the electrodes 10, 18. In this case, the widths L1, L2 of sidewalls 11', 19, can be accurately formed at different values by altering the protruding lengths l, k of the films 31, 32. Accordingly, the optimum sidewall widths, i.e., forming widths of N<-> diffused regions 4, 5, 14, 15 can be set in the transistors Q1 and Q2. Thus, the operating characteristics of the transistors can be optimized.

Description

[Detailed description of the invention]

[Industrial Application Field] This invention provides an L
The present invention relates to a semiconductor device having a plurality of types of transistors having a D D (L1!hty Doped Draln) structure, and a method for manufacturing the same.

[Conventional technology]

FIG. 5 is a sectional view showing a conventional EFROM having an LDD structure. As shown in the figure, there is an element formation region A in which a memory transistor Q1 and a peripheral transistor Q2 are separated by a field oxide film 1. It is formed on the P- semiconductor substrate 1 in B. In the memory transistor Q1, an N source region 3a and an N drain region 3b, which are deeply doped to N type, are formed in the upper layer of the P'' semiconductor substrate 1 in the element formation region A. Adjacent to each of the N source region 3a and the N drain region 3b, shallow N-type doped N- diffusion regions 4.5 are formed. Further, the area near the surface of the P- semiconductor substrate 1 between the N- diffusion regions 4 and 5 is defined as a channel region 6. A gate electrode 8 made of polysilicon is provided on channel region 6 with gate oxide film 7 in between. A gate electrode 10 made of polysilicon is provided on this gate electrode 8 with a gate oxide film 9 interposed therebetween. A sidewall 11 made of a non-doped oxide film is provided on the gate oxide film 7 in contact with the sidewalls of the gate electrodes 8 and 10 and the gate oxide film 9. On the other hand, in the peripheral transistor Q2, an N source region 13a and an N+ drain region 13 deeply doped to N type are formed in the upper layer of the P− semiconductor substrate 1 in the element formation region B.
b is formed. N+ source region 13a and N
Adjacent to each of the drain regions 13b, shallowly doped N- diffusion regions 14,15 of N'' type are formed. Further, the area near the surface of the P- semiconductor substrate 1 between the N- diffusion regions 14 and 15 is defined as a channel region 16. Gate oxidation on channel region 16! A gate electrode 18 made of polysilicon is provided via 117. A sidewall 19 made of a non-doped oxide film is placed on the gate oxide film 17 in contact with the side wall of the gate electrode 18.
is provided. FIG. 116 is a sectional view showing a method of manufacturing the LDD structure EPROM shown in FIG. Hereinafter, the manufacturing method will be explained with reference to the same figure. First, in order to form isolated element formation regions A and B on a P-semiconductor substrate 1, a field oxide film 2 is formed, and a field oxide film 2 is formed. Oxidation between I2.2ll1lI2
form 1. Next, a polysilicon layer 22 having a film thickness of approximately 3000 layers is deposited, and using a resist patterned by photolithography as a mask, the polysilicon layer 22 is subjected to anisotropic plasma etching using CF4 gas.
As shown in FIG. 4(a), a polysilicon layer 22 is left on the oxide film 21 in the element formation region A. Then, after removing the oxide film 21 in the element formation region B by etching with an aqueous solution of hydrofluoric acid, the polysilicon layer 21 is removed.
An oxide film 23 is formed on the P- semiconductor substrate 1 in the element formation region B. Subsequently, a polysilicon layer 24 having a thickness of 4,000 wafers is formed over the entire surface as shown in FIG. 4(b). Next, a resist 25 is applied to the entire surface, and this resist 25
is patterned in the element formation area A by photolithography, and then, using the patterned resist 25 as a mask, dry etching is performed on the polysilicon layer 22, 24 and the oxide lI 23, as shown in FIG. , a gate electrode 8.10 and a gate oxide film 9 are formed in the element formation region A. At this time, since the resist 25 covers the entire surface of the element formation region B, the polysilicon layer 24 in the element formation region B is not etched. Next, the resist 25 is removed, and then a resist 26 is applied, and this resist 26 is buttered in the element formation area B by photolithography. Dry etching is performed to form a gate electrode 18 in the element formation region B, as shown in FIG. 2(d). At this time, since the resist 26 covers the entire surface of the element formation area A, the shapes of the gate electrodes 8 and 10 and the gate oxide film 9 in the element formation area A remain unchanged. After removing the resist 26, using the gate electrode 10.18 as a mask, the entire surface of the p-semiconductor substrate 1 is exposed to an energy of about 50 KeV at a dose of 1 to 5 x.
P ions of 1013[cs-21] are implanted, and an N impurity is added to the upper layer of the P semiconductor substrate 1. Subsequently, a film thickness of 1000 to 8000 was obtained using a vapor phase growth method.
A non-doped deposited film about the size of a human body is formed on the entire surface of the P semiconductor substrate 1, and the underlying oxide 112 is
Anisotropic etching is performed to remove thick bone including 1.23. As a result, the non-doped oxide film on the side walls of the gate electrodes 8, 10 and the gate oxide film 9 and the side wall of the gate electrode 18, which are thicker in the vertical direction with respect to the P semiconductor substrate 1 than in other regions, remains. As shown in (e), sidewalls 11.19 are formed, and
A gate oxide film 7.17 is formed. After that, the gate electrode 10.18 and the sidewall 11
．． Using 19 as a mask, P 30 to 4 is applied to the entire surface of the semiconductor substrate 1.
Dose amount 2-4 x 101 with energy around 0Ke
5 [cs-2] of As ions were implanted, and then 900 [cs-2] of As ions were implanted.
By performing thermal diffusion treatment at a temperature of 950°C to 950°C, the N source region 3a is formed as shown in FIG. 13 as N'' diffusion regions 4.degree.5.14.15 are formed under the sidewalls 11.19 together with the N drain regions 3b and 13b. In addition, this heat treatment
P, As is annealed. Thereafter, although not shown, a smooth coat, contact holes, aluminum wiring, and a surface protection film are sequentially formed to complete the EFROM. In this way, the manufactured LDD structure transistor Ql
, Q2 provides a low concentration region 4.14 between the channel 6.16 and the drains 3b and 13b by forming a sidewall 11.19. Therefore, by weakening the electric field generated near the drain when drain voltage and gate voltage are applied, the energy of hot electrons running in the electric field can be weakened. Note that the width of the sidewall manufactured in this way is determined by the thickness of the non-doped oxide film forming the sidewall and the dry etching time of this oxide film. Sidewall 11.1 formed by etching treatment
The widths L1 and L2 of 9 are the same. [Problems to be Solved by the Invention] The conventional LDD structure EPROM is configured as described above, and the widths and L2 of the sidewalls 11 and 18 of the memory transistor Q1 and the peripheral transistor Q2 are both the same length. Ta. First, the formation widths of N-regions 4 and 5 and N-regions 14 and 15 were the same. FIG. 7 shows the width Lt of the sidewall 11 in the memory transistor Q1, the write depth Δvth (which is the difference from the threshold value vth, and is an index of write efficiency), and the source-drain breakdown voltage BV8. It is a graph showing the correlation with. The memory transistor Q1 has a deep write depth Δvth and a source-drain breakdown voltage B V s. Since it is desirable that ΔV BV be higher, the optimum value of the width L1 is th' at the intersection of both ΔV BV and ΔV BV as shown in FIG.
SD is approximately 1.4 μm. FIG. 8 shows the width L of the sidewall 19 and the substrate current in the peripheral transistor Q2! (Ho2
SOB (which is an indicator of the amount of electrons generated) and current amplification factor β (which is an indicator of the current drive ability of the transistor)
It is a graph showing the correlation with the reciprocal number 1/β. Peripheral transistor Q2! , 1/UB β is preferably smaller, so the optimum value for the width L2 of the sidewall 19 is as shown in FIG. ,1
/β is approximately 2.0 μm. SOB Thus, memory transistor Q1. The widths of the sidewalls 11 and 19 of the peripheral transistor Q2 and the optimum value of L2 are different. However, as described above, since the widths of the sidewalls 11.19 and L2 are formed to have the same length, the individual transistors Q1. There was a problem in that an optimum sidewall width could not be achieved in Q2, and the operating characteristics of individual transistors could not be optimized. Note that methods for changing the width of the sidewall in individual transistors include, for example, performing an etching process using a mask or changing the thickness of the non-doped oxide film between the element formation regions A and B. Another problem with these methods is that the width of the sidewall cannot be set with high precision. This invention was made in order to solve the above-mentioned problems, and provides a semiconductor device consisting of multiple types of transistors with an LDD structure and a method for manufacturing the same, in which the operating characteristics of each individual transistor can be optimized. The purpose is to obtain. [Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, and first and second transistors formed on the semiconductor substrate, Each of the second transistors is formed on the gate electrode, and the end portion thereof is a first transistor that is closer to the gate electrode than the gate electrode in the first transistor.
a mask layer that protrudes a second length from the gate electrode in the second transistor, and a mask layer that protrudes a second length from the gate electrode; a gate electrode sidewall portion having a first formation width corresponding to the length of the gate electrode, and a gate electrode sidewall portion having a second formation width corresponding to the second length in the second transistor;
a first semiconductor region of a second conductivity type with a low impurity concentration formed in the upper layer of the semiconductor substrate under the side wall of the gate electrode; and a first semiconductor region of the semiconductor substrate under the region where the gate electrode is not formed. and a second semiconductor region of the second conductivity type that is formed adjacent to the first semiconductor region and has a higher impurity concentration than the first semiconductor region. On the other hand, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing first and second transistors on a semiconductor substrate of a first conductivity type, the method comprising: forming an insulating film on the semiconductor substrate; forming a first layer on the insulating film to become the gate electrode of the first transistor; and forming a second layer on the insulating film to become the gate electrode of the second transistor. forming a third layer, which serves as a first mask layer, on the first layer and has a lower etching rate than the first layer for first anisotropic etching; forming a fourth layer on the second layer, which serves as a second mask layer and has a lower etching rate than the second layer in the second anisotropic etching; and the first and third layers. selectively performs the first anisotropic etching to form the gate electrode of the first transistor, and due to the difference in etching rate, the end portion has a first length longer than the gate electrode of the first transistor. forming the first mask layer that protrudes slightly; and selectively performing the second anisotropic etching on the second and fourth layers to form a gate electrode of the second transistor. At the same time, due to the difference in etching rate, the edges are as described above! forming the second mask layer protruding from the gate electrode of the transistor No. 02 by a second length;
and using the gate electrode of the second transistor as a mask,
a step of implanting a second conductivity type impurity into the upper layer of the semiconductor substrate to form a first semiconductor region with a low impurity concentration; and a step of implanting a gate electrode sidewall on the semiconductor substrate including the third and fourth layers. and a step of forming a fifth layer serving as a part,
The fifth layer has a higher etching rate than the third and fourth layers for the third anisotropic etching, and has a higher etching rate than the third and fourth layers.
and performing the third anisotropic etching on the fifth layer using the second mask layer as a mask, and etching the first and second layers.
The first and second forming widths reflect the length of the first and second forming widths.
forming gate electrode side wall portions on both sides of the gate electrodes of the first and second transistors, respectively; gate electrodes of the first and second transistors and side wall portions of the first and second gate electrodes; using as a mask, implanting impurities of a second conductivity type into the upper layer of the semiconductor substrate, and forming a semiconductor region of m2 with a higher impurity concentration than the first semiconductor region adjacent to the first semiconductor region. It also has the following. [Operation] In the first transistor, the gate electrode side wall portion has a first formation width corresponding to the first length that is the protrusion length of the mask layer with respect to the gate electrode, and in the second transistor, the gate electrode side wall portion has a first formation width corresponding to the first length. Since the second formation width corresponds to the second length, the difference in the protruding length of the mask layer from the gate electrode in the first and second transistors causes the difference in the length of the first and second transistors. Second
The formation width of the gate electrode side wall portion can be set to be different between the transistors. [Example] Figure 1 shows an EPR of an LDD structure which is an example of this invention.
It is a sectional view showing OM. As shown in the figure, unlike the prior art, a stopper thin film 31 is formed on the gate electrode 10 of the memory transistor Q1, and a stopper thin film 32 is formed on the gate electrode 18 of the peripheral transistor Q2. The stopper thin films 31 and 32 are connected to the gate electrodes 10 and 10, respectively.
The end protrudes from 18. Therefore, for reasons to be described later, the widths L, L of the sidewalls 11.19
are different. Note that the other configurations are the same as those of the prior art, so explanations will be omitted. FIG. 2 is a sectional view showing a method of manufacturing the EFROM having the LDD structure shown in FIG. Hereinafter, the manufacturing method will be explained with reference to the same figure. First, in order to form isolated element formation regions A and B on a P-semiconductor substrate 1, a field oxide film 2 is formed, and an oxide film 21 is formed between the field oxides 1112 and 2. Next, a polysilicon layer 22 having a thickness of about 300 Å is deposited, and using a resist patterned by photolithography as a mask, the polysilicon layer 22 is subjected to anisotropic plasma etching using CF4 gas. (a)
As shown in FIG. 2, a polysilicon layer 22 is left on the oxide film 21 in the element formation region A. Then, after removing the oxide film 21 in the element formation region B by etching with an aqueous solution of hydrofluoric acid, the polysilicon layer 21 is removed.
An oxide film 23 is formed on the P″″ semiconductor substrate 1 in the element formation region B and on the P″″ semiconductor substrate 1 in the element formation region B. Subsequently, after forming a polysilicon layer 24 with a thickness of 4,000 on the entire surface, a thin film of silicon nitride, etc.
! i33 is formed over the entire surface as shown in FIG. 3(b) by a deposition phase growth method with a thickness of about 100 to 200 layers. This thin film 33 has an etching rate of 1/3 or less of the polysilicon layer 22.24 for the etching used for patterning the polysilicon layer 22.24, and also plays the role of a mask during the non-doped oxide film etching described later. It is a membrane that can fulfill the role of Next, a resist 25 is applied to the entire surface, and this resist 25
are patterned in the element formation area A by photolithography, and then using the patterned resist 25 as a mask, the polysilicon layers 22, 24, . The oxide film 23 and thin film 33 are dry-etched to form gate electrodes 8, 10, gate oxide film 9, and stopper thin film 31 in the element formation region A, as shown in FIG. At this time, by taking advantage of the difference in etching rate between the polysilicon layers 22, 24 and the thin film 33 and setting the dry etching time longer than before, the end of the stopper thin film 31 can be more accurately set to a predetermined length than the gate electrode 10. ! It can be made to protrude (hereinafter, this length 9 will be referred to as "protrusion length"). Furthermore, since the oxide film 23 also has a lower etching rate than the polysilicon layer 22, the end of the gate oxide film 9 protrudes from the gate electrode 8. For example, when it is desired to realize a width of the gate electrode 10 of 1.0 μm, a protrusion length of 0.2 μm, and a dimensional difference of 0.05 μm between the resist 25 and the stopper thin film 31, as shown in FIG. By setting the dimension to 1.8 μm and setting the dry etching time to a predetermined time, accurate formation can be achieved. Note that at this time, the entire surface of the element formation region B is covered with a resist 25.
Since the polysilicon layer 2 in the element formation region B is covered with
4 is not etched. Next, the resist 25 is removed, and then a resist 26 is applied to the entire surface, and this resist 26 is buttered in the element formation region B by photolithography. Using the buttered resist 26 as a mask, the polysilicon layer Then, dry etching is performed on the thin film 33 to form a stopper thin film 32 and a gate electrode 18 in the element forming region B, as shown in FIG. 3(d). At this time, by taking advantage of the difference in etching rate between the polysilicon layer 24 and the thin film 33 and setting the dry etching time to a longer setting time than before, the edge of the stopper thin film 32 can be etched more accurately than the gate electrode 18. It can be made to protrude to a predetermined length. At this time, since the resist 26 covers the entire surface of the element forming area A, the shapes of the gate electrode 8, 10, gate oxide film 9, and stopper thin film 31 in the element forming area A remain unchanged. After removing the resist 26, using the gate electrode 10.18 as a mask, a dose of I11 to 5x1013 [cm'-2] is applied to the entire surface of the P-semiconductor substrate 1 with an energy of about 50 keys.
] is implanted into the upper layer of the P-semiconductor substrate 1.
Add impurities. Subsequently, a film thickness of 1000 to 3000 was obtained using a vapor phase growth method.
A non-doped deposited film about the size of a human being is formed on the entire surface of the P'''' semiconductor substrate 1, and an oxide film 21.2 is formed on the non-doped oxide film.
Anisotropic etching is performed to remove the film thickness including 3. As a result, the non-doped oxide film remains on the side walls of the gate electrode 8, 10 and the gate oxide film 9, and the side wall of the gate electrode 18, which are thicker in the vertical direction with respect to the P-semiconductor substrate 1 than in other regions. As shown in the same figure (0),
While the side walls 11' and 19' are formed,
Gate oxide films 7 and 17 are formed. As shown in FIG. 4(a), the width L2 of the sidewall 19 provided on the sidewall of the conventional gate electrode 18 was approximately equal to the thickness m of the non-doped oxide film 35. On the other hand, the width L2 of the side wall 19 provided on the side wall of the gate electrode 18 in this embodiment is as shown in FIG. It is equal to the length added to the protrusion length k. Similarly, the width L of the side walls 11 and 11'
, also applies to L. That is, the width L of the sidewall 11' is equal to the sum of the thickness m of the non-doped oxide film 35 and the protrusion length of the stopper thin film 31. From the above, the stopper thin film 31.
2 protrusion length 1. Due to the difference in the formation width L
L2 can be set to different values with high accuracy. Although the stopper thin films 31 and 32 themselves are actually etched, there is no problem as long as a film having a low etching rate and sufficient etching resistance is used for the etching performed on the non-doped oxide film 35. After that, the gate electrode 10.18 and the sidewall 11
Using ', 19' as a mask, apply 30 to the entire P-semiconductor substrate 1.
~Dose 112~4X with energy around 40Ke
After implanting A8 ions of 1015 [cs-2],
By performing thermal diffusion treatment at 900° C. to 950° C., as shown in FIG.
N-diffusion regions 4.5.14.15 are formed under ', 19'. Moreover, P and As are annealed by this heat treatment. After that, although not shown, a smooth coat, contact holes, aluminum wiring, and a surface protection film are sequentially formed, and the EFROM
is completed. As mentioned above, the protrusion length 1 of the stopper thin film 31, 32
．． By changing k, the sidewalls 11', 19
The widths L and L of ' can be formed to different values with high accuracy. As a result, the optimal sidewall widths for the memory transistor Q1 and the peripheral transistor Q2, that is, the N-diffusion regions 4, 5, and 14.1
Since the formation width of 5 can be set, it is possible to obtain an EPROM with an LDD structure in which the operating characteristics of each transistor can be optimized. In this example, an oxide film was used as the material for the sidewall, polysilicon was used as the electrode material, and a silicon nitride film was used as the material for the stopper thin film, but the present invention is not limited to these. On the other hand, the etching rate ratio between the sidewall material and the stopper thin film material is about 3:1 or more, and the etching rate ratio between the electrode material and the stopper thin film material is 3:1 or more for etching for electrode formation. : It is sufficient if it is 1 or more. Further, in this embodiment, the gate electrode 10 of the memory transistor Q1 and the gate electrode 18 of the peripheral transistor Q2 are
Although they are formed by etching the same polysilicon layer 24, they may be formed by etching separate layers. Furthermore, although the peripheral transistor Q2 is shown to have an N-type MO8 configuration, it is also applicable to a P-type MO8 configuration. Furthermore, the present invention is applicable to all semiconductor devices having multiple types of LDD structure transistors on the same substrate. [Effects of the Invention] As described above, according to the present invention, in the first transistor, the gate electrode side wall portion has a first length corresponding to the first length that is the protrusion length of the mask layer with respect to the gate electrode.
Since the second transistor has a second width corresponding to the second length, the second transistor has a second width corresponding to the second length. Due to the difference in the protruding length of the mask layer from the gate electrode in the second transistor, the first. The formation widths of the gate electrode sidewall portions can be set to be different between the second transistors. As a result, the first semiconductor region formed under the side wall of the gate electrode is the first semiconductor region formed under the side wall of the gate electrode. Since the optimal formation width can be obtained between the second transistors, the first. This has the effect of making it possible to optimize the operating characteristics of each second transistor.

[Brief explanation of drawings]

Figure 11 shows the EPR of an LDD structure which is an embodiment of this invention.
2 is a sectional view showing the manufacturing method thereof; FIGS. 3 and 4 are explanatory views showing features of the present invention; FIG. 5 is a sectional view showing a conventional LDD structure EPROM; FIG. 6 is a cross-sectional view showing the manufacturing method thereof, and FIGS. 7 and 8 are graphs pointing out the problems of the conventional EPROM of LDD structure. In the figure, 1 is a P-semiconductor substrate, 3a and 13a are N
Source region, 3b, 13b are N Drain regions, 4, 5
, 14.15 is the N- diffusion region, 6°16 is the channel region, 7, 9.17 is the gate oxide film, 8, 10.18 is the gate electrode, 11' 19 is the sidewall center, 31.3
2 is a stopper thin film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Cause (Part 1) Figure 7 (Spontaneous) 1. Indication of the case Heiken Patent Application No. 1-81884 3. Representative of the person making the amendment 5. ``Detailed description of the invention column'' of the specification to be amended 6. Contents of the amendment (1) Page 11 of the specification Correct rl, 4 μmJ in line 18 to ro, 14 μm. (2) “2.0 μm” on page 12, line 7 of the specification,
ro, 20 μm”. that's all

Claims (2)

[Claims] (1) A semiconductor substrate of a first conductivity type, and first and second transistors formed on the semiconductor substrate, each of the first and second transistors having: a gate electrode formed through an insulating film; an end portion of the gate electrode formed on the gate electrode that protrudes a first length from the gate electrode in the first transistor; a mask layer protruding from the electrode by a second length; and a mask layer formed on both sides of the gate electrode and extending from the first
In the transistor, the first length corresponds to the first length.
a gate electrode side wall portion having a second formation width corresponding to the second length in the second transistor; and a gate electrode formed on the upper layer portion of the semiconductor substrate below the gate electrode side wall portion. a first semiconductor region of a second conductivity type with a low impurity concentration; and the second semiconductor region of the second conductivity type, which has a higher impurity concentration than the semiconductor region. (2) A method for manufacturing a semiconductor device in which first and second transistors are manufactured on a semiconductor substrate of a first conductivity type, the method comprising: forming an insulating film on the semiconductor substrate; , forming a first layer that will become a gate electrode of the first transistor; forming a second layer that will become a gate electrode of the second transistor on the insulating film; forming a third layer, which becomes a first mask layer and has a lower etching rate than the first layer in the first anisotropic etching, on the layer; and forming a third layer on the second layer. forming a fourth layer serving as a second mask layer having a lower etching rate than the second layer with respect to the anisotropic etching; 1 is anisotropically etched to form a gate electrode of the first transistor, and the end portion of the first transistor protrudes from the gate electrode of the first transistor by a first length due to a difference in etching rate. selectively performing the second anisotropic etching on the second and fourth layers to form a gate electrode of the second transistor, and forming a mask layer on the second and fourth layers; forming the second mask layer whose end portion protrudes from the gate electrode of the second transistor by a second length; and using the gate electrodes of the first and second transistors as a mask, the semiconductor implanting a second conductivity type impurity into an upper layer of the substrate to form a first semiconductor region with a low impurity concentration; and forming a gate electrode sidewall on the semiconductor substrate including the first and second mask layers. forming a fifth layer, wherein the fifth layer has a higher etching rate than the first and second mask layers for the third anisotropic etching, and the fifth layer has a higher etching rate than the first and second mask layers; The third anisotropic etching is performed on the fifth layer using the second mask layer as a mask, and the third anisotropic etching is performed on the fifth layer using the second mask layer as a mask.
and a first width of the first and second formed widths reflecting the second length.
and forming second gate electrode sidewall portions on both sides of the gate electrodes of the first and second transistors, respectively; and the gate electrodes of the first and second transistors and the first and second gates. using the electrode sidewall as a mask, implanting a second conductivity type impurity into the upper layer of the semiconductor substrate;
A method of manufacturing a semiconductor device, further comprising: forming a second semiconductor region having a higher impurity concentration than the first semiconductor region adjacent to the first semiconductor region.