JPS62229978A - Semiconductor device - Google Patents

Abstract

PURPOSE:To relax the field strength in the direction parallel to a channel at the end part of a high-impurity concentration drain region and to make larger the drain withstand voltage by a method wherein the high-impurity concentration drain region is formed in the semiconductor layer provided on the upper part of the low-impurty concentration drain region provided in a semiconductor substrate. CONSTITUTION:Low-impurity concentration source and drain regions 7 and 8 are formed in an Si substrate 1 and afterward, a B ion beam is implanted through a poly Si film 20 and a gate oxide film 4, which are formed on those regions, and a high-impurity concentration channel layer 14 is formed by performing a thermal annealing. Then, the two-layer film of the poly Si film and the oxide film is processed by a photo etching method and a gate electrode 15 and a gate protection insulating film 6 are formed. After that, an oxide film formed by a CVD method is etched and gate sidewall insulating films 9 are formed. Then, the poly Si film is grown by a CVD method and after a high-concentration As ion implantation and a high- temperature and short-time annealing are performed, the poly Si film is processed by a photo etching method and a source Si electrode 15 and a drain Si electrode 16 are formed. Lastly, an interlayer insulating film 12 is formed, a contact hole opening is performed and by forming Al electrodes 13, an MOSFET is completed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and in particular to an MO3 field effect transistor (hereinafter abbreviated as MOSFET).
The present invention relates to a semiconductor device suitable for application to an 8 integrated circuit (hereinafter abbreviated as MO3IC).

[Conventional technology]

As integrated circuits become more highly integrated, the MOSFEs that make up them
The channel length of T is becoming shorter and its length is about to become less than or equal to 1. When the channel length becomes less than 1, the electric field is concentrated between the highly doped source/drain region and the channel region.1 A drain breakdown voltage of 5V or more, which is required for normal MOS memory or logic, is obtained. things become difficult. For this reason, there was a problem in that it was difficult to miniaturize the element.

Conventional MOSFETs with an effective channel length of 14 or less
In order to enable operation with a 5V power supply, the L shown in Figure 4
DD (Lightly Doped Drain)
It has a high voltage MO8 structure called a ly Doped Drain) structure. (I.E.E., Transactions on Electron Devices, Volume ED-27, Number 8.1359-1
See page 367 (August 1980). ) This conventional LDD
A MOSFET having the structure is shown in FIG.

In FIG. 4, 1 is a p-type silicon substrate, 2 is a thick field oxide film for isolation between elements, 3 is a channel stopper layer, 4 is a gate oxide film, 5 is a gate electrode, and 6 is a gate protection insulating film. . 7 and 8 are n-type low impurity concentration source and drain regions formed by impurity introduction using the gate electrode 5 as a mask, 9 is a gate sidewall insulating film, and 10.11 is impurity introduction using the gate sidewall insulating film 9 as a mask. n-type high impurity concentration source and drain regions formed by
2 is a surface protection insulating film, and 13 is a source and drain electrode (wiring).

In this LDD structure MOSFET, the drain applied voltage is n-type low impurity concentration source and drain regions 7.8
Therefore, by arbitrarily controlling the width of this region during manufacturing, that is, widening it, the effective channel length can be reduced to 1t1.
Even in ultra-fine MO8FETs with a size of less than m, it is possible to achieve high breakdown voltages that do not cause avalanche even when a drain voltage of 5V is applied. Low impurity concentration source and drain regions7.
8 and the high impurity concentration source and drain regions 10 and 11 are different, so by widening the width of the gate sidewall insulating film 9, it is theoretically possible to increase the breakdown voltage to any extent possible. However, a part of the low impurity concentration source and drain regions 7.8 in the LDD structure is not covered with the gate electrode 5 as shown in FIG. 7.8 cannot be controlled by the gate voltage, that is, the low impurity concentration source and drain regions 7.8 not covered by the gate electrode 5 act as a series resistance.

As the widths of the low impurity concentration source and drain regions 7 and 8 are increased in order to increase the withstand voltage, the problem arises that the current driving capability is reduced. This problem negates the main purpose of miniaturizing semiconductor devices, which is high-speed operation.

Other problems with the LDD structure are the low impurity concentration source and drain regions and the high impurity concentration source and drain regions.
This is caused by the difference in the impurity introduction boundary of 0111.

That is, in the LDD structure, after forming the low impurity concentration source and drain regions 7.8 using the gate electrode 5 as a mask, the gate sidewall insulating film 9 is formed, and using the gate sidewall insulating film 9 as a mask, the high impurity concentration is formed. Source and drain regions 10.11 are formed. However, since the gate sidewall insulating film 9 is left behind by sputter etching, the controllability of its width is usually poor, and therefore the width of the low impurity concentration source and drain regions 7. It varies depending on. This results in variations in breakdown voltage characteristics and current drive capability between the source and drain, resulting in a problem of significantly lowering manufacturing yield.

In order to solve the problems of the MOSFET with the above-mentioned LDD structure, the present inventors first partially introduced impurities into the channel part of the MOSFET using a focused ion beam. We proposed a MOSFET and its manufacturing method that can shorten the length and obtain high current drive capability (Japanese Patent Application Laid-Open No. 59-61965).
.

FIG. 5 is a sectional view showing the main part configuration of a typical example of this MOSFET, p-type (100) plane, 10Ω·cII
1 silicon substrate 1, 20 nm thick gate oxide film 4.
Polycrystalline SL gate electrode with a thickness of 0.3I1m5. Arsenic (A
In the structure having highly impurity-concentrated source and drain regions 10 and 11 doped with s), a highly impurity-concentrated channel layer 14 is additionally formed using a focused ion beam. This high impurity concentration channel layer 14 is here:
A high concentration boron (B) implanted layer with a width of 0.14 was used. Note that 29 indicates a low impurity concentration channel layer.

By adding the high impurity concentration channel layer (high impurity concentration boron implantation layer) 14, the substantial channel length becomes equal to the width of the boron implantation layer, so the polycrystalline SL
Compared to the gate length represented by the width of the gate electrode 5, the effective channel length can be made much shorter. The reason for this is that instead of the conventional method of determining the gate length by photolithography or etching, a focused ion beam is used, and the width at the channel portion is 0.1. This is because the impurity concentration can be controlled in such a minute width.

However, as can be seen from FIG. 5, the gate electrode 5 covers not only the substantial channel region (high impurity concentration channel layer) but also the entire channel region, including the low impurity concentration channel layer. It was found that the capacitance between the gate electrode 5 and the high impurity concentration drain region 11 increased by about 40% compared to the conventional structure with the same gate length. The capacitance between the gate and drain needs to be small in order to operate the MOSFET at high speed. Fifth
In the structure shown in the figure, in order to reduce the capacitance between the gate and drain, the length of the low impurity concentration channel layer 29 should be made as short as possible, or the length of the gate electrode 5 should be made as short as possible.
The latter method is extremely difficult with the current microfabrication technology, in which the channel layer 14 must be provided only on the top of the high impurity concentration channel layer 14. Therefore, when we experimentally investigated the former method, we obtained the results described below.

In other words, the gate length of the drain breakdown voltage BVos (the length of the gate electrode 5), which is one of the important performances of MOSFET.
The dependence was investigated experimentally. In the experiment, the gate oxide film thickness was 2
An accelerating voltage of 30 keV is applied to the center of the channel of a MOSFET with a gate length of 0 nm and a gate length of 0.1 to 1.0-.

Beam diameter 0.1. A focused boron (B) ion beam of 0. M with an effective channel length of IIltm
Prototype OSFETs were manufactured, and each drain breakdown voltage BVos
was measured. As a result, it was found that when the gate length was shortened to 0.4° or less (naturally, the length of the low impurity concentration channel layer 29 was shortened), the drain breakdown voltage was sharply reduced. Numerical analysis of the cause of this revealed that the electric field strength in the boundary region between the high impurity concentration drain region 11 and the low impurity concentration channel layer 29 increases rapidly as the low impurity concentration channel length decreases due to the shortening of the gate length. was found to increase.

In this way, high-performance MO8F with the structure shown in Fig.
According to ET, by shortening the actual channel length, the problem of the conventional structure in which the current drive ability decreases with the miniaturization of semiconductor devices can be solved.
When an attempt was made to shorten the length of the low impurity concentration channel layer by shortening the gate length in order to reduce the capacitance between the drains, a new problem occurred in that the drain breakdown voltage suddenly decreased.

[Problems to be solved by the invention] As mentioned above, the conventional LDD structure MO with a fine channel length
In the 5FET, while it is possible to increase the drain breakdown voltage, there are problems such as a decrease in current drive capability and an increase in manufacturing variations in breakdown voltage characteristics, current drive capability, and the like.

Furthermore, in order to solve the above problems, the present inventors previously proposed. In high-performance MO8FETs, while it is possible to improve the current drive capability, if you try to shorten the length of the low impurity concentration channel layer by shortening the gate length to reduce the capacitance between the gate and drain, the drain There was a problem in that the breakdown voltage was significantly lowered.

The purpose of the present invention is to solve the problems of the conventional technology, and to provide a semiconductor with sufficiently high current drive capability, a small decrease in source-drain breakdown voltage, and a small gate-drain capacitance. The goal is to provide equipment.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a first conductivity type semiconductor substrate having a first conductivity type impurity doped region formed in a surface region and having a higher concentration than the semiconductor substrate.
a lightly doped region of a second conductivity type opposite to the first conductivity type formed in a surface region of the semiconductor substrate on both sides of the impurity doped region of the conductivity type; and at least the first conductivity type of the semiconductor substrate. a gate electrode formed on the impurity-doped region with an insulating film interposed therebetween; and a gate electrode formed on the second conductivity type low concentration impurity-doped region of the semiconductor substrate with an insulating film interposed on both sides of the gate electrode. It is characterized by having at least a highly impurity-doped semiconductor thin film of two conductivity types.

[Effect]

Numerical analysis of the characteristics of the MOSFET with the structure of the present invention revealed that unlike the conventional structure, the drain region with high impurity concentration is not formed in the semiconductor substrate, but is formed on top of the drain region with low impurity concentration provided in the semiconductor substrate. By forming a highly concentrated impurity in a doped semiconductor layer,
It has been found that the electric field strength in the direction parallel to the channel (direction from the low impurity concentration drain region toward the source region) at the end of the high impurity concentration drain region can be significantly relaxed, and the drain breakdown voltage can be increased.

The MOSFET of the present invention improves current drive capability by providing a highly impurity concentration channel layer, and also functions as an impurity concentration channel without substantially providing a high impurity concentration source or drain region in the semiconductor substrate. By providing a semiconductor layer doped with a high impurity concentration above the low impurity concentration source and drain regions, it was possible to improve the drain breakdown voltage and reduce the capacitance between the gate and the drain.

〔Example〕

FIG. 1 is a sectional view of a MOSFET according to a first embodiment of the present invention. In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a channel stopper layer, 4 is a gate oxide film, 5 is a gate electrode, 6 is a gate protection insulating film, 7.8
is n-type low impurity concentration (10"am-' or more 10"c++
9 is a gate sidewall insulating film, and 12 is an interlayer insulating film.

13 is an aluminum electrode (wiring), 14 is an n-type channel region with high impurity concentration, 15 is a source silicon region with high impurity concentration, and 16 is a drain silicon region with high impurity concentration. In addition, the source silicon electrode 15 and drain silicon electrode 16 having high impurity concentration have a diameter of 10" to ensure good ohmic contact with the aluminum electrode 13.
An impurity concentration of 101'cm-' or more is appropriate, and the low impurity concentration drain region 8 functions even if the channel depth is 101'cm-' or more.
A surface concentration of less than

In the MOSFET of this example, the current drive capability, that is, the drain current, under the voltage application conditions of 8V, drain voltage 5V, and gate voltage 5V is about 4.5A, and the same gate length (0 , 5#l1l) conventional structure M
Compared to O8FET, the drain breakdown voltage was approximately twice as high, and the capacitance between the gate and drain was reduced by approximately 40%. That is, the MOSFET of this embodiment can operate at high speed while maintaining the conditions for using a 5V normal power supply.

FIGS. 2(a) to 2(g) show the MOS of the second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of the FET.

First, as shown in FIG. 2(a), the p-type (100) plane,
1000℃, 2 on silicon substrate 1 of 10Ω・Cff1
An oxide film (thermal oxide film) 17 with a thickness of 20 nm was grown by dry oxidation for 0 minutes, and then chemical vapor deposition (Chemical Vapor Deposition) was performed.
A silicon nitride film 18 is grown to a thickness of 30 nm by an apor deposition method (hereinafter abbreviated as CVD method), and the silicon nitride film 18 other than the portion where a MOSFET is to be formed is removed by a photoetching method. Next, B ions were implanted onto the silicon substrate 1 in the portion where the silicon nitride film 18 was removed by a normal ion implantation method at an acceleration voltage of 70 kaV and an implantation amount of 3 x 10 cm-. Wet oxidation is performed at a temperature of 2 hours to form a field oxide film 2 with an n diameter of 0.6- and a channel stopper layer 3 below the field oxide film 2.

Next, as shown in FIG. 2(b), the silicon nitride film 18
Then, the oxide film 17 is removed, and a gate oxide film 4 with a thickness of 15 nm is grown by dry oxidation at 1000° C. for 20 minutes, and phosphorus (P) is diffused thereon using phosphorus oxychloride (POCN) as a diffusion source. (7) Polycrystalline 5ilpJ20 was grown by low pressure CVD method, layer resistance 20Ω/hole, thickness 0, 2tea, and this polycrystalline Si film 20
An oxide film 21 having a thickness of 30 nm+ is grown thereon by dry oxidation at 1000° C. for 30 minutes.

Thereafter, as shown in FIG. 2 (Q), a polymethyl methacrylate (PMMA) resist film 22 with a thickness of 0.5 mm is coated on the oxide film 21, and line width is increased by electron beam (FB) lithography processing. An opening 23 of 0.1 μs is formed. Next, after removing the oxide film 21 under the opening 23 by reactive sputter etching,
A high impurity concentration channel layer 14 was formed by implanting a 0 keV B ion beam 24 from the entire surface. The amount of ion implantation in this case is determined by the set value of the threshold voltage vth of the MOSFET, but in this example, in order to obtain a threshold voltage of 0.5V, ion implantation was performed with an implantation amount of 8X 1012c+m-''. .

Next, as shown in FIG. 2(d), the PMMA resist film 22 is removed by an oxygen (O2) plasma asher method. Then tungsten hexafluoride: / (WF,)
(7) A W film 25 is selectively deposited to a thickness of 50 nm only on the polycrystalline Si film 20 below the opening 23 by a CVD method using water (Ht) reduction. Next, the oxide film 21 is removed by etching, and the polycrystalline Si film 20 is anisotropically etched away using the W film 25 as a mask by reactive sputter etching to form the gate electrode 5.
An oxide film 26 having a thickness of 0.2 am is deposited by the method.

Next, the oxide film 26 is etched away by a reactive sputter etching method, and as shown in FIG. 2(8), the bottom width is 0.1. The gate sidewall insulating film 9 is left. After that, using the gate sidewall insulating film 9 and the W film 25 as a mask,
Phosphorus (CP) ions 27 with an acceleration voltage of 50 keV were implanted at an implantation amount of I x 10 "am-", and annealing was performed at 900° C. for 30 minutes to form low impurity concentration source and drain regions 7.
．． form 8.

Next, as shown in FIG. 2(f), an oxide film with a thickness of 0.2 t1m is formed by the CVD method, and processed by the photoetching method to form the gate protection insulating film 6. After that, C
A 0.3 um thick polycrystalline Si film is deposited by the VD method and processed according to the desired circuit configuration by the photoetching method to form the source silicon electrode 15 and drain.

An in-silicon electrode 16 is formed. Next, the acceleration voltage 70
Implant amount of 27 keV arsenic (As) ions 6XIO”
Ca1-" implantation and high-temperature short-time annealing at 1100°C for 30 seconds were performed to activate the implanted As. As is known, the diffusion coefficient of As in polycrystalline Si is the same as that in single-crystal silicon. As the diffusion coefficient is 10 to 20 times larger than that in However, the impurity distribution in the low impurity concentration source and drain regions 7.8 in the silicon substrate 1 is hardly affected.
A high impurity concentration layer having almost the same concentration as the uniformly distributed impurity concentration (2XIO "cl") in silicon substrate 1 is also formed on the surface of low impurity concentration source and drain regions 7. The junction depth of the high impurity concentration layer is extremely shallow, about 3 On, and does not pose any problem.

Finally, as shown in FIG. 2(g), a glabellar insulating film 12 is formed, contact holes are made, and aluminum electrodes (
A 1M05FET was completed by forming wiring (13).

The drain breakdown voltage of the MOSFET completed in the above process is approximately 6
．． 5V, which is more than twice as high as the drain breakdown voltage of 3V of the MOSFET with the conventional structure shown in FIG. 5 for the same gate length (0, 1, us). Also.

Under the voltage application conditions of drain voltage 5V and gate voltage 5V, the current drive capability, that is, the drain current, is about 5mA, which is almost the same as that of the conventional MO3FET. 6
Comparing the current drive capability with that of a conventional structure MOSFET (Fig. 5) with v, it has been improved by about 1.5 times, and the capacitance between the gate and drain has been reduced by about 30%. In the MO8FET structure based on the example, 5V
It was found that high-speed operation is possible while maintaining the conditions of normal power supply usage.

Note that instead of the W film 25 in this embodiment, a titanium (Ti) film with a thickness of 60 na+ was formed by sputtering.
It goes without saying that similar effects can be obtained by using a Ti silicide film in which unreacted Ti is removed by etching after thermal annealing at .degree. C. for 20 minutes.

Figures 3(a) to (c) are the MOSFETs shown in Figure 1.
This is a cross-sectional view showing the manufacturing process of , and each process will be explained below.

First, an oxide film with a thickness of 20 nm (not shown, see FIG. 2(a)) is formed on a p-type (100) plane, 10 Ω em silicon substrate 1 by dry oxidation at 1000° C. for 20 minutes.
Further, a silicon nitride film (not shown, see FIG. 2(a)) is grown to a thickness of 30 nm using the CVD method, and the silicon nitride film other than the portion where the MOSFET is to be formed is photoetched. 6th step to remove:
As shown in FIG. 3(,), B ions are implanted into the silicon substrate 1 in the portion where the silicon nitride film has been removed by an ordinary ion implantation method at an acceleration voltage of 70 keV and an implantation amount of 3X.
After driving under the conditions of 10"c+a-", 1000℃,
Wet oxidation is performed for 2 hours to form a field oxide film 2 of 0.6-thickness and a channel stopper layer 3 below it. Thereafter, the silicon nitride film and oxide film described above are removed by etching, and a gate oxide film 4 with a thickness of 10 nm is grown by dry oxidation at 1000° C. for 10 minutes.
Next, P ions with an acceleration voltage of 150 keV were implanted at a dose of 3
X 1013 cm-2 implanted, low impurity concentration source,
A drain region 7.8 is formed. After that, POC! l,
A polycrystalline Si film 20 doped with P and having a layer resistance of 20 Ω/gate and a thickness of 0.2 − is formed using as a diffusion source. Next, an acceleration voltage 9 is applied through the polycrystalline Si film 20 and the gate oxide film 4.
0keV, beam diameter 0. After implanting with IIM's focused B ion beam at an implantation depth of I
A high impurity concentration channel layer 14 is formed by thermal annealing at 00° C. for 20 minutes.

Next, as shown in FIG. 3(b), the polycrystalline Si film 2
After growing an oxide film with a thickness of 0.1 - on the gate electrode 5 by the CVD method, the two-layer film of the polycrystalline Si film and the oxide film is processed by the photoetching method to form the gate electrode 5 and the gate protective insulating film 6. form. After that, the thickness is 0 by CVD method.
．． After forming a 3 tm thick oxide film, etching is performed to form a gate sidewall insulating film 9. Next, the thickness is 0 by CVD method.
．． 3- polycrystalline Si was grown at an accelerating voltage of 70 keV.
After implanting As ions in an implantation amount of 6.times.10 "am-" and performing short-time annealing at a high temperature of 1100 DEG C. for 30 seconds, a source silicon electrode 15 and a drain silicon electrode 16 are formed by photo-etching.

Finally, as shown in FIG. 3(c), an interlayer insulating film 12 is formed, contact holes are made, and aluminum electrodes (
By forming wiring (13), the MOSFET was completed.

〔Effect of the invention〕

As explained above, according to the present invention, the current drive capability is sufficiently high and the degree of decrease in breakdown voltage is small.

Moreover, a semiconductor device with small capacitance can be provided. In particular, we can provide a MOSFET with a fine channel length that can operate with a normal power supply of 5V, has high current drive capability, and has reduced capacitance between the gate and drain by up to 40%. It is possible to achieve higher performance without impairing the high-speed operation of the MOSFET.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a MOSFET according to an embodiment of the present invention, FIGS. 2(a) to (g) are sectional views showing the manufacturing process of a semiconductor device according to the first embodiment of the invention, a) to (c) are cross-sectional views showing the manufacturing process of a semiconductor device according to a second embodiment of the present invention, FIG. 4 is a cross-sectional view of a MOSFET having a conventional LDD structure, and FIG. 5 is a cross-sectional view of a conventional high-performance MO8FET. FIG. 2 is a cross-sectional view showing a typical example of the configuration of the main parts. DESCRIPTION OF SYMBOLS 1...Silicon substrate 2...Field oxide film 3...Channel stopper layer 4...Gate oxide film 5...Gate electrode 6...
・Gate protection insulating film '7.8...Low impurity concentration source and drain regions 9・
...Gate sidewall insulating film 10.11-...High impurity concentration source and drain regions 1
2... Interlayer insulating film 13... Aluminum electrode (wiring) 14... High impurity concentration channel layer 15... Source silicon electrode 16... Drain silicon electrode 17. 19, 26... Silicon oxide film 18...Silicon nitride [20...Polycrystalline silicon film 21...Polycrystalline silicon oxide film 22...Resist layer 23...Opening portion 24...Boron ion beam 25...Metal film 27... Arsenic ion beam 28... Focused boron ion beam 29... Low impurity channel layer Patent attorney Junnosuke Nakamura 1P1 Figure 7--480,000 ---
Dore 4〉Silico>ta=? 2 Figure 27 --- Ri〉Ion Dome

Claims (1)

[Claims] 1. A first conductivity type impurity doped region with a higher concentration than the semiconductor substrate formed in a surface region of the first conductivity type semiconductor substrate, and a surface of the semiconductor substrate on both sides of the first conductivity type impurity doped region. a low concentration impurity doped region of a second conductivity type opposite to the first conductivity type formed in the region, and an impurity doped region of at least the first conductivity type formed in the semiconductor substrate via an insulating film. at least a gate electrode and a semiconductor thin film of a second conductivity type doped with a high concentration impurity formed on the low concentration impurity doped region of the second conductivity type of the semiconductor substrate with an insulating film on both sides of the gate electrode. A semiconductor device characterized by: