JPH0927556A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a MISFET whose high reliability is realized by making the speed of an operation fast and by enhancing a latch-up resistant property. SOLUTION: A triple well at an input/output part is constituted of a deep n-type well 6 whose impurity concentration is highest near the surface of a p-type semiconductor substrate 1 and of a shallow p-type well 11 which is formed on the main face of the semiconductor substrate 1 and whose impurity concentration is the highest near a part directly under a LOCOS oxide film 4. As a result, its impurity concentration is low near the surface of the semiconductor substrate 1, and its impurity concentration is high in the interior of the semiconductor substrate 1. Consequently, a parasitic capacitance between a heavily doped source-drain region 17 which is formed near the surface of the semiconductor substrate 1 and a well region is reduced, the resistance in the interior of the semiconductor substrate 1 becomes low, and the latch-up resistant property of a semiconductor integrated circuit device is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a MISFET (Meta
l Insulator Semiconductor Field Effect Transistor)
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having the above.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, an electric signal is input from a power source outside the chip to a semiconductor element in an input / output section inside the chip, and the circuit inside the chip is operated by receiving this electric signal.

However, when a voltage due to excessive fluctuations in the power supply voltage outside the chip or excessive noise such as linking is applied to the semiconductor element in the input / output section inside the chip, this voltage is applied to the semiconductor element of the internal circuit through the semiconductor substrate. This causes the malfunction of the semiconductor integrated circuit device.

As a method of preventing malfunction, the semiconductor diode characteristic is utilized to electrically separate the semiconductor element of the input / output section from the semiconductor element of the internal circuit so that excessive noise is generated inside the semiconductor element of the input / output section. There are triple wells that prevent transmission to the semiconductor elements of the circuit.

The triple well is opposite to a deep flat well having a conductivity type opposite to that of the semiconductor substrate, which is provided to a predetermined depth from the surface of the semiconductor substrate, and a deep flat well formed in the deep flat well. It consists of shallow flat wells of conductivity type.

The manufacturing process of the well region constituted by the flat well will be described below. First, as shown in FIG. 7, a silicon oxide film 20 is formed on the surface of the p-type semiconductor substrate 1 by a thermal oxidation process. Next, using a patterned photoresist (not shown) as a mask, phosphorus (P) ions are implanted into the semiconductor substrate 1 at high energy,
The photoresist is removed, and then thermal diffusion is performed for a first time at a high temperature for a long time to form a deep n-type well 6 in the semiconductor substrate 1 of the input / output section over a predetermined depth from the surface of the semiconductor substrate 1.

Next, as shown in FIG. 8, after depositing a silicon nitride film 21 on the semiconductor substrate 1, the silicon nitride film 21 is patterned using the patterned photoresist 7 as a mask.
Are etched, and then phosphorus ions for forming the shallow n-type flat well 22 are implanted into the semiconductor substrate 1 of the internal circuit.

Next, as shown in FIG.
Then, selective oxidation is performed to form a thick silicon oxide film 23 on the semiconductor substrate 1. Then, after removing the silicon nitride film 21, in order to form a shallow p-type flat well 24 in the semiconductor substrate 1 of the internal circuit and the deep n-type well 6 of the input / output portion with energy that does not penetrate the thick silicon oxide film 23. Boron (B) ions are implanted.

Subsequently, the second long-time thermal diffusion is performed at a high temperature to form the shallow n-type flat well 22 in the semiconductor substrate 1 of the internal circuit, the inside of the deep n-type well 6 of the input / output portion and the semiconductor of the internal circuit. A shallow p-type flat well 24 is formed on the substrate 1, a triple well is provided in the input / output portion, and p-type and n-type double wells are provided in the internal circuit.

Next, after cleaning the surface of the semiconductor substrate 1 to remove the silicon oxide film 20 and the thick silicon oxide film 23, a silicon oxide film (not shown) and a silicon nitride film (not shown) are formed on the surface of the semiconductor substrate 1. (Not shown) are sequentially formed,
A patterned photoresist (not shown) is used as a mask, and LOCOS (Local Oxidation of Silic
on) The silicon nitride film in the region where the oxide film 4 is formed is etched.

Then, as shown in FIG.
N near the surface of the semiconductor substrate 1 on which the OS oxide film 4 is formed
In order to form the type channel stopper region 9 and the p type channel stopper region 12, impurity ions are implanted into the semiconductor substrate 1 using a patterned photoresist (not shown) as a mask. Next, after removing the photoresist, selective oxidation is performed to form L on the main surface of the semiconductor substrate 1.
An OCOS oxide film 4 is formed.

A method for forming a flat well is described in Japanese Patent Application Laid-Open No. 56-43756.

[0013]

However, the present inventor has found that the triple well of the input / output portion formed by the flat well has the following problems.

That is, 3 formed by a flat well
The impurity concentration of the heavy well is as shown in FIG.
It becomes highest near the surface of the semiconductor substrate. For this reason, the parasitic capacitance between the source / drain regions and the triple well of the semiconductor element formed near the surface of the semiconductor substrate becomes large, and the operation speed of the semiconductor element becomes slow.

Further, if the impurity concentration of the triple well is increased in order to suppress the latch-up due to the parasitic bipolar, the parasitic capacitance is proportional to the 1/2 power of the well concentration. The increase of the parasitic capacitance between the triple wells becomes more remarkable.

Further, in order to form the triple well, it is necessary to perform two long thermal diffusion steps for forming the deep flat well and the shallow flat well, and further, the channel stopper region is formed by the flat well. However, there is also a problem that the manufacturing process becomes long.

It is an object of the present invention to source the MISFET,
(EN) Provided is a technique capable of realizing a well region capable of increasing the operating speed by reducing the parasitic capacitance between the drain region and the well region and improving the reliability by improving the latch-up resistance of the MISFET. Especially.

Another object of the present invention is to provide a technique capable of shortening the manufacturing process of the well region and the channel stopper region of the MISFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0020]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) the semiconductor integrated circuit device of the present invention has a well region formed by a first well having a conductivity type opposite to that of a semiconductor substrate and a second well formed inside the first well. The first well has a flat well with the highest impurity concentration near the surface of the semiconductor substrate, and the second well is a retrograde well with the highest impurity concentration in a region of a predetermined depth from the surface of the semiconductor substrate. Has been formed.

(2) Further, the semiconductor integrated circuit device of the present invention comprises a first well having a conductivity type opposite to that of the semiconductor substrate and a second well formed inside the first well. The first well has a well region, the first well has a highest impurity concentration on the surface of the semiconductor substrate, and the second well has an impurity concentration near the field insulating film formed on the main surface of the semiconductor substrate. Formed of the highest retrograde wells.

(3) Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, after forming a field insulating film on the main surface of a semiconductor substrate, the patterned first photoresist is used as a mask to oppose the semiconductor substrate. Then, impurity ions of the conductivity type are implanted into the semiconductor substrate, and then thermal diffusion is performed to form a first well in the semiconductor substrate. Then, using the patterned second photoresist as a mask, impurity ions of the same conductivity type as the semiconductor substrate or impurity ions of the conductivity type opposite to the semiconductor substrate are implanted into the first well with energy penetrating the field insulating film. Then, the second well is formed inside the first well.

[0023]

According to the above means, as shown in FIG. 11B, the impurity concentration is highest near the surface of the semiconductor substrate,
Since the flat well of the opposite conductivity type to the semiconductor substrate and the impurity concentration of the region of a predetermined depth from the surface of the semiconductor substrate have the highest impurity concentration and the retrograde well of the same conductivity type of the semiconductor substrate constitutes a triple well. A well region having a low impurity concentration near the surface of the semiconductor substrate and a high impurity concentration in a region of a predetermined depth from the surface of the semiconductor substrate can be obtained.

Therefore, the impurity concentration in the vicinity of the surface of the well region of the triple well structure is kept low, and the parasitic capacitance between the source / drain region and the well region can be reduced. Further, the impurity concentration inside the semiconductor substrate is increased, and the latch-up resistance can be improved.

Further, according to the above-mentioned means, the thermal diffusion process which was required twice for forming the deep flat well and the shallow flat well in the conventional triple well is performed once for forming the deep flat well. Can be reduced to times. Furthermore, since the channel stopper region is formed below the field insulating film at the same time when the retrograde well is formed, the step of forming the channel stopper region becomes unnecessary, and the manufacturing process can be shortened.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a sectional view showing the principal part of a CMOSFET according to an embodiment of the present invention. The deep n-type well 6 of the input / output section is formed as a flat well having the highest impurity concentration near the surface of the semiconductor substrate 1, and the shallow p-type well 11 of the input / output section and the internal circuit and the shallow n-type well 8 of the internal circuit are formed. , The retrograde well having the highest impurity concentration immediately below the LOCOS oxide film and the low impurity concentration near the surface of the semiconductor substrate 1.

Further, when the impurity ions are implanted into the semiconductor substrate 1 to form the shallow n-type well 8 or the shallow p-type well 11, the impurity ions are also implanted under the LOCOS oxide film 4, and the n-type is formed. The channel stopper region 9 or the p-type channel stopper region 12 is formed.

Next, a CMOSF which is an embodiment of the present invention
A method for manufacturing ET will be described with reference to FIGS.

First, as shown in FIG. 2, a silicon oxide film 2 is formed on the surface of a p-type semiconductor substrate 1 by thermal oxidation, and subsequently a silicon nitride film 3 is formed on the semiconductor substrate 1 by C.
It is deposited by the VD (Chemical Vapor Deposition) method. Next, the silicon nitride film 3 is etched by using a patterned photoresist (not shown) as a mask to remove the photoresist, and then the LOCOS oxide film 4 having a thickness of about 400 nm is selectively oxidized to form the LOCOS oxide film 4 on the main surface of the semiconductor substrate 1. Form on top.

Next, as shown in FIG. 3, after the silicon nitride film 3 is removed, a patterned thick film (for example, 2
5 μm) Phosphorus ions are implanted into the semiconductor substrate 1 using the photoresist 5 as a mask so that impurities are also introduced under the LOCOS oxide film 4. Next, after removing the photoresist 5, thermal diffusion at 1200 ° C. is performed for 3 hours to form a deep n-type well 6 in the input / output portion from the surface of the semiconductor substrate 1 to a predetermined depth.

Next, as shown in FIG. 4, in order to form a shallow n-type well 8, the patterned thick photoresist 7 is used as a mask so that the impurity concentration is maximized in the vicinity immediately below the LOCOS oxide film 4. For example, phosphorus ions are implanted into the semiconductor substrate 1 under the conditions of energy of 400 keV and dose of 1 × 10 ¹³ / cm ² . As a result, the shallow n-type well 8 and the n-type channel stopper region 9 having a high impurity concentration are simultaneously formed under the LOCOS oxide film 4 in the internal circuit.

Next, as shown in FIG.
And then to form a shallow p-type well 11,
Using the patterned thick photoresist 10 as a mask, boron ions are deeply n-doped under the conditions of, for example, energy of 200 keV and dose of 1 × 10 ¹³ / cm ² so that the impurity concentration is maximized immediately below the LOCOS oxide film 4.
It is injected into the mold well 6 and the semiconductor substrate 1. As a result, the shallow p-type well 11 in the input / output section and the internal circuit and the LO
A p-type channel stopper region 12 having a high impurity concentration is simultaneously formed under the COS oxide film 4.

Next, after removing the photoresist 10 and the silicon oxide film 2, the semiconductor substrate 1 is subjected to a thermal oxidation process.
A gate insulating film 13 is formed on the surface of the. After that, the gate electrode 14, the low concentration source / drain region 15, the side wall spacer 16, the high concentration source / drain region 17, the insulating film 18 and the metal wiring 19 are formed according to the conventional manufacturing method. CM of this embodiment
The OSFET is completed.

As described above, according to this embodiment, since the shallow n-type well 8 and the shallow p-type well 11 are formed by the retrograde well, the triple well and the internal circuit formed in the input / output portion are formed. The impurity concentration in the vicinity of the surface of the formed double well becomes low, and the parasitic capacitance between the source / drain region and the well region of the MOSFET can be reduced. Further, the impurity concentration inside the semiconductor substrate 1 is increased, and the latch-up resistance can be improved. Further, since the n-type channel stopper region 9 or the p-type channel stopper region 12 is formed simultaneously with the shallow n-type well 8 or the shallow p-type well 11, the manufacturing process can be shortened.

(Embodiment 2) FIG. 6 is a sectional view showing the principal part of a CMOSFET according to an embodiment of the present invention. The structure of the well region of the input / output portion (deep n-type well 6 and shallow p-type well 11) and the p-type well region of the internal circuit (shallow p-type well 11) is the same as that of the first embodiment, but the internal circuit is the same. The structure of the n-type well region is different from that of the first embodiment and is constituted by a deep n-type well 6 which is a flat well and a shallow n-type well 8 which is a retrograde well.

When the deep n-type well 6 is formed at the input / output portion in the first embodiment, phosphorus ions are also implanted into the n-type well region of the internal circuit to form the deep n-type well 6. Other manufacturing steps are performed in the same manner as in the first embodiment.

As described above, according to this embodiment, the n-type well region of the internal circuit is formed into the deep n-type well 6 and the shallow n-type well.
By forming the triple well including the type wells 8, the impurity concentration inside the semiconductor substrate 1 can be increased,
Latch-up resistance is improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0041]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, it is possible to form a well region having a triple well structure in which the impurity concentration near the surface of the semiconductor substrate is low and the impurity concentration inside the semiconductor substrate is high. It is possible to realize high speed of the MISFET by reducing the parasitic capacitance between the regions and high reliability of the MISFET by improving the latch-up resistance.

Further, according to the present invention, it is possible to reduce the heat diffusion process for a long time when forming the well region having the triple well structure, and the process for forming the channel stopper region is not necessary. The manufacturing process of the well region and the channel stopper region can be shortened.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 3 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device examined by the present inventor.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device examined by the present inventors.

FIG. 9 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device examined by the present inventor.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device examined by the present inventors.

FIG. 11 is a schematic diagram of impurity concentration distributions of a triple well formed by a flat well and a triple well formed by a flat well and a retrograde well.

[Explanation of reference numerals] 1 semiconductor substrate (p-type) 2 silicon oxide film 3 silicon nitride film 4 LOCOS oxide film 5 photoresist 6 deep n-type well (flat well) 7 photoresist 8 shallow n-type well (retro grade well) 9 n-type Channel stopper region 10 Photoresist 11 Shallow p-type well (retro grade well) 12 p-type channel stopper region 13 Gate insulating film 14 Gate electrode 15 Low concentration source / drain region 16 Sidewall spacer 17 High concentration source / drain region 18 Insulating film 19 Metal wiring 20 Silicon oxide film 21 Silicon nitride film 22 Shallow n-type flat well 23 Thick silicon oxide film 24 Shallow p-type flat well

Claims (7)

[Claims] 1. A first well having a conductivity type opposite to that of a semiconductor substrate, and a second well formed inside the first well.
A semiconductor integrated circuit device having a well region formed by the wells, the first well being a flat well having the highest impurity concentration near the surface of the semiconductor substrate, and the second well being the surface of the semiconductor substrate. A semiconductor integrated circuit device characterized by being a retrograde well having the highest impurity concentration in a region of a predetermined depth. 2. A semiconductor substrate having a field insulating film for insulating adjacent semiconductor element regions formed on the main surface thereof, and having a first well and a conductivity type opposite to those of the semiconductor substrate. A semiconductor integrated circuit device having a well region formed by a second well formed inside the well, wherein the first well is a flat well having the highest impurity concentration near the surface of the semiconductor substrate, The second well is a retrograde well having the highest impurity concentration immediately below the field insulating film. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step of forming a field insulating film on the main surface of the semiconductor substrate, the semiconductor substrate using the patterned first photoresist as a mask. A step of implanting impurity ions of the opposite conductivity type into the semiconductor substrate and then performing thermal diffusion to form a first well in the semiconductor substrate; and using the patterned second photoresist as a mask, the semiconductor substrate An impurity ion of the same conductivity type as that of the above or an impurity ion of the conductivity type opposite to that of the semiconductor substrate is implanted into the first well with energy penetrating the field insulating film, and a second ion is formed inside the first well. A method of manufacturing a semiconductor integrated circuit device including a step of forming a well. 4. A semiconductor substrate having a field insulating film for insulating adjacent semiconductor element regions, the first well having a conductivity type opposite to that of the semiconductor substrate, and the same conductivity type as the semiconductor substrate. A first well region formed by a second well formed inside the first well, a second well region formed by a second well having the same conductivity type as the semiconductor substrate, and the semiconductor A semiconductor integrated circuit device having a third well region constituted by a third well having a conductivity type opposite to that of a substrate, wherein the first well is a flat well having the highest impurity concentration near the surface of the semiconductor substrate. , The second well and the third well are retrograde wafers having the highest impurity concentration immediately below the field insulating film. Semiconductor integrated circuit device as a characteristic. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the step of forming a field insulating film on the main surface of the semiconductor substrate, the semiconductor substrate using the patterned first photoresist as a mask. A step of implanting impurity ions of the opposite conductivity type into the semiconductor substrate and then performing thermal diffusion to form a first well in the semiconductor substrate; and using the patterned second photoresist as a mask, the semiconductor substrate Implanting impurity ions of the same conductivity type into the first well and the semiconductor substrate with energy that penetrates the field insulating film to form a second well inside the first well and in the semiconductor substrate. , Using the patterned third photoresist as a mask, the impurity ions of the conductivity type opposite to the semiconductor substrate are removed from the field. A method of manufacturing a semiconductor integrated circuit device, comprising the step of implanting into the semiconductor substrate with energy penetrating an insulating film to form a third well in the semiconductor substrate. 6. A semiconductor substrate having a field insulating film for insulating adjacent semiconductor element regions, the first well having a conductivity type opposite to that of the semiconductor substrate, and the same conductivity type as the semiconductor substrate. A first well region formed by a second well formed inside the first well, a second well region formed by a second well having the same conductivity type as the semiconductor substrate, and the semiconductor A semiconductor having a fourth well having a conductivity type opposite to that of the substrate and a third well region having a conductivity type opposite to that of the semiconductor substrate and formed by a third well formed inside the fourth well. In the integrated circuit device, the first well and the fourth well are flat wells having the highest impurity concentration near the surface of the semiconductor substrate,
The semiconductor integrated circuit device according to claim 1, wherein the second well and the third well are retrograde wells having the highest impurity concentration immediately below the field insulating film. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the step of forming a field insulating film on the main surface of the semiconductor substrate and the patterned first photoresist as a mask are used. A step of implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate, followed by thermal diffusion to form a first well and a fourth well in the semiconductor substrate, masking the patterned second photoresist As the impurity ion of the same conductivity type as that of the semiconductor substrate is implanted into the first well and the semiconductor substrate with energy that penetrates the field insulating film, and the second ion is introduced into the inside of the first well and the semiconductor substrate. In the step of forming the well, using the patterned third photoresist as a mask, the impurity ion of the conductivity type opposite to that of the semiconductor substrate is used. A method of manufacturing a semiconductor integrated circuit device, comprising the step of injecting silicon into the fourth well with energy that penetrates the field insulating film to form a third well inside the fourth well.