JPS597229B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a novel MOS field effect transistor (hereinafter M
The present invention relates to a method of manufacturing an integrated circuit (hereinafter abbreviated as MOSIC) comprising a plurality of MOSFETs (hereinafter abbreviated as MOSFET) and a plurality of MOSFETs.

The basic cross-sectional structure of a conventional silicon gate MOSFET is as shown in FIG. In a portion surrounded by gate oxide film 3 and field oxide film 4, a source 5 and drain 6 of a conductivity type opposite to that of the substrate, for example, nf, are formed by thermal diffusion or ion implantation.

Therefore, the effective channel length L of the FET is calculated by subtracting twice the diffusion length l of impurities forming the source 5 and drain 6 portions in the lateral direction from the actual gate length L'L
The length is 2.e, which is smaller than the set value of the length on the mask or gate.

The size of the lateral diffusion length l is 8 times the diffusion depth Xj(7)O when formed by thermal diffusion, and 0.4 times when formed by ion implantation; As shown in FIG. 1, when wiring 7 using aluminum as the metal is used for the source 5 and drain 6 of the MOSFET, an aluminum-silicon eutectic is formed, and the source or drain 6 is The silicon in the drain part dissolves into aluminum, causing electrical contact between the substrate 1 and the aluminum wiring T, and the resulting MOSFET becomes inoperable. For this reason, the effective channel length 1, compared to the channel length L' on the mask, is 0.8 μm when at least the source and drain are formed by ion implantation, and when formed by thermal diffusion. It becomes shorter by about 1.6 μm. Furthermore, considering the element area, aluminum wiring 7
This is done through a contact hole made in the PSG film 8 (phosphorus silicate glass SiO2 (P2O5)) deposited on the field oxide film 4, so that the aluminum wiring 1 can properly contact the source 5 and drain 6 parts. requires a margin for mask alignment, making it difficult to reduce the device area.

Further, as described above, since there is lateral diffusion of impurities, it is difficult to reduce the element area and the isolation region between elements. In order to increase the speed of MOSFETs and MOSICs, it is generally effective to shorten the effective channel length L, and particularly to reduce the area of the source and drain portions, and further reduce the area of the overlapped portion of the drain and gate. be.

For this purpose, it is necessary to reduce the channel length L7 on the master, but for the reason mentioned above, the lateral diffusion length is large, so in order to make L the required value, the diffusion length l must be reduced. It is necessary to control accurately. Furthermore, the effective channel length L
As becomes shorter, the withstand voltage between the source 5 and drain 6 decreases due to the punch-through phenomenon, and the MOSF
It is not possible to apply the voltage necessary for ET and MOSIC operation, and the side effect of lowering the MOSFET threshold voltage VTH occurs, making it impossible to shorten the channel to increase speed. become. The problems of conventional MOSFETs and ~10SIC have been listed above, but to summarize again: 1) Because eutectic formation of aluminum and silicon occurs, the diffusion depth of the source and drain must be increased to at least about 1 μm or more.

2) For this reason, the channel length becomes at least 0.8 to 1.6 μm shorter than the designed value of the mass, making it difficult to operate with the designed characteristics.

3) Shortening the channel length, which is particularly important when increasing the speed of MOSFETs and MOSICs, becomes impossible due to the reduction in source/drain breakdown voltage and threshold voltage caused by the aforementioned effects.

4) It is necessary to drill contact holes in order to make electrical connections between the aluminum and the source/drain.
In order to prevent C from becoming inoperable, it is essential to increase the area of the source or drain of the junction.

For this reason, it is very difficult to reduce the element volume. Therefore, the capacitance of the diffusion layer cannot be reduced, making it difficult to increase the speed of the device. The present invention is applicable to the current MOSFET described below.
This was done in order to eliminate the drawbacks of the MOSIC manufacturing method, and eliminates the cause of defects due to the eutectic of aluminum and silicon, and also reduces the effective diffusion depth of the channel part to reduce the channel length to the design value. approximately equal to , which results in MOSFETs and MOs with short channel lengths.
The present invention provides a method for manufacturing a semiconductor device that prevents a decrease in source/drain breakdown voltage and a decrease in threshold voltage in an SIC, and further reduces the area of the element.

The present invention will be described in detail below based on examples. FIG. 2 to FIG. 5 are diagrams showing one embodiment of the present invention.
As shown in Figure 2, P type (100) resistivity 10Ω・?
A silicon single crystal substrate 11 is wet-oxidized at 1100°C to grow a silicon oxide film 12 to a thickness of 1 μm, the oxide film in the area where the MOSFET is to be formed is removed by photoetching, and then re-oxidized at 1050°C in dry oxygen. Then, the gate oxide film 13 is grown to a thickness of 1200 nm.
Polysilicon with a thickness of 5000× was deposited by the CVD method, and the gate 4 was formed by the photoetching method. The gate width is 8 μm and the channel length L/ on the mask is 8 μm. Next, as shown in FIG.
6 and at the same time a gate 14 made of a polysilicon layer.
was doped to be n-type, and a PSG layer 17 was further deposited by CVD. The conditions for implanting phosphorus ions are an acceleration voltage of 15
At 0kV1 implantation amount 1×1015/~, n+ diffusion layer 15
The surface resistance value is 150Ω/the diffusion depth is 0.15 μm. The deposition conditions for SC(G) Old 6 were as follows: 4% monosilane supplemented with nitrogen and 1% phosphine at a flow rate ratio of 20:1, the substrate temperature during deposition was 400°C, and the thickness was 8000A. As shown in FIG. 4, contact holes 18 are formed in the portions that are to become the source 15 and drain 16 by photoetching, and then POCI is inserted through the contact holes 18.
Deep diffusion layers 19, 2 are formed by a thermal diffusion method using , as a diffusion source.
0 was formed in the source region and drain region, respectively. The size of the contact hole is 8 μm×8 μm, the depth of the diffusion layer×j is 10 μm, and the surface resistance value is 20 Ω/hole. The diffusion layers 19 and 20 can also be formed by ion implantation. Next, as shown in FIG. 5, in order to electrically connect the deep diffusion layers 19 and 20 formed in the source and train to the outside of the semiconductor device through the contact hole 18 used for diffusion, aluminum 21 is deposited by vacuum evaporation. It was deposited to a thickness of 1 μm and removed by photoetching, leaving only the necessary portions. The MOSFET with the structure shown in FIG. 5 eliminates all the drawbacks of the conventional technology such as the aluminum-silicon eutectic problem, lower source/drain breakdown voltage, and lower threshold voltage, and reduces the device area. things become possible.

In this example, in a device with a channel length of 3 μm on the mask, it is possible to improve the source/drain breakdown voltage by 50%, the threshold voltage by 30%, and the device area by 30% compared to the device with the conventional structure. Ta. According to the present invention, not only the MOSFET shown in the embodiment but also a plurality of the MOS
It is clear that MOSICs made of FETs can also be manufactured and the same effect can be obtained. The present invention is particularly suitable for 5 μm
MOSFETs with short channels of less than
This is particularly effective when applied to OSIC.

It goes without saying that this method is also effective when manufacturing MOSICs with a high degree of integration, and the area for integrating the same circuit can be reduced by approximately 30% compared to MOSICs using conventional technology. . Furthermore, the operating time of the same circuit can be reduced by about 25% when compared with MOSIC using the prior art, and when used together with the effect of shortening the channel length, the operating time can be reduced to 1/2. The effects of the present invention are not only the significant reduction in device area and operation time as described above, but also the ability to control the withstand voltage and threshold voltage of MOSFETs, thereby increasing yield and reliability. It can be improved. As described above with reference to the embodiments, according to the present invention, MOSFETs and MOSICs with high characteristics that could not be achieved using conventional techniques can be manufactured by forming a shallow diffusion layer by implanting ions through a gate oxide film, and by forming a contact hole. forming a deep diffusion layer through
It can be manufactured by a process of obtaining a metal-diffusion layer contact in a self-aligned manner.

It goes without saying that the materials used in the present invention are not limited to those described in this embodiment, and may be, for example, n-type or (111) oriented silicon single crystals. It goes without saying that the temperature, atmosphere, etc. in each thermal process can be set to appropriate values by a skilled engineer.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a MOSFET having a conventional structure, and FIGS. 2 to 5 are views showing embodiments of the present invention. 11: Substrate, 12: Field oxide film, 13: Gate oxide film, 14: Gate conductor, 15: Source, 16: Drain, 17: PSG, 18: Contact hole, 19: Source contact, 20: Drain contact, 21 : Metal wiring.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device including the following steps: (1) A step of forming a shallow diffusion layer using a gate as a mask in a region on the surface of a semiconductor substrate where a source and a drain are to be formed. (2) Process of depositing an insulating film over the entire surface. (3) forming a contact hole in the insulating film to expose a part of the surface of the shallow diffusion layer; (4) Forming a deeper diffusion layer than the shallow diffusion layer through the contact hole.