JPS5642373A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5642373A JPS5642373A JP11757279A JP11757279A JPS5642373A JP S5642373 A JPS5642373 A JP S5642373A JP 11757279 A JP11757279 A JP 11757279A JP 11757279 A JP11757279 A JP 11757279A JP S5642373 A JPS5642373 A JP S5642373A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- film
- layer
- region
- deep
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000010410 layer Substances 0.000 abstract 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 2
- 239000011229 interlayer Substances 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 238000011109 contamination Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To avoid contamination of gate film in the semiconductor device by forming a deep diffused layer of impurity dope through a contact hole opened at an interlayer insulating film in an MOS semiconductor device having a deep source and drain diffused layers at far distance from a gate and shallow source and drain diffused layers at near distance therefrom. CONSTITUTION:A thick field SiO2 film 202 is formed on the periphery of an Si substrate 201, a thin gate SiO2 film 203 is coated on the substrate 201 surrounded thereby, and a polycrystalline Si layer 204 becoming the gate is formed at the center. Then, with the film 204 as a mask ion is implanted, and shallow source and drain regions 205 are formed, and an interlayer insulating film 206 is deposited on the whole surface including the region 205. Thereafter, a contact hole is opened at the film 206 at the position far from the gate layer 204, impurity is diffused therein, and a deep region 207 is formed in the region 205, and aluminum electrode 208 is covered thereon. Thus, the gate layer 204 may not be contaminated, and can be increased in density while reducing the number of steps of photoetching them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11757279A JPS5642373A (en) | 1979-09-13 | 1979-09-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11757279A JPS5642373A (en) | 1979-09-13 | 1979-09-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5642373A true JPS5642373A (en) | 1981-04-20 |
Family
ID=14715134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11757279A Pending JPS5642373A (en) | 1979-09-13 | 1979-09-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5642373A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60189267A (en) * | 1984-03-08 | 1985-09-26 | Nec Corp | Manufacture of mis field effect transistor |
| US4616399A (en) * | 1983-04-11 | 1986-10-14 | Nec Corporation | Method of manufacturing an insulated gate field effect transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5169985A (en) * | 1974-12-16 | 1976-06-17 | Hitachi Ltd | Handotaisochino seizohoho |
-
1979
- 1979-09-13 JP JP11757279A patent/JPS5642373A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5169985A (en) * | 1974-12-16 | 1976-06-17 | Hitachi Ltd | Handotaisochino seizohoho |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4616399A (en) * | 1983-04-11 | 1986-10-14 | Nec Corporation | Method of manufacturing an insulated gate field effect transistor |
| JPS60189267A (en) * | 1984-03-08 | 1985-09-26 | Nec Corp | Manufacture of mis field effect transistor |
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