JPS55102272A - Method of fabricating mos semiconductor device - Google Patents

Method of fabricating mos semiconductor device

Info

Publication number
JPS55102272A
JPS55102272A JP925979A JP925979A JPS55102272A JP S55102272 A JPS55102272 A JP S55102272A JP 925979 A JP925979 A JP 925979A JP 925979 A JP925979 A JP 925979A JP S55102272 A JPS55102272 A JP S55102272A
Authority
JP
Japan
Prior art keywords
layer
substrate
film
doped layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP925979A
Other languages
Japanese (ja)
Inventor
Junichi Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP925979A priority Critical patent/JPS55102272A/en
Publication of JPS55102272A publication Critical patent/JPS55102272A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain MOS semiconductor elements having different threshold values without a photomasking step by forming first channel doped layer on a substrate, forming second channel doped layer with the electrode of the first MOS element as a mask, and then forming the electrode of the second MOS element.
CONSTITUTION: An SiO2 film 12 is coated on a silicon substrate 10, impurity ion 14 is implanted through the film 12, and the first channel doped layer 16 is formed on the surface of the substrate 10. Then, the first gate electrode layer 24 of polycrystalline silicon is formed in predetermined region on the film 12. With the layer 24 and the exposed film 12 as masks ion 20 is implanted. Thus, the second channel doped layer 22 of different impurity density from other portion is formed on the other portion than the portion under the layer 24 while retaining the first doped layer 16 under the layer 24. Thereafter, the second gate electrode layer 26 of polycrystalline silicon is similarly formed on the layer 12 at the position isolated from the layer 24. A doped region 28 is formed in the substrate 10 not covered with the layers 24 and 26 by ion implantation process to obtain MOS semiconductor elements Q1, Q2 having different threshold values from each other.
COPYRIGHT: (C)1980,JPO&Japio
JP925979A 1979-01-31 1979-01-31 Method of fabricating mos semiconductor device Pending JPS55102272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP925979A JPS55102272A (en) 1979-01-31 1979-01-31 Method of fabricating mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP925979A JPS55102272A (en) 1979-01-31 1979-01-31 Method of fabricating mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS55102272A true JPS55102272A (en) 1980-08-05

Family

ID=11715418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP925979A Pending JPS55102272A (en) 1979-01-31 1979-01-31 Method of fabricating mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS55102272A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043856A (en) * 1983-08-22 1985-03-08 Toshiba Corp Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5411687A (en) * 1977-06-28 1979-01-27 Oki Electric Ind Co Ltd Manufacture for semiconductor integrated circuit
JPS5448179A (en) * 1977-09-26 1979-04-16 Hitachi Ltd Mis-type semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5411687A (en) * 1977-06-28 1979-01-27 Oki Electric Ind Co Ltd Manufacture for semiconductor integrated circuit
JPS5448179A (en) * 1977-09-26 1979-04-16 Hitachi Ltd Mis-type semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043856A (en) * 1983-08-22 1985-03-08 Toshiba Corp Semiconductor device

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