JPS6043856A - Semiconductor device - Google Patents

Abstract

PURPOSE:To imporve a short channel effect, lower punch-through voltage and enhance the controllability of the gate length of a transfer gate electrode while increasing capacitance and the degree of integration by bringing a substrate section in the vicinity of the transfer gate electrode to low impurity concentration. CONSTITUTION:An element isolation region 22 is formed to the surface of a P type Si substrate 21 through a selective oxidation method, and a gate insulating film 24, a transfer gate electrode 25 consisting of polycrystalline silicon containing an impurity and a first SiO2 film 26 are formed to a predetermined section on an island region 23 in succession. An oxide film 28' as a thick insulator film is left on the side walls of the gate oxide film 24, the transfer gate electrode 25 and the SiO2 film 26 through reactive ion etching to an oxide film 28. A polycrystalline silicon layer 30 is shaped on the whole surface, a capacitance electrode 31 is also formed on one part of the transfer gate electrode 25, and an N type diffusion region 33 in which a section in the vicinity of the transfer gate electrode 25 is shallow and has low concentration and other regions are deep and have high concentration is formed.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to improvements in semiconductor devices.

[Technical background of the invention and its problems]

Conventionally, in a semiconductor device, for example, a dynamic semiconductor memory having one capacitance and one switch transistor, the first
The one shown in the figure is known.

1 in the figure is, for example, a P-type semiconductor substrate, and an element isolation region 2 is formed on the surface thereof. An N+ layer 4 is formed on a predetermined surface of the island region 3 surrounded by the element isolation region 2. A capacitive electrode 5 is provided on the substrate 1 with an insulating film 6 interposed therebetween so that a portion thereof extends over the element isolation region 2. An S 102 film 8 is provided around the capacitor electrode 5 . A transfer gate electrode 9 constituting a part of a switching transistor is provided on the substrate 1 including a part of the breakdown layer 4 so as to partially extend over the capacitor electrode 5 with a gate insulating film 10 interposed therebetween. It is being

An interlayer insulating film 11 is provided on the entire surface including the transformer 7 add electrode 9 and the like. A contact hole 12 is provided in the interlayer insulating film 11 corresponding to a part of the first layer 4, and an extraction electrode 13 connected to the N+ layer 4 is provided in this contact hole 12.

However, although the semiconductor memory IC of the above-mentioned structure has the advantage of being integrated, the dart length (L) of the switching transistor is
Since the dart length is determined by the matching technique for the capacitor electrode 5, it is difficult to control the dart length, and it is not suitable for semiconductor memories having fine transistors.

Because of this, a semiconductor memory as shown in FIG. 2 has recently become known. That is, in this semiconductor memory, the transfer dart electrode 9' does not extend over the capacitance electrode 5, and the switching transistor is connected to N+l (on the surface of the island region 3).
It has a structure in which it is connected to the capacitor electrode 5 through the entire drain (drain) 14. In addition, in the case of such a structure, the N+ layer 4 is called a source. However, since the semiconductor memory shown in FIG. 2 has a structure in which the source and drain 4.14 are provided in the island region 3 at both ends of the dart, the capacity is small and the dart length is shortened to about 1.0 μm. If it is done,
This method has the disadvantage of increasing short channel effects.

In general, as a means to prevent the short channel effect of the shortest dart transistor determined by photolithography technology, the lateral diffusion that occurs when forming the source and drain (i.e., from the dirt edge to the It is effective to prevent the formation of an r-layer that diffuses inward.

For this reason, in recent years, arsenic with a small diffusion coefficient has been used as an n-type impurity by ion implantation, etc.
A method of forming a shallow bonding layer of 0.3 μm0 layer has been attempted. However, with this method, the shallow junction layer has a high resistivity and forms a direct resistance between the source and drain of the transistor, which is not favorable for operation.

Further, since the bonding layer can be used as an electrode wiring in some cases, the diffusion layer is not preferable because it delays signals. From this point of view, current semiconductor memories are comprehensively optimized, and in the N+ layer, for example, the junction depth is reduced to 0.3.
A value of μm1 specific resistance of 50Ω/mouth is adopted.

In addition, from the viewpoint of preventing the lateral diffusion of impurities and further preventing the short channel effect, although not shown in the figure, an insulator such as a SiO2 film is provided on the side wall of the transfer dart electrode as a mask during ion implantation. Measures are being taken to substantially prevent the spread of. However, according to this method, since the diffusion layer must be made completely deep to sufficiently cover the side wall portion, the dart length is 1.0.
A device shortened to approximately μn1 has the disadvantage that the through voltage of 4 inches between the source and drain regions is reduced. Furthermore, when the junction layer is shallow, that is, when the lateral diffusion length is short, there is a drawback that the channel region is separated from the source and drain by the sidewalls.

[Purpose of the invention]

The present invention has been made in view of the above circumstances.
The substrate portion near the adder electrode 9 is made to have a low impurity concentration to improve the controllability of the short channel effect, the reduction of the no-kunchi-through voltage, and the actual dart length of the transfer dart electrode, and the self-alignment of the capacitor electrode with the transfer dart electrode. The object of the present invention is to provide a semiconductor device ft'e- which can be formed to increase capacity and achieve high integration.

[Summary of the invention]

The present invention provides a semiconductor substrate of a first conductivity type, a transfer electrode provided on the substrate via a dirt insulating film, an insulating film thicker than the dirt insulating film formed on the side wall of the dirt electrode, and A capacitor electrode is provided on the substrate via an insulating film and a portion is provided on the dirt electrode via a thick insulating ♂V, and a capacitor electrode is provided on the substrate surface near the dirt electrode on the opposite side of the capacitor electrode. a low concentration first impurity layer of a second conductivity type; and a second conductivity type high concentration impurity layer provided adjacent to the first impurity layer on the substrate surface opposite to the capacitor electrode and away from the dirt electrode. The present invention is characterized by comprising the impurity layer described in item 2, and is aimed at achieving the above-mentioned object.

[Embodiments of the invention]

Hereinafter, a process for manufacturing an N-channel type semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 3(a) to 3(g).

[i) First, a multi-element isolation region 22 was formed on the surface of, for example, a P-type St substrate 21 by selective oxidation.

Note that the surface of the substrate 21 surrounded by this element isolation region 22 becomes an island region 23 (as shown in FIG. 3(,)).

Subsequently, a predetermined portion on the island region 23 is subjected to thermal oxidation and CVD.
Dirt insulating film 24 with a thickness of 200X, thickness 3 according to the law etc.
A transfer dart electrode 25 made of polycrystalline silicon containing impurities of 000X, and a first 8 with a thickness of 3000X.
102 films 26 were sequentially formed.

Next, as a 26'ft mask of the 5102 film, an n-type pure substance such as arsenic was applied to the surface of the island region 23 at an accelerating voltage (gp
, 3 (illustrated in Figure 1(h)). Furthermore, a ridge Pzs with a thickness of about 3000X was formed on the entire surface by CVD method (Fig. 3(c)
).

[11] Next, the oxide film 28 was etched away by anticentric ion etching (RIE) in a CF 2 /H 2 gas atmosphere, and the oxidized N,? 4
, ) (as shown in Figure 3(d)). Subsequently, a second 8102 layer 29 with a thickness of 100X was formed on the exposed island region 23 by a thermal oxidation method, and then a polycrystalline silicon layer 30'i with a thickness of 3000X was formed on the entire surface by a CVD method ( Third
Figure(,)Illustrated). Next, the polycrystalline silicon layer 30 is selectively etched away by photolithography, so that a portion of the polycrystalline silicon layer 30 extends over the element isolation region 22 and a first layer also extends over a portion of the transfer gate electrode 25. The capacitor electrode 3 extending through the SiO2 film 26 and the residual oxide film 28/
Note that the capacitor electrode 31 was formed in a self-aligned manner with respect to the transfer gate electrode 25. Furthermore, this capacitor electrode 3, the first 5i02 film 26 and the remaining oxide film 2
Arsenic is applied to the surface of the island region 22 as a mask at an accelerating voltage of 4
Ion implantation was performed at 0 kV and a dose of 1 x 10 /'crn to form a highly concentrated and deep N''W layer 32. As a result, the vicinity of the transfer dart electrode 2'5 was shallow and lightly doped, and the other regions were Deep and highly concentrated N-type diffusion region 3
After forming the CVD-sio□ film 34t on the entire surface (as shown in FIG. All 29 fully open contact holes 35 were formed in the SiO2 film 29. Thereafter, an extraction electrode 36 connected to the diffusion region 33 through the contact hole 35 was completely formed on the CVD-S i O 2 film 34 to manufacture a semiconductor memory (as shown in FIG. 3(g)).

As shown in FIG. 3(g), the semiconductor memory according to the present invention has a transfer dart on a predetermined portion of the island region 23 of the 81 substrate 21 surrounded by the element isolation region 22 via a dart insulating film 24'fc. An electrode 25 is provided, a capacitor electrode 3 is provided on the island region 23 so that a part thereof extends on the transfer dirt electrode 25 via the residual oxide film 28' and the first 5lO2 film 26, and the capacitor electrode A shallow and low concentration diffusion region 33 is formed on the surface of the island region 23 near the transfer gate electrode 25 on the opposite side from the diffusion region 31, and the other region is deep and high concentration.
It has a structure with

According to the present invention, the N-type layer 272 forming a part of the diffusion region 33 is provided on the surface of the island region 23 near the transformer 7 adder electrode 25 on the opposite side from the capacitor electrode 31. As a result, the through voltage can be lowered by ÷f, and the substantial gate length of the transfer electrode 25 can be completely controlled.

In addition, since the dart electrode 25 is used as a part of the switching transistor and is used as part of the total capacitance of the capacitor electrode 3, and the capacitor electrode 31 can be formed in a self-aligned manner with the transfer dart electrode 25, the capacitance can be reduced. It becomes possible to increase the number of devices and increase the integration of devices.

In the above embodiment, polycrystalline silicon was used as the material for the transfer dart electrode and the capacitor electrode. It's okay.

'Furthermore, in the above embodiment, an SiO2 film was used as the dirt insulating film and the insulating film provided between the St substrate and the capacitor electrode, but the invention is not limited to this.
A Ta205 film, a laminated film of these films, and a mixed film of these films may also be used.

Further, in the above embodiment, the case of an N-channel type semiconductor memory was described as the i1 semiconductor device, but the present invention is not limited to this, and can be similarly applied to a P-channel type semiconductor memory.〇 [Effects of the Invention] As detailed above, according to the present invention, short channel effects, reduction in punch-through voltage, and transfer dart voltage:
It is possible to provide a semiconductor device in which the gate length of the box can be controlled, and the capacity can be increased and the degree of integration can be increased.

[Brief explanation of drawings]

1 and 2 are sectional views of a conventional semiconductor memory, and FIGS. 3(a) to 3(g) are sectional views showing the steps of manufacturing a semiconductor memory device according to an embodiment of the present invention. 2 No.: St substrate (semiconductor substrate), 22: element isolation region, 23: island region, 24: dirt insulating film,
25... Transfer gate electrode, 26.29...
S i O2 film, 271.272. 32... N-type layer, 28... Oxide film, 28'... Residual oxide film (thick insulator layer, 30... Polycrystalline silicon layer, 3)... Capacitor electrode, 33... Diffusion region, 34...CVD-810
□Membrane, 35... Contact hole, 36... Extraction electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 8 Figure 3

Claims (3)

[Claims] (1) In a semiconductor device having at least one set of an MO8 capacitor and a transistor, a semiconductor substrate of a first conductivity type;
A transfer dart electrode provided on this substrate via a dirt insulating film, and a low concentration first impurity layer of a second conductivity type provided on the substrate surface near the dirt electrode on the opposite side to the capacitor electrode. , comprising a second impurity layer of a second dielectric type with a high concentration provided adjacent to the first impurity layer on the substrate surface opposite to the capacitor electrode and away from the dirt electrode. semiconductor device. (2) The semiconductor device according to claim 1, characterized in that polycrystalline silicon, a high melting point metal, or a silicide compound with a high melting point metal is used as a material for the dart electrode and the capacitor electrode. (3) SIO2 film, Si, N4 film, A
The semiconductor device according to claim 1, characterized in that it uses a T203 film, a laminated film thereof, and a mixture film thereof.