JPS58118141A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enhance integration in a DRAM of a single cross point structure by a method wherein the material used to build a capacity-generating element for a memory cell has a larger dielectric constant than the material used to build a capacity-generating element for a reference level generating cell. CONSTITUTION:A cell M is composed of FETQDM consisting of a P type substrate 1, N<+> layers 4, 5, SiO2 film 3, and poly-Si 7 (word line 8) and a capacity- generating element Cs consisting of a poly-Si 6, Si3N4 3a, SiO2 3b, and N<+> layer 4, and the layer 6 is grounded. A cell D is composed of FETQD1/D2 consisting of the substrate 1, N<+> layers 11, 12, SiO2 film 3, and Si 17 and 18 with an Al dummy word line 16 and discharge signal phiDC line 19 respectively connected thereto and a capacity-generating element Cds consisting of a poly-Si 15, SiO2 10, and N<+> layer 12. As for the dielectric constants of Si3N4 and SiO2 respectively constituting the active parts in Cs and Cds, the constant of the former is two times larger than that of the latter. The area occupied by Cds can therefore be reduced, resulting in the reduction in area of the memory cell, which satisfactorily cope with the enlarging of DRAM capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, particularly an insulating gate II field effect transistor (MIspg'r, MetalInsulator).
lator Sem1 conductor Fie
The present invention relates to a one-intersection type dynamic random access memory (hereinafter referred to as D-RAM) configured with ldEffect Transistor). In the current one-intersection type D-RAM, the capacity is approximately 172
A dummy cell (reference level generation cell) capacitor Cds is used. In this case, the memory cell and the gummies are connected to their respective capacitors C6,
In the interval Cd, the capacitance value is C as mentioned above.
In order to set B:Cdaζ2:1, conventionally, the same material such as SiQ or film was used for each cell as a dielectric layer, and the area ratio (i.e., the ratio of the area S of the capacitor C8 to the area Sd of the capacitor Cds) was adjusted. The ratio is approximately 2:1.

However, when trying to reduce the area occupied by a memory cell as the capacity of a D-RAM increases, the above-mentioned means for changing the area ratio has the following drawbacks.

That is, the area occupied by the memory array within one semiconductor substrate (semiconductor chip) is extremely large.

Further, within this memory array, the area occupied by the capacitor CB of the memory cell is extremely large, and this tendency becomes stronger as the capacity increases. therefore,
In order to reduce the chip size of D-RAM, especially when trying to reduce the capacitor C6 by mm5e, the area 8d of the capacitor Cds is further reduced due to the need to set the capacitance ratio to C8:Cd, S2:1 as described above. It has to be made smaller. However, compared to the rate of variation in the area S of the capacitor C8 due to manufacturing variations such as etching, the area of the capacitor C should be approximately half of that.
The fluctuation rate of 1kIfsIISd of dS becomes extremely large, making it impossible to obtain a capacitor Cds having a capacitance value approximately half that of capacitor C8. Therefore, capacitor Cs
There was a limit to how small the area could be, which hindered the ability to gather spears.

Therefore, an object of the present invention is to achieve high integration of a single-point type D-RAM.

Another object of the present invention is to provide a one-intersection type D-RAM that can be manufactured without increasing the number of steps in the manufacturing process.

In order to achieve these objects, according to the present invention, the dielectric constants of the dielectric films are made the same so that the areas of the capacitors of the memory cell and the dummy cell can be made almost the same.

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, with reference to FIG. 1, the circuit configuration of the one-intersection type D-EXAM common to each embodiment will be explained.

In this figure, for simplicity, one memory cell M-CE
L and dummy cell (reference level generation cell) D-CEL are connected to a pair of word lines W and tummy word lines DW, and a complementary theta line pair I). Each cell is connected. M-
CEL includes a memory capacitor C8 for storing charges corresponding to the logic value of a logic signal, and a transfer MISFBTQM whose gate receives a word signal and is connected to sense amplifiers S and A via data lines. It is made up of. On the other hand, a dummy cell (reference level generation cell') D-CgL serves as a standard for level comparison with M-CEL.
is a capacitor Cd having a capacitance value approximately half that of C6 above.
s, receives a dummy word signal at the gate and receives data 41.
j! A transfer MI8FET QD1 connected to the sense amplifiers S and A via D, and an M18FET QD used to discharge the charge of the cd& described above form an S. As shown in the figure.

Complementary data line pair in I)-R and AM of l-intersection method.

D extends from the sense amplifier 8A in opposite left and right directions. Therefore, the memory cells and the corresponding dummy cells are provided spaced apart from each other on the left and right sides of the sense amplifier.

Next, regarding the M-CBL in FIG.
The structure of the first embodiment of the EL is shown in FIG. In the figure,
1 is a p-type semiconductor substrate, 2 is a relatively thick insulating film (hereinafter referred to as field insulating film), 3 is a third gate insulating film, 3a is a dielectric film with high electroconductivity, 4 and 5 are N+ type semiconductor regions, 6
7 is a first polycrystalline silicon layer, 7 is a second polycrystalline silicon layer,
8 is an aluminum layer, 9 is a thin first gate insulating film (8t
o*membrane).

MISFET QM4;t in one u-CFiL, its substrate, source region, drain region, gate insulating film and gate electrode are the above-mentioned P type semiconductor substrate 1, N+ type semiconductor region 4, N+ type conductor region 5, They are each composed of a third gate insulating film (8i0.@) 3 made of semiconductor oxide and a second polycrystalline silicon layer 7. The second polycrystalline silicon layer 7 is connected, for example, to the aluminum layer 8 as the word line W shown in FIG. N+ type semiconductor region Jt25 is data I! Used as D.

On the other hand, in the storage capacitor C6 in the M-CEL, one electrode, the dielectric layer, and the other electrode are the first polycrystalline silicon layer 6, the insulating film (semiconductor oxide film 3, that is, the first gate insulating film 9, and the semiconductor nitride film 3). A two-layer insulating layer 11 made of material 3a, ie, Si and N4jl, and an N+ type semiconductor region 4 are respectively constructed.

The upper electrode (first polycrystalline silicon layer 6) of this capacitor C8 is . Connected to D.

FIG. 3 shows one D-CEL in FIG. 1.
Indicates CEL @ construction. In FIG. 3, 10 is the second gate insulating M (840! film), 11-13 are N-type conductor regions, 15 is the first polycrystalline silicon layer, 17 and 18 are the second polycrystalline silicon layers, 16 and 19 indicates an aluminum layer.

I) The MISFET QD in the -CEL has a substrate, a train region, a source region, a gate insulating film, and a gate electrode that are composed of a P-type semiconductor substrate 1, an N+-type semiconductor region 11, an N+-type semiconductor region 12, and a third gate insulating film. 8 IOt#
) 3 and a second polycrystalline silicon layer 17, respectively. This second polycrystalline silicon layer 17 is
For example, it is connected to the aluminum layer 16 as a dummy war (DW) shown in FIG. 1)-M in CEL
Ii9FETQD.

The substrate, drain region, source image region, gate insulating film, and gate electrode are P-type semiconductor substrates 1. N” type semiconductor region 13, N+ type conductor region 12, third gate insulating film (8i
Q, film) 3 and second polycrystalline silicon>, 11.18, respectively. A discharge signal φdc shown in D-GEL in FIG. 1, for example, is applied to the polycrystalline π silicon layer 18 from the aluminum layer 19.

L) - The capacitor Cds in CEL has one electrode, a dielectric layer and the other electrode connected to the first polycrystalline silicon region 12.
Each is composed of: This capacitor Cds
The upper electrode (first polycrystalline silicon layer 15) is vDD
connected to.

As described above, in the capacitor C in the M-CEL, 8i, N, which has a high dielectric constant of 7 to 8, is used as the dielectric layer that essentially acts as a capacitor, and in the capacitor Cd5 in the D-CEL, 8i, N, which has a high dielectric constant of 7 to 8, is used. In this case, SiQ, which has a relatively low dielectric constant of 35 to 4, is used as a dielectric layer that essentially acts as a capacitor.
is used.

These capacitors are designed to have approximately the same area.

FIG. 4 is a schematic diagram for explaining the layout pattern of memory cells and dummy cells.

The layout pattern of the mass and memory cell portions will be explained. The field insulating film 2 is arranged more or less regularly, as shown by solid lines and dotted lines, in order to define the data line and the capacitor cs made of the N+ type semiconductor region 5.

The first polycrystalline silicon layer 6, which is the upper electrode of the capacitor c6, is configured as a common electrode for all the capacitors C8 connected to two adjacent data lines, as shown by the solid line and the dashed line. A voltage supply 4IvDD-L&:w! made of aluminum is provided through a contact hole CH opened in an interlayer insulating film (not shown). It continues.

As a result, a voltage DD is applied to the second polycrystalline silicon layer 6. The second gate electrode of MI8FBTQM
The polycrystalline silicon layer 7 is regularly and repeatedly arranged in a polygonal pattern as shown by solid lines and two-dot chain lines.
A contact hole CH opened in an interlayer insulating film (not shown).

Word 58 (W) made of aluminum through CH,
is connected to. These aluminum wirings extend perpendicularly to the data lines made of semiconductor regions.

On the other hand, in the dummy cell portion, the field insulating film 2 is formed so that the capacitance of the capacitor cd is c8 ml/2.
In order to define the area of d, power is distributed as shown by solid lines and dotted lines. The first polycrystalline silicon layer 15, which is the upper electrode of the capacitor CD, is a common electrode for two capacitors Cds connected to two adjacent data lines, as shown by a solid line and a dashed line, and further It is also continuous with the first polycrystalline silicon layer 6 in the memory cell portion.

Therefore, the voltage ■DD is applied to the first polycrystalline silicon layer 15.
is applied. The second polycrystalline silicon 117 and 18, which are the gate electrodes of MISFET QD1 and QDs, are arranged as shown by the solid line and the two-dot chain line,
A dummy word $16 (DW) made of aluminum and a signal 1119 (φ
dc''. Also, the N+ conductor region 13 is connected to the ground potential @V8.-L via contact holes CH,,CH, and the N+ lid semiconductor region 1
1 is connected to the semiconductor region 5 which is a data line.

Next, the manufacturing process of the D-RAM of this embodiment will be explained in detail with reference to FIGS. 5A to 5Q. In each figure,
I is a process cross-sectional view of the memory cell shown in Figure 2, X is a process cross-sectional view of the dummy cell shown in Figure 3,
It is a process sectional view of ISFET. Note that X is X, -X in FIG.

The cross section is X! The same <xv

(A. Oxide film and oxidation-resistant film forming step) As shown in FIG. 5A, an oxide film 102 and an insulating film that does not allow oxygen to pass through, that is, an oxidation-resistant film 103, are formed on the surface of the semiconductor substrate 101. Semiconductor substrate xot, aluminum! 11o
2&hik oxide film 1 o * As a preferred specific material, P-type nest crystal silicon having (100) crystals (8
i) A substrate, a silicon dioxide (8+01) film and a silicon nitride (8i,N,) film are used, respectively.

The 8+Otill 02 is formed to a thickness of about 50 OA by surface oxidation of the 81 substrate 101 for the following reason. That is, 8isN, the film 103 is directly
When formed on the surface of the substrate 101, the 8i substrate 101 and S
i. Due to the difference in thermal expansion coefficient from that of the N4 film 103, crystal defects are caused on the surface of the Si substrate 101. To prevent this, a Si, N film 102 is formed on the surface of the 8+ substrate 101 before the Si, N, film 103 is formed. On the other hand, Si, N,
The film 103 is formed by, for example, CVD (
Chemical Vapor Deposition
) method to a thickness of approximately 140 OA.

(B. Selective removal of oxidation-resistant film and ion implantation step) First, an etching mask is used to selectively remove 8i3N and M2O3 on the surface of the Si substrate 101 where a relatively thick insulating film, that is, a field insulating film is to be formed. A photoresist 1l1104 is selectively formed on the surface of the N4 film 103 as a photoresist. In this state, exposed portions of the Si, N, and film 103 are removed by, for example, plasma etching, which allows for highly accurate etching. Next, the surface of the 81 substrate 101 on which the field insulating film is formed [+C] A layer of conductivity type opposite to that of the substrate.
An impurity having the same conductivity as that of the substrate, that is, a P-type impurity, is introduced into the 8i substrate 101 through the exposed SjO film 102 while leaving the 4. Ion implantation is preferred as a method for introducing this P-type impurity.

For example, poron (B) ions, which are P-type impurities, are implanted into the Si substrate 101 with implantation energy of 75 Kev.

The ion dose at this time is 3×10'' atoms/cIi.

(C. Field Insulating Film Forming Step) A field insulating film 105 is selectively formed on the surface of the 8i substrate 101. That is, as shown in FIG. 5C, after removing the photoresist film 104, the surface of the Si substrate 101 is selectively oxidized by thermal oxidation using 8i, N4I 1103 as a mask, and an 8i0. A film 105 (hereinafter referred to as field 8iQ, film) is formed. During the formation of the field Sin, @105, the poron ion implanted with tI is stretched and diffused into the 8i substrate 101, and a P reversal prevention layer (not shown) having a predetermined depth is formed as the field Sin, film 105. It is formed directly below.

(D, oxidation-resistant film and oxide film removal process) Field 870. In order to expose the surface of the 8i substrate 101 where the film 105 is not formed, 5L3N4
The film 103 is removed using, for example, hot phosphoric acid (H3P0.) solution. Subsequently, the 5101 film 102 is removed using, for example, a HF solution, and as shown in FIG.
The surface of the i-substrate 101 is selectively exposed. The planar shape in this state is shown in FIG. 6A.

(E, first gate insulating film forming step) A first gate insulating layer 130 is shown in FIG. Form it like this. That is, by thermally oxidizing the exposed surface of the 8i substrate 101, a thin oxide film with a thickness of about 5 OA is formed on the surface.

CF, nitride film formation process) In order to obtain the dielectric layer of capacitor C8 in M-CE L, a 8i, N, film 131 was deposited on the entire surface as shown in Fig. 5F.
It is formed to a thickness of 00 to 500A. This 8i, N film as a dielectric layer is formed to make the dielectric constant different from that of the dielectric layer (8iQ, film) of the capacitor Cds in the dummy cell.

(G, N+ type semiconductor region formation process) N+ type semiconductor regions are formed on the thin substrate electrodes of the capacitor in the memory cell and the capacitor in the dummy cell. A photoresist film 132 is formed on the entire surface, and the photoresist in the portions that will become the capacitor CB of the memory cell and the capacitor portion of the dummy cell is removed by photo processing. Subsequently, by ion-implanting the remaining photoresist (as a mask) with an N+ impurity, for example, arsenic, an N+lI conductor region 133 is formed on the surface of the 8i substrate in the capacitor portion of the memory cell and the capacitor portion of the dummy cell, as shown in FIG. 5q. form.

(H, dummy cell nitride film removal process) The photoresist film 132 used in the above process G is removed,
Newly selectively formed photoresist film area (X,
), the Slo! and N4 films 131 are selectively etched away, and then the Slo! 4.X in FIG. 5H by removing ll130.

Part S' substrate 101 and its adjacent field insulation 1
Expose the ilj105 surface.

C1, second gate insulating film forming step) D-CELfr-exposed SI of the part to be formed (X,)
A capacitor Cds in the D-CEL is placed on the surface of the substrate 101.
A second gate insulating film 109 is formed to obtain a porcelain shell layer. That is, by performing thermal oxidation, as shown in FIG. 51, an oxide film 1()9 having a thickness of about 40 OA is formed on the exposed Si substrate surface of D-CELI@S. This thermal oxidation simultaneously produces M-CE as shown in FIG.
The 8i, N surfaces of the portion (X,) forming the L and the portion (X,) forming the peripheral circuit are oxidized to form a thin oxide film 35 with a thickness of about 40λ.

(J, doffing of first conductor layer) In order to obtain one electrode of the capacitor in M-CEL and D-CEL, a polycrystalline silicon layer as the first conductor layer 107 is formed by CVD method as shown in FIG. 5J. Like SL board 101
Formed over the entire surface.

The thickness of this polycrystalline silicon layer is about 4000A. The polycrystalline silicon layer 107 formed on the M-CEL is 8i,N with a thin oxide film 135 interposed therebetween.

Deposited onto membrane 131. In order to reduce the resistance value of polycrystalline silicon layer 107, an N-type impurity such as phosphorus is introduced into this polycrystalline silicon by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer 107 is approximately 16Ω10.

Subsequently, 8i0. ! l1136 thickness 4000~
Formed to 5,000 people.

(K. Selective Removal of First Conductor Layer II) In order to form the first conductor layer, that is, the first polycrystalline silicon layer 107 into a predetermined electrode shape, the insulating film 136 is removed by photo-etching as shown in the figure. The first polycrystalline silicon layer 107 including
is selectively removed and left as electrodes 108 and 108B of the capacitor in M-CWL and D-CEL. -1
As a method for selectively removing the polycrystalline silicon layer 107, plasma etching is preferred since it allows for highly accurate etching. The planar shape in this state is shown in FIG. 6B.

(L. Polycrystalline silicon layer surface oxidation @4) 8i0. Membrane 1
Polycrystalline silicon layer 10 exposed with 36 attached
8 (side YjjJ of the polycrystalline silicon layer 108) is surface oxidized to form a 8iQ layer 137 as an interlayer insulating film of the capacitor portion, as shown in FIG. 5L.

(M, nitride film removal step) A portion where MI8FETQM in M-CEL is to be formed, a portion where MISF'ETQD□ in D-CEL is to be formed, and MI8FE of the peripheral circuit should be formed. Part 8i0. llll! 130,135,Si,
The N4 film 131 is selectively etched away to expose that portion of the substrate 101 as shown in FIG. 5M.

(N, 3rd game F insulation expansion forming process) M-CEL, 1)-CEL and MI in the peripheral circuit section
In order to obtain a gate insulating film for the SFET, a third gate insulating film 110 is formed on the exposed surface of the Sl& plate 101 as shown in FIG. 5N. That is, by thermally oxidizing the exposed surface of the 8i substrate 101, the third
A gate insulating film 110 is formed on the surface. Therefore, the third gate insulating film is 8i0. It's from.

Next, in order to define the threshold voltage of the MISFET in this state, the third gate SIO! PI impurities are introduced into the substrate surface through the film 110 by ion implantation.

For example, boron (B) is used as the P-type impurity. The implantation energy is 75Ke. The dose of t' ions is 2.4.
X l O'' atoms/cIi are preferred.

(0, Formation step of second conductor layer) A polycrystalline silicon layer is grown on the entire surface by CVD method,
After introducing phosphorus and reducing its resistance value as mentioned above,
Each polycrystalline silicon layer 138, 1 is patterned by photo-etching to serve as a second conductor layer as shown in FIG.
39 and 140, respectively. These layers are approximately 35 mm thick
00^, and functions as a gate electrode of each MISFET.

The planar shape of FIG. 50 is shown in FIG. 6C.

(P, source and drain region formation process & MISFET
As shown in FIG.
Introduced into the substrate 101. Ion implantation is preferred as a method for introducing this Nl impurity. For example, arsenic ion t]
It is implanted into the Si substrate 101 with an implant energy of 80 KeV. The ion dose at this time is lX10+e atoms/It.

(Q, interlayer insulating film and aluminum wiring formation process) Si
An interlayer insulating film is formed over the entire surface of the substrate 101.

That is, as shown in FIG.
G) A film is formed on the entire surface of the St substrate 101. This PSG
The membrane 118 also serves as a getter for natocran (Na) ions that have an unfavorable effect on the characteristics of the MISFET.

Contact holes (CH in FIG. 4,
-CH,) is formed.

Next, in order to planarize the PEG film 118,
The PSG film 118 is heat-treated at a temperature of 0.00C. The arsenic impurity ion-implanted by this heat treatment is stretched and diffused into the N+ type semiconductor region 1 having a predetermined depth.
19 to 122 are formed. These N''ll semiconductor regions become source/drain regions.

Next, a third conductive layer, for example, an aluminum layer with a thickness of 12000λ, is formed over the entire surface of the Si substrate 101. Subsequently, this aluminum layer is selectively etched to form aluminum interconnections 118, 16, 19, . . . corresponding to FIGS. 2 and 3, as shown in FIG. 5Q. This planar shape is equal to the shape shown in FIG.

In the manner described above, the dynamic random access memory of the present invention is completed.

It will be understood that the one-intersection method D-)tAM described in detail above has the following remarkable advantages.

(1) The degree of integration can be improved.

As the dielectric of the capacitor C6 of the memory cell, an 8i, N4 film with a relative permittivity of 7 to 8 is mainly used, and as the dielectric of the capacitor Cd8 of the tammy cell, an 8i, with a relative permittivity of 35 to 4 is used.
By using N and 8 r Ot Wi4, which is about 1/2 that of the film, it is possible to maintain the capacitance ratio of C8 and Cds at 2 volumes and to make the areas of both approximately the same. As a result, it is possible to significantly reduce the difference in the rate of variation (or variation) of both areas due to variations in manufacturing conditions that cannot be avoided in the kyosetsu process, and also eliminate the restriction imposed by Cd5 on the reduction of the area of C6. For this reason,
The area of C6 can be reduced to about 172 compared to the conventional area. By reducing the area of C6, which occupies a large portion of the memory array,
The memory array, which occupies 50 to 60 times the chip area, can be made smaller, improving integration efficiency.

+21 The capacitor can be stabilized using the 1II manufacturing process.

According to the present invention, it is possible to prevent the polycrystalline silicon layer from being deposited directly on the 8iJNd film of the capacitor Cs. That is, in order to alleviate the thermal strain caused by the difference in thermal expansion coefficient between the polycrystalline silicon layer and the SL and N4 films, the Si and N4 films are thermally oxidized to form a thin SiQ film on their surfaces, and at the same time, the D-C
ll of capacitor cds in EL! SiQ, which is an electric layer
, forming a film.

Further, an independent process for this purpose is not necessary, and stable C8 can be obtained without increasing the number of processes.

Next, a second embodiment of the present invention will be described with reference to FIGS. 7 to 10.

According to this embodiment, the memory cell structure (see FIG. 2) according to the first embodiment described above is modified as shown in FIG. 7. Other configurations such as the dummy cell structure are the same as in Example #11.

That is, in the storage capacitor C8 in the M-CEL, one Wt electrode, the M electric layer, and the other electrode are made of a first polycrystalline silicon layer 6a, an insulating film (mainly a semiconductor nitride 3a, that is, a high dielectric constant). It is formed of Si3N, II oxide and the second polycrystalline silicon layer 6b.Therefore, the above-mentioned first
In the example and PIll, capacitor C6 in M-CEL
8i, N, which has a high dielectric constant of 7 to 8, is used as a dielectric layer that substantially acts as a capacitor, and D-C
The capacitor CD in the EL is made of a dielectric layer having a relatively low dielectric constant of 35 to 4, 810. is used. These capacitors are designed to have approximately the same area. Moreover, C
6 is formed of a laminate of polycrystalline silicon -8i, N, -polycrystalline silicon. Note that an oxide film 3b is formed on the surface of the N4 layer 3a, and a thin SiO film 3c is formed on the surface of the polycrystalline silicon layer 6b.

The capacitor C6 having such a laminated structure is shown in FIGS.
It is created using the steps shown in Figure I.

First, the steps shown in FIGS. 5A to 5D described above are carried out in the same manner, and then the following steps are sequentially carried out to complete the device.

(A. First insulation film forming step) In the state shown in FIG. 5D, the exposed substrate surface is heat treated in an oxidizing atmosphere to form a first insulation film with a thickness of 750A
Grow 0. And the part that forms the memory cell (
The first insulating layer 3I240 of the capacitor C8 part in the capacitor C8 part in the dummy cell forming part (X, ) and the capacitor Cd51' in the part (X, As shown in the figure, that portion of the 8i substrate 101 is exposed.

This first insulating film serves as a mask for forming an N#M semiconductor region under the capacitor Cg"ds.

(B. Step of Deposition of First Conductor Layer) As the first conductor layer for forming the lower electrode of the capacitor C8 of the memory cell, a thickness of 1000A to 2000A is applied over the entire surface.
A first polycrystalline silicon layer 241 is formed by, for example, a CVD method. Thereafter, N+ source semiconductor regions are formed on the substrate side electrodes of the capacitors in the memory cells and the capacitors in the dummy cells. That is, using the first insulating film 240 under the first polycrystalline silicon layer 241 as a mask, N + m impurities, such as arsenic, are ion-implanted (implantation energy is K).
eV, dose amount lXl0” atoms/d)!?)
, as shown in Figure 118B, N is applied to the surface of the 8i substrate in the capacitor part of the memory cell and the capacitor part of the tammy cell.
A + type semiconductor region is formed. This arsenic ion implantation also reduces the resistance value of the first polycrystalline silicon layer 241.

(Selective removal of C1 first conductor layer and nitride film formation process) In order to give the first polycrystalline silicon layer 241 a predetermined shape and shape, the first polycrystalline silicon layer 241 is removed by photo-etching as shown in FIG. 8c. selectively removes capacitor C
s electrode 241 as a person. As a method for selectively removing the first polycrystalline silicon layer, plasma etching is preferred because it allows for highly accurate etching. The planar shape in this state is
Shown in the figure.

Next, in order to obtain the dielectric layer of capacitor C8, as shown in FIG.
Formed to a thickness of 0OA. This St, N4 layer 242 is formed to make the dielectric constant different between the capacitor Cda and the dielectric body (S t otll ). In addition,
In this process, the arsenic introduced into the substrate surface is stretched and diffused to form "1 semiconductor region 243, which becomes the lower electrodes of capacitors Cll and Cds.

(D. Dummy cell 8i, N, film removal process) Using the newly formed photoresist film as a mask, the 8i, N4 film in the dummy cell formation area (X!) is selectively removed by etching, and then the same area is removed. By removing the first insulating film 240, the 8i substrate 101 in the Xt portion and the field insulating film 105 in the vicinity thereof are
expose the surface.

(E, first gate insulating film forming step) The exposed Si base [10] of the portion (X, , ) where the D-GEL is to be formed. A film 244 is formed. That is, by performing thermal oxidation, an oxide film 244 having a thickness of about 400 Å is formed on the exposed surface of the 8i substrate of the dummy cell 16 (X,) as shown in FIG. 8E. As a result of this thermal oxidation, as shown in FIG. A film 239 is formed.

(F, second conductor layer deposition process) Capacitors C8 and Cd in memory cells and dummy cells
In order to obtain the upper electrode s, a second polycrystalline silicon layer 245 as a second conductor layer is formed to a thickness of 4000λ over the entire surface of the 81 substrate 101 by CVD. The polycrystalline silicon layer 245 formed on the memory cell is deposited on the 5AIN411242 through a thin oxide film 239. In order to reduce the resistance value of the second polycrystalline silicon layer 245, 8 g of impurity, for example phosphorus, is introduced into this polycrystalline silicon by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer is approximately 16Ω/hole. After this, an etching process was performed using the photoresist film as a mask.

The second polycrystalline silicon layer 245 is selectively removed, and the
As shown in the figure, a 2' polycrystalline silicon layer 245A, which will become the upper electrode of the capacitor C6 of the memory cell, and a second polycrystalline silicon layer 245B, which will become the upper electrode of the dummy cell capacitor Cds, are formed.

(G, nitride film removal step) Using the photoresist film pattern from the previous step as is,
Exposed S10. Membrane 239 and 5llN4 membrane 24
2 is removed by etching. Furthermore, using the same photoresist film as a mask, the newly exposed first polycrystalline silicon layer 241A is removed by etching to form the shape shown in FIG. 8G. As a result, the diagonally shaded portion of the first polycrystalline silicon layer 241A, which had a shape as shown in FIG. 9, is etched and removed. Note that the flat surface of the second polycrystalline silicon layer 145
The hl shape is the same as 108A in FIG. 6B.

Therefore, the final shape of the first polycrystalline silicon layer 241 is determined by the shape of the second polycrystalline silicon layer 245, and the etched edges of both sides match because they are etched using the same mask. do. Therefore, it can be said that the capacitance l of the capacitor Cs is determined by the shape of the second polycrystalline silicon layer 245A, and as in the conventional case,
Errors in alignment between the pattern of the field insulating film and the pattern of the first polycrystalline silicon layer, which is the upper electrode of capacitor C6, or etching of the oxide film for forming the first gate insulating film, which is the dielectric of capacitor C6. There is no variation in the capacitance of C8 due to variations in .

(H, first insulating film and first gate insulating film removal step) Furthermore, using the photoresist film pattern 4- as a mask,
All exposed first insulating films 240 (thickness 750λ
) and the first gate insulating film 244 (thickness: 40 OA) are removed by etching, and the substrate 1 is removed as shown in FIG. 8H.
01 is exposed.

As this etching means, in order to prevent the surface of the substrate 101 from being etched, etching using 7r7a, which has an etching action on 8iQ and does not work on silicon, is preferable.

(1. Second gate insulating film formation step) M-CEL, D-CEL and MI in the peripheral circuit section
In order to obtain a gate insulating film for the SFET, a second gate insulating film 246 is formed on the exposed surface of the 81 substrate 101 as shown in FIG. 18I. That is, by thermally oxidizing the exposed surface of the 81 substrate 101, a second gate insulating film (SiQ film) 246 having a thickness of about 500 AI7) is formed on the surface. At the same time, an oxide film (8iQ) is also formed on the surface of the second polycrystalline silicon layer.

A film) 247 is formed to a thickness of 1000 to 1500A.

The subsequent steps are carried out in the same manner as shown in FIG.

According to the memory cell structure shown in FIG.
In addition to the advantages mentioned in the embodiment, the following significant advantages are obtained.

(The degree of accumulation can be increased in 11 history.

Since C6 has a stacked structure of polycrystalline silicon-81 and N4-polycrystalline silicon, C6 can be formed over the field 8iQ film, making effective use of the bird's beak area and the field, and reducing the device area accordingly. It is possible to achieve even higher integration by making the device smaller.

(2) The capacitance ratio of C6 and Cds can be achieved almost as designed.

Conventionally, in order to form C6 and Cds dielectric layers, it was necessary to remove the oxide film existing on the substrate surface in advance. Due to this variation in the etching at the bird's beak portion, the areas of the C8 and Cds dielectric layers vary greatly. However, if C6 has a laminated structure as in the present invention, this problem will not occur, and C6 can have a customer volume value almost as designed.

Furthermore, variations in the area of C8, which has a large capacity per unit area, are suppressed by laminating C8. Therefore, the capacitance ratio between 06 and Cds can be made almost as designed.

(3) Information inversion caused by α rays can be reduced.

By reducing the area of CB, the incidence probability of α rays is reduced, and since C6 has a sandwich structure of polycrystalline silicon, neutralization of the N-type inversion layer by holes generated by α particles does not occur. Since there is no such thing, information inversion caused by alpha rays can be significantly reduced.

(4) It is easy to form aluminum wiring.

FIG. 10 shows a cross section of this embodiment, which corresponds to the -7-Yil fracture in FIG. 810. Since it extends over the film, the surface of the interlayer insulating film 10 on both C8s which are close to each other can be made into a relatively wide flat surface. Therefore, it is possible to easily make contact between the third polycrystalline silicon layer 7 and the word line 8, and the contact is
If you are at the top, you will not be subject to as many positional restrictions.

Next, a third embodiment of the present invention will be described with reference to FIGS. 11 to 13.

In this embodiment, the M-CEL is configured as shown in FIG. 7, and the capacitor of the D-CEL is also configured as shown in FIG. It has a laminated structure of 15b. Therefore, each of the capacitors M-CEL and 4' has a laminated structure of polycrystalline silicon, and the former is made of 8i, N, which has a high dielectric constant of 7 to 8, and the latter has a dielectric constant of 3.5. .about.4 int and 5 int having a relatively low dielectric constant are used as dielectric films, respectively, and are formed in approximately the same area.

The one-intersection type D-)CAM having both cells is created as follows.

(A. First polycrystalline layer photo-etching and nitride film deposition step) First, after performing the steps up to FIG. 8B of the second embodiment described above to deposit the first polycrystalline silicon layer 241 on the entire surface, In order to make the polycrystalline silicon layer 241 into a predetermined electrode shape,
The first polycrystalline silicon layer 241 is formed by photo-etching.
is selectively removed and left as electrodes 241A and 241B of capacitor C6 and Cds, as shown in the diagram.

As a method for selectively removing the first polycrystalline silicon layer, plasma etching is preferred because it allows for highly accurate etching. The planar shape in this state is shown in FIG.

Next, in order to obtain the dielectric layer of capacitor C8, the 12th A
As shown in the figure, the CVD method is used to coat the entire surface with St, N, and film 2.
42 is formed to a thickness of 400A.

This Si, N film 242 is formed to equalize the dielectric constant between it and the dielectric layer (Sin film) of the capacitor Cds.

Note that in this process, the arsenic introduced into the substrate surface is stretched and diffused, and N becomes the lower electrode of capacitor C6 and Cds.
A + type semiconductor region 243 is formed.

(B, dummy cell 8i, N, film removal process) Using the newly formed photoresist film as a mask, the 8i, N, film 242 of the dummy cell forming area X is selectively removed by etching, as shown in FIG. 12B. Then, X, s of the first polycrystalline silicon layer 241B, the first insulating film 240, and the surface of the field insulating film 105 in the vicinity thereof are exposed.

(C, rmi-1'le (7) 8iQ, film forming process Ii ri D
- A capacitor Cds in a dummy cell is placed on the exposed surface of the first polycrystalline silicon layer 241B of the CEL forming part (X,).
A second insulating film (8i0. film) 24 is used to obtain a dielectric layer of
form 4. That is, as shown in FIG. 12C, a dummy cell? ! On the surface of the exposed first polycrystalline silicon layer 241B of 6(X!), a fist suppuration (8jQ, film) 244 having a film thickness of about 4.0 OA is formed by thermal oxidation of the surface. This thermal oxidation simultaneously oxidizes the surface of the 8i3N film 242 in the memory cell forming area (Xl) and the peripheral circuit forming area (Xs), as shown in FIG. 12c.
A thin oxide film 239 having a thickness of about 4 OA is formed.

(D, second conductor layer deposition process) Memory cell and dummy cell capacitors C6 and Cds
In order to obtain the upper electrode, a second polycrystalline silicon layer 245 as a second conductive layer is formed over the entire surface of the substrate to a thickness of 4000 mm by CVD. The polycrystalline silicon layer 245 formed on the memory cell is made of Si and N via a thin oxide film 239.

11242. 112 polycrystalline silicon layer 2
In order to reduce the resistance value of 45, an N-type impurity such as phosphorus is introduced into this polycrystalline silicon by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer is approximately 16Ω/hole. After that, the second polycrystalline silicon layer 245 is selectively removed by etching using the photoresist film as a mask.
As shown in FIG. 12D, a second polycrystalline silicon layer 245A, which will become the upper electrode of the capacitor C8 of the memory cell, and a second polycrystalline silicon layer 245B, which will become the electrode, are formed on the capacitor Cds of the dummy cell.

(E, C6 and Cds patterning process) The photoresist film pattern from the previous process is used as is, and the 8+0. The film 239 and the first insulating film 240 are removed by etching. Furthermore, using the same photoresist film as a mask, the newly exposed first polycrystalline silicon layer 241
A and 241B were removed by etching, and the 12th Ew
Shape as shown in i. As a result, the hatched portions of the first polycrystalline silicon layers 241A and 241B, which had the shape shown in FIG. 13 in plan view, are etched and removed. Note that the second polycrystalline silicon layer 24
The planar shapes of the five persons and 245B are the same as those of 108A and 108B in FIG. 6, respectively. Therefore, the final shape of the first polycrystalline silicon layers 241A and 241B is
The etching is determined by the shapes of the polycrystalline silicon layers 245A and 245B, and the etched ends of both are coincident because they are etched using the same mask. therefore,
It can be said that the capacitance of the capacitors C8 and Cds is determined by the shape of the second polycrystalline silicon layers 245A and 245B.
There are no variations in the capacitance of C6 and Cds due to alignment errors with the pattern of the polycrystalline silicon layer or variations in etching of the oxide film for forming the first gate insulator M, which is the dielectric of the capacitors C8 and Cds. .

Furthermore, using the same photoresist film pattern as a mask,
All 8i0 exposed! Remove the film by etching,
As shown in FIG. 12H, the substrate 101 is exposed. As the etching means, it is preferable to use etching using heptase, which has an etching effect on SiQ but does not work on silicon, so that the exposed surface of the substrate 101 is not etched.

(F. Gate insulating film formation process) M-CBL, D-CEL and MI in the peripheral circuit section
In order to obtain a gate insulating film for the SFET, a gate insulating film 246 is formed on the exposed surface of the 8i substrate 101 as shown in FIG. 12F. That is, by thermally oxidizing the exposed surface of the 8i substrate 101, a gate insulating film (8102 film) 46 having a thickness of about 50 OA is formed on the surface. At the same time, an oxide film (8i Q, film) 247 is also formed on the surface of the second polycrystalline silicon layer 245.
is formed to a thickness of 1000 to 1500A.

Since the subsequent steps are the same as those shown in FIG. 5N and subsequent steps described above, the explanation thereof will be omitted.

The one-intersection type D-RAM according to the third embodiment has the following advantages in addition to the advantages described in the second embodiment.

(1) It becomes easier to design both capacitors.

The capacitance of both C and Cds depends on the alignment of the second polycrystalline silicon layer with respect to the first polycrystalline silicon layer. That is, a portion of the first polycrystalline silicon (Mll+7) is etched again to determine the pattern of the second polycrystalline silicon layer. In this re-etched portion, the patterns of C6 and CdS are constricted and not sandwiched, so that fluctuations in each capacitance itself due to one misalignment can be reduced. Besides, C8 and Cds
Since both of the L lower electrodes are formed through the same process, fluctuations in the capacitance ratio due to misalignment can be reduced. Therefore, the capacity ratio of 08 and Cds can be realized as designed.

(2; Information inversion caused by α rays can be reduced.

By making the area of C6 smaller than before, the incidence probability of α rays is reduced, and CS and Cd5 are
Since it has a sandwich structure of polycrystalline silicon, the N-type inversion layer is not neutralized by holes generated by α particles, so information inversion caused by α rays can be significantly reduced.

Note that, based on the technical idea of the present invention, the above-described embodiment can be further modified as follows.

In the second and third embodiments described above, the capacitance of the capacitor C8 is determined by the first polycrystalline silicon layer and the second polycrystalline silicon layer, and the shape of the field insulating film is Therefore, the shape of the field insulating film in the memory cell part does not have to be the pattern shown in FIG. It can be changed arbitrarily as long as it has the desired shape.

Also, since an N+ type semiconductor region is provided under the capacitor C6 and Cds regions, a voltage Vs8 (ground potential) is applied instead of ■DD to the second polycrystalline silicon layer which is the upper electrode of C8 and Cds. You can also.

Moreover, materials other than those mentioned above may be used as the electrode material and dielectric material of the capacitor. In addition, silicon-aluminum alloy, molybdenum,
Heat-resistant metals such as tungsten, chromium, tanker, etc. or their silicides may be used, or a laminate of these and a polycrystalline silicon layer may be used as the conductor layer. Further, each of the above-mentioned transfer MISFETs may be of a P-channel type, and may be, for example, a P-channel MISFET provided in an N-type well formed in a P-type substrate. In this case, it is desirable that the peripheral circuit be formed of N-channel MISFETs.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention; FIG. 1 is a circuit diagram of the main part of a single-point type dynamic random access memory common to each embodiment, and FIG. FIG. 3 is a perspective cross-sectional view showing the structure of a 1 m dummy cell according to the first example, and FIG. 4 is a layout pattern of the first real ma memory cell and dummy cell. Figures 5A to 5Q are process cross-sectional views of the manufacturing process of the l-intersection type random access memory according to the embodiment @1, and Figures 6A to 6C are 5
Figures A to 5Q are plan views of some processes, Figure 7 is a perspective cross-sectional view of a memory cell according to the second embodiment, and Figures 8A to 8I are one-intersection method according to the second embodiment. 9 is a cross-sectional view of the manufacturing process of the random access memory, FIG. 9 is a plan view of the process of FIG. 8C, and FIG.
11 is a cross-sectional view corresponding to the cross section formed by th
Slanted surface L111zA diagram of the dummy cell according to Example 3~
FIG. 112F is a cross-sectional view of the manufacturing process of a one-intersection type random access memory according to the third embodiment, and FIG. 13 is a plan view of the process of FIG. 12A. In addition, in the symbols shown in the drawings, Qyl + Qp 1
+QD1...MISFET; CB, Cd,...
Capacitor = M-GEL...Memory cell; D-CEL
...Dummy cell; 3...Gate insulating film; 3a...
High dielectric film; 3b. 3 c ”' 8 jO* N , 6.6a,
6b, 15, 15a, tsb. 17.18... Polycrystalline silicon layer; 8, 16.19.
...It is an aluminum layer. i,j,',',+14・- Figure 2 Figure 3/r

Claims (1)

[Claims] 1. It has a memory cell and a reference level generation cell, and
In a semiconductor memory device configured to be used as an intersection type dynamic random access memory, the dielectric film of the capacitor of the memory cell is made of a dielectric material having a higher dielectric constant than the dielectric film of the capacitor of the reference level generation cell. A semiconductor memory device characterized by: