FR2519461A1 - SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE - Google Patents

Abstract

THE INVENTION CONCERNS A SEMICONDUCTOR MEMORY DEVICE AND A PROCESS FOR ITS MANUFACTURING. THE DEVICE INCLUDES M-ARY NETWORKS OF M-CEL MEMORY CELLS CONTAINING A MISFET Q TRANSISTOR AND A C CAPACITOR, D-ARY FICTITIOUS NETWORKS INCLUDING EACH OF THE D-CEL FICTITIOUS CELLS PROVIDING A REFERENCE LEVEL AND CONTAINING A CONDENSER MISFET TRANSISTORS Q, Q, THE CAPACITORS C HAVING CAPACITIES LOWER THAN THOSE OF THE CAPACITORS C, AND

Description

The present invention relates to a semiconductor memory device

and more particularly a

  D-RAM memory (dynamic memory direct or random access

  field) constituted by MISFET transistors (metal-insulator-semiconductor field-effect transistors). Similarly, the invention relates to a method of manufacturing

  such a semiconductor memory device.

  Hereinafter, the prior art will be described.

  In a current D-RAM memory, for

  the data memorized in the capacitor C of a

  In the case of memory "1" or "O", the capacitor Cds is usually used for a fictitious one (a cell used to produce a reference level) whose capacitance is

  set to a value equal to about half of the capacity

  capacitor-Cs The detection method consists in comparing in advance the level of voltage stored in the

  capacitor C of the memory cell in accordance with

  it is given at the reference voltage level stored in

  the capacitor Cds of the fictitious cell In the structure

  re of the D-RAMI memory of the prior art, in order to adjust the ratio of capacitance values of the capacitors Cs and Cds to the value C: Cds = 2: 1, the same material is used for the two cells (Si O 2) to constitute

  dielectric layers and gives the surface S

  denser Cs a value equal to approximately twice

  of the surface Sd of the capacitor Cds * In addition these conden-

  the dielectric layer is interposed between an inversion layer or a diffusion layer formed within a subtrate

  semiconductor, and polycrystalline silicon.

  From this point of view, in the case where one seeks to reduce the occupation area of the memory cells in order to increase the capacity of the D-RAM memory, it is presented from the point of view of the construction of the memory. D-RM 4 memory as described above, the problems that we

will indicate below.

  First, when seeking to increase

  integration, there is a problem in the context of

  of the manufacturing process A surface occupied by

  Memory buckets inside a single semiconductor body (chip or semiconductor chip) is very important and the capacitance occupying surface Cs of the memory cells is very large inside the

  network memory Therefore, it is necessary to

  the surface S of the capacitor Cs to reduce the

  chip size of the D-RAM memory To this su-

  when a low value is given to the surface S of the capacitor Cs, the surface Sd of the capacitor Cds becomes even smaller, since the capacitance ratio must be set to, the value Cs: Cds = 2: 1 Therefore ,

  relative to the rate of change of the surface S of the conden-

  C because of induced manufacturing dispersions

  by corrosion or chemical attack, etc., the rate of

  the surface Sd of the capacitor Cds' which must be approximately equal to half of the indicated surface S

  above, becomes very important.

  Cds denser having a capacity whose value is also

  the one to about half that of capacitor C can not be manufactured Therefore there is a limitation

  to the reduction of the surface of capacitor Cs and it is

  an obstacle to increasing the density of

  tion. Secondly, the structure of capacitors of the prior art raises the problem of temporary errors attributable to particles which are emitted by uranium U, thorium Th, etc. in a packaging material. the particles a, which are introduced into the semiconductor body, are a cause of production

  carriers that neutralize charges in

  by exerting a detrimental influence on the maintenance

  In particular, the capacitor C of the cell

  s the memory with the large area of occupation is subject to the penetration of a significant amount of

  particles is and is sensitive to the influence that these

  ticles exert. An object of the present invention is to increase the density of integration of a D-RAM memory and to obtain

  a good function of maintaining or retaining data.

  According to one aspect of the implementation of

  In this invention, different values are given to the dielectric constants of the dielectric films of

  respective capacitors Cs and Cds of a memory cell

  and a fictional cell, which has the effect of

  capacitance capacitance Cs takes a value twice that of capacitor CS despite the fact that capacitors C and Cds have substantially equal surfaces, and sd beside that, capacitor Cs is made in a stacked structure which consists of first and second conductive layers formed on the substrate

  and between which is interposed the dielectric film

  cudgel. The surface of the capacitor Cs, which had a larger footprint area, is brought to a lower value by the use of the film having the higher dielectric constant.

  because of the existence of the stacked structure, it is

  effectively reads a space on the thick oxide film for the insulation and a bird-shaped part of this film for the capacitor Cs Since the capacitor Cs has a small surface area and a large capacitance, it has a In addition, it is resistant to particles a because of the presence of

stacked structure.

  Other features and advantages of the pre-

  invention will emerge from the description given

  Reference is made hereinafter to the accompanying drawings, in which: Figure 1 is a diagram showing the arrangement of the main circuit of a D-RAM memory of the folded-line & bit-transmission type; Figure 2 is a perspective view in section of the structure of a memory cell located in the memory D-RA-M of Figure 1;

  FIG. 3 is a perspective and cutaway view.

  pe showing the structure of a dummy cell located in the DRAM memory of Figure 1; FIG. 4 is a perspective view and in

  section showing the structure of a part of the circuit

  a network of memory located in the memory

D-RAM of Figure 1; -

  FIG. 5 is a plan view showing the arrangement

  storing the memory network and a dummy network located in the D-RAE memory of FIG. 1; FIGS. 6A, 6B and 6C are larger scale plan views of a field oxide film,

  a first polycrystalline silicon layer and a

  layer polycrystalline silicon layer represented res-

respectively in Figure 5;

  FIGS. 7A to 7F are cross-sectional views

  polishing the manufacturing process phases of the

  D-RAM memory of Figures 2 to 6 C in order;

  FIGS. 8A to 8D are horizontal plan views.

  tring the states of the memory array and the fictitious network during the manufacturing process steps illustrated in FIGS. 7A-7P; Figure 9 is a perspective and sectional view showing the structure of a dummy cell which is an alternative embodiment of the dummy cell of Figure 3; FIGS. 10A to 10F are sectional views illustrating the operating phases of fabrication of a

  D-RAM memory which contains the dummy cell of the

  9, in order; Figs. 1A and 11B are plan views showing memory lattice states and a fictitious network during the manufacturing process steps illustrated in Figs. 10A-10F;

  Figure 12 is a diagram showing the relationships between

  position of a memory cell and a cell.

  fictitious lule compared to a sense amplifier.

  or reading in a line-type D-RAM memory

  green bits transmission; FIG. 13 is a perspective view and in

  section showing the structure of a memory cell

  killed in the D-RAM memory of Figure-12; Fig. 14 is a perspective and sectional view showing the structure of a dummy cell located in the D-RAM memory of Fig. 12;

  FIG. 15 is a plan view showing the arrangement

  storing a memory array and a dummy network located in the D-RAM memory shown in FIGS. 12 to 14; Fig. 16 is a view showing a sectional plane taken along line Y-Y in Fig. 15; Fig. 17 is a perspective and sectional view showing the structure of a dummy cell which is a variant of the dummy cell of Fig. 14; and Fig. 18 is a plan view showing the layout scheme of a memory array and a network.

  fictitious located in a D-RAM memory which contains the cell

the fictional figure 17.

  The embodiments will be described below.

preferred embodiments of the invention.

  Embodiments, wherein the present invention is applied to a folded bit line type D-RAM memory, will be

described with reference to the drawings.

  A D-RAM memory circuit made according to the first embodiment of the present invention is shown in FIG. 1. The circuit of the D-RAM memory consists of a sense amplifier or

  detection system, an M-ARY memory network, a

  dummy bucket D-ARY, a column switch C-SW 1,

  a decoder of RC-DCR lines and columns, a

  ADB address, DOB data output buffer, DIB data input buffer, MA main amplifier, etc. An M-CEL memory cell located in the M-ARY network is consisting of a capacitor Cs, which stores the charges corresponding to the logic value of a logic signal, and a transfer transistor MISFET QM whose gate receives a word signal, on the other hand a dummy cell (a cell serving to produce a reference level) D-CEL which is contained in the D-ARY network and which serves to provide the reference for the comparison of the level with the cell M-CEL, consists of a capacitor Cds which has a capacitance of which the value is equal to about half that of the capacitor Cs, a transfer MISFET transistor QD 1 whose gate receives a dummy word signal, and a MISFET transistor QD 2 which serves to discharge loads

in the capacitor Cds.

  In FIG. 1, the MISFET transistors assigned asterisks x, for example Q 52 and Q 53 'are arranged

  way that the threshold voltages of these transistors can

  may take values lower than those of other MISFET transistors, such as for example Qs 8 and Qs 9 s 599, The structure of an MCEL cell of FIG.

1 is shown in Figure 1.

  In this figure reference 1 denotes a P-type semiconductor substrate, the reference designates a film of thick insulating material (hereinafter referred to as

  under the term "field oxide film"), the reference

  3 denotes a thin insulating film (hereinafter referred to as "second gate insulator film"), numeral 3 denotes a dielectric film having a high dielectric constant, references 4 and 5

  designate semiconductor regions of type N, the reference

  6a denotes a first polycrystalline silicon layer

  tallin, reference 6b designates a second layer of silicone

  polycrystallineium, reference 7 designates a region se-

  N + type, the reference 8 designates a third

  ss polycrystalline silicon layer, reference 9

  designates a layer of PSG (abbreviation of glass with phos-

  phosilicates) and 10 denotes a layer of aluminum

miniun.

  The substrate, the source region, the drain region, the gate insulator film, and the

  gate of the MISFET transistor Q M located in the cell M-

  CLE are constituted respectively by the semi-

  P-type conductor 1, the N-type semiconductor region 4, the N-type semiconductor region 5, a second gate insulator film (Si O 2 film) 3 and a third polycrystalline silicon layer 8 mentioned

  The third layer of polycrystalline silicon

  Lin 8 is used, for example, as a transmission line.

  word mission WL 1 2 shown in FIG.

  Aluminum plate 10 connected to the N + type semiconductor region is used, for example, as a line of

  DL 1 data transmission shown in Figure 1.

  In addition, the storage capacitor C S located in the cell

  lume M-CEL is characterized by the fact that the electrodes,

  one dielectric layer and the other electrode of this capacitor

  are respectively constituted by the first group

  of polycrystalline silicon 6a with an insulating film

  te (essentially the semiconductor nitride film 3a, i.e., silicon nitride Si 3 N 4 having

  a high dielectric constant) and by the second

  polycrystalline silicon 6b That is, the

  densifier C uses Si 3 N 4 as a dielectric and is made according to a stacked structure, in which a

  electrode is located in direct contact with the substrate.

  The first polycrystalline silicon layer 6a, which forms

  the lower electrode of the capacitor C is in direct contact with the N-type region 7 inside the substrate 1, while the upper electrode (the second polycrystalline silicon layer 6b) is connected to a Vss line.

  (MASS) The surface of film 3a of Si 3 N 4 is coated with

  green by a thin film 3 b of Si O 2.

  Figure 3 relates to the D-CEL cell of the

  Figure 1, and shows the structure of such a cell.

  In particular in FIG. 3, the references 14 designate N + type semiconductor regions.

  15 denotes a second layer of silicon

  lycrystalline, the reference 16 designates a semiconducting region

  type N +, the references 17 and 18 designate third layers of polycrystalline silicon, the reference

  19 denotes an aluminum layer and the reference numeral 29

  a first film of gate insulator.

  The substrate, the drain region, the source region, the gate insulator film, and the gate electrode of the MISFET transistor Q Di located in the cell

  D-CEL are constituted respectively by the semi-substrate

  P-type conductor 1, the semiconductor region of type

  N 11, the N-type semiconductor region 12, the second

  3 Grid Insulator Film and the Third Layer

  of polycrystalline silicon 17 The second film of iso-

  the gate 3 is constituted for example by a film

  The second layer of polycrystalline silicon

  lin 17 extends on the semiconductor substrate of Pl e type.

  as for example fictitious line of transmission of

  words DWL 1-2 shown in FIG.

  The semiconductor 19 connected to the N-type semiconductor region extends over the P-type semiconductor substrate 1, to form, for example, a dummy transmission line DL 1 shown in FIG. 1. The substrate, the drain region, the source region, the gate insulator film and the electrode

  gate of the MISFET transistor QD 2 located in the cell

  D-CEL are constituted respectively by the P-type semiconductor substrate 1, the N-type semiconductor region 13, the N-type semiconductor region 14, a second gate insulating film (Si O 2 film)

  3 and the third polycrystalline silicon layer 18.

  The third polycrystalline silicon layer 18 is fed by a discharge signal cd for example, which is shown inside the D-CEL cell of the

figure 1.

  The capacitor Cds located in the cell D-CEL comprises an electrode, a dielectric layer and its other electrode which are constituted respectively by

  the second polycrystalline silicon layer 15, the first

  first grid insulating film 29 and the semi-

  conductor-type N + 16 Since the underside

  the substrate (capacitor surface) of the capacitor

  tituated by the N-type semiconductor region, the electro-

  superior (second layer of polycrystalline silicon

  ) is connected to the line Vss (MASS).

  As described above, the condensation

  Cs in the memory cell uses Si 3 N 4 which possesses

  having a high dielectric constant: "and whose constant

  the relative dielectric is equal to 78 and serves as a dielectric layer acting essentially as a capacitance, while the capacitor Cds in the dummy cell uses SiO 2 having a relatively low dielectric constant and having a constant

25194-61

  dielectric layer the value of 3.7 4 and serving to form the dielectric layer acting essentially as a capacitor The surfaces of these capacitors are

  dimensioned to be approximately identical to

  The capacitor Cs is constituted by the structure em-

  crushed: polycrystalline silicon Si 3 N 4 polycrystalline silicon

  Tallin. FIG. 4 shows in the form of a perspective view in partial section, the structures of certain elements situated in a peripheral circuit formed in the periphery of the M-ARY memory array, and this for example in an active regeneration circuit AR 1, in particular in FIG. 4, the references 23 designate N-type semiconductor regions while the references 27 denote third polycrystalline silicon layers and the reference 28 denotes N-type semiconductor regions.

means an aluminum layer.

  A MISFET transistor Qs 6 located in the active regeneration circuit AR 1 shown in FIG. 1 has its substrate, its source region, its drain region, its gate insulator film and its gate electrode respectively constituted by the P-type semiconductor substrate 1, the N-type semiconductor region 20,

  semiconductor region of type N + 21, the second film

  gate insulation 3 and a third layer of silicone

polycrystallineium 24.

  A MISFET Qs 4 transistor located in the circuit

  active regeneration AR 1 has its substrate, its

  this, its drain region, its gate insulator film and its gate electrode respectively constituted by

  the semiconductor substrate of type P 1, the semicon-

  N + type conductor 22, the N + type semiconductor region 23, the second gate insulator film 3 and the third polycrystalline silicon layer 27 An active regeneration control signal 110a shown in FIG.

  FIG. 1 is applied to the third layer of silicone.

polycrystallineium 27.

  A capacitor C B11 located in the resistor circuit

  Active generation AR has an electrode and a dielectric layer formed respectively by the third polycrystalline silicon layer 25 and the gate insulator film 3. The third polycrystalline silicon layer 25 is continuously connected to a third layer of polycrystalline silicon. 24 which is used as the gate electrode of the MISFET transistor Qs 6 In addition a part 25a of this third

  polycrystalline silicon layer 25 is directly

  to the N + 22 semiconductor region of the tran-

  MISFET Q: The reason is that when the third

  s 4 th polycrystalline silicon layer 24 and the N-type semiconductor region 22 are connected to the aluminum wiring layer, it is necessary to have the

  contact surface between the polycrystalline silicon surface

  tallin 24 and the aluminum wiring layer, so that the density of the wiring can not be improved The connection means mentioned previously are by

  consequently adopted with a view to increasing the density of

  ge. The other electrode of the preceding capacitor CB11 is constituted for example by an N-type inversion layer (or a N-type semiconductor region) which is

  formed on the surface of the semiconductor substrate 1

  type N inversion cyte is formed using a voltage

  which is applied to the third polycrystalline silicon layer

  Although this is not shown, the inversion layer extends to an N + semiconductor region that is formed in the semiconductor substrate 1

  and to which is applied a signal 6 rs of control of

  active generation, shown in Figure 1 The third

12 -

  polycrystalline silicon layer 26 constitutes an electrolytic

  trode of a capacitor RB 12 shown in Figure 1.

  As in the case of the capacitor C Bll 'a part of the

  polycrystalline silicon layer is connected directly

  the source region of a MISFET transistor Qs 5 shown in FIG. 1, and another portion is continuously connected to the gate electrode of a transistor

MISFET Q 57.

  Hereinafter will be described the arrangement scheme of the M-ARY memory array and the D-ARY factor network.

with reference to FIG.

  The memory array M-ARY shown in FIG. 5 is such that several memory cells M-CEL

  represented in FIG. 2 are arranged according to a

  bucket on the semiconductor substrate 1 On the other hand the

  fictional network D-ARY is such that several cells fictitious

  D-CELs shown in Figure 3 are arranged

  according to a network on the semiconductor subtrate 1.

  First of all, the memory network 1 -ARY represents

  Figure 5 is made up as shown below.

  under. In order to isolate from one another the different memory cells M-CEL, each of which consists of the MISFET transistor QM and the storage capacitor Cs, the film of the semiconductor substrate 1 is formed on the surface of the semiconductor substrate 1. field oxide 2 based on a configuration shown in Figure 6A (indicated by a dashed line on the

  Figure 5) Contrary to such a basic law of confi-

  a field oxide film 2a is an exception-

  nally disposed below a contact hole CH O

  for the application of the voltage Vss to the second cou-

  polycrystalline silicon 6b It is therefore

  possible to prevent the defect that an aluminum alloy

  minium-silicon, which is formed on the basis of the interaction

  between the aluminum layer and the poly silicon layer

  crystalline in the vicinity of the contact hole CHO, penetrates through an insulating film directly below the contact hole CHO, and undesirably reaches the surface of the semiconductor substrate 1.

  On a part of a surface surrounded by pel-

  2, the first polycrystalline silicon layer 6a is formed having a shape as shown in FIG. 6B (in FIG. 5 this zone is indicated in a portion surrounded by a line formed by dashes separated by double points to keep the

  clarity of the drawing) This first layer of polysilicon

  crystal 6a is the electrode of the capacitor Cs of the cell.

  memory and is in direct contact with the

  N + type semiconductor material which is formed inside the substrate in a part other than the oxide film

field 2.

  On the first layer of polycrystalline silicon 6a, a second polycrystalline silicon layer 6b is formed (marked by a line formed of dashes with dots

  overlapping in Figure 5) which is the

  This capacitor on the film of Si 3 N 4,

* which forms the dielectric of capacitor Cs, and on the basis of

  of a drawing or configuration as shown

  in FIG. 6C The second layer of polycrystalline silicon

  lin 6b is the common electrode to all capacitors Cs and is powered by the voltage Vss via the

  THO contact hole, as described above.

  In addition to WL word transmission lines -

  WL 1-6 which are formed in the third layer of silicon

  polycrystalline 8 in Figure 2 in the vertical direction

  of Figure 5 extend above the second

  polycrystalline silicon 6b In addition a line of

  energy supply V ss-L, which serves to apply the

  V 55 via the contact hole CH O at the

  polycrystalline silicon layer 6b, which forms an electrolyte

  storage capacitor Cs, extends according to the

  horizontal direction of Figure 5.

  On the other hand, the data transmission lines DL 1 i 1 and DL 1 1 ', each of which consists of the aluminum layer 10 in FIG. 2, extend essentially parallel to the power supply line Vss- L as shown in FIG. 5 The DL 1 -1 transmission line is connected to the drain region of the MISFET transistor QM located in the M-CEL cell via a contact hole CH 1, while that the data transmission line DL 1 is connected to the drain region of the MISFET transistor QM located in a

  another M-CEL cell via a lead hole

  CH 2 In the same way as the transmission lines

  DL 11 and 11 data transmission, data transmission lines DL 1 i 2 and DL 1-2 extend in the direction

  horizontal in Figure 5 and are connected aturions-

  of the MISFET QM transistors located in the

  M-CELs, through contact holes, in

predetermined regions.

  The dummy network D-ARY shown in the figure is constituted in the manner indicated below. The field oxide film 2 is formed on a portion of the surface of the semiconductor substrate 1, while the second film of gate insulator is formed.

  on another part of the surface of the semiconductor substrate

  1 On the field oxide film 2 and on the

  grid insulation 3, second layers of silicone

  15 and 15b are in the directions shown in FIG.

  the width of each of these sec-

  polycrystalline silicon layers 15a and 15b is very

  important for the determination of the value of the

  Cds capacitor tee The semiconductor region of type

  N 14 shown in Figure 3 is located between the second

  polycrystalline silicon layer 15a and the second layer of

  Polycrystalline silicon fiber 15b This semiconductor region

  N + 14 trice is used as a common ground line (Vss) of a set of several dummy cells D-CEL In addition the dummy line of word transmission

  DWL 1 which is formed by the third layer of polysilicon

  lens 17 in FIG. 3, extends above the surface of

  polycrystalline silicon layer 15 a This dummy word transmission line WL 1 i 1 forms the gate electrode of the transistor MISFET QD 1 located in the cell D-CEL. On the other hand a signal transmission line

  command line O dc-Ll 'which is formed by the third cou-

  polycrystalline silicon 18 in FIG.

  to apply the discharge control signal O dc representing

  in Figure 1, is distant from the imaginary line of

  transmission of words DWL 1 and extends parallel to this

  the last one A transmission line

  Mande O dc-L 2 forms the gate electrode of the transistor MIS-

  FET QD 2 located in the D-CEL cell.

  Similarly, the fictional line of transmission

  wording DWL 1 i 2 and the control transmission line

  of O ds L 2 extend parallel to the dummy word transmission line DWL 1 1 and to the transmission line

  of control signals O dc-Ll 'In addition, the transmission lines

  data mission D Let, -i i DL_ 2 and 2 extend

  from the memory array (M-ARY) as shown

  The line DL 1 i 1 is connected to the FIG.

  MISFET QD-1 transistor drain terminal located in the

  lule D-CEL via the contact hole CH 3, and the

  line DL 1 i 2 is connected in a similar manner to the

  transistor MISFET QD 1 drain located in another

  D-CEL cell, via TH 4 contact hole.

  Hereinafter, we will describe in detail the

  process for manufacturing the D-RAM memory according to the present embodiment with reference to FIGS. 7A 7 P In each of these figures, a region X 1 represents a sectional view of the device during the implementation of the process, taken following the line X1 X1 in the memory array M-ARY shown in FIG. 5, while a region X 2 represents a sectional view of the device during the implementation of the method, taken along a line X 2 X 2 in FIG. the memory array D-ARY shown in FIG. 5, and that a region X 3 represents a sectional view of the device

  during the implementation of the method, a transistor MIS-

  FET other than those of the memory network and the network fic-

  tif, for example the MISFET transistor Qs 4 in FIG.

  (A formal operating phase of the film

  oxide and the oxidation-resistant film).

  As shown in FIG. 7A, the surface of a semiconductor substrate 101 is covered by an oxide film 102 and an insulating film.

  which does not allow the passage of oxygen through it-

  same, that is to say that it is a film 103 which resists

  both to the oxidation A substrate is used respectively

  of P-type monocrystalline silicon (Si) having the

  (100), a film of silicon dioxide

  cium (Si O 2) and a silicon nitride film (Si 3 N 4> respectively to constitute the appropriate real materials

  components of the semiconductor substrate 101, the film

  the oxide 102 and the oxidation-resistant oxide film 103 The SiO 2 film 102 is formed to a thickness of about 50 nanometers by means of the surface oxidation of the Si substrate 101 and this the reason given below In the case where the film 103 of Si 3 N 4 is formed directly on the surface of the Si substrate 101,

  a thermal stress is applied to the surface of the sub-

  Si 101 stratum because of the difference between the thermal expansion coefficients of the Si substrate 101 and the film of Si 3 N 4.

  crystallites are created in the Si 101 substrate surface.

  In order to prevent this phenomenon, the SiO 2 film 102 is formed on the surface of the Si substrate 101 before carrying out the

  formation of the film of Si 3 N 4 104 On the other hand, it is

  the film of -Si 3 N 4 103 over a thickness of about nanometers using for example the chemical vapor deposition process since this film is

  used as a mask for the local oxidation of the sub-

  stratum in Si 101 as will be described in detail

below.

  (B Optical phase of selective removal of the film resistant to oxidation and ion implantation). As shown in FIG. 7B, to serially remove the film of Si 3 N 4 103 from

  the portions of the Si-substrate surface 101 on which

  the relatively thick insulating film, i.e., a field oxide film, is to be formed, a photosensitive resin film 104 is first formed on the selected portions of the surface of the Si 3 N film 4

  103 as a mask against the chemical attack.

  that In this state, the bare parts of the film of

  If 3 N 4 103 are eliminated by means of, for example, a process

  plasma corrosion, which allows corrosion to be performed with high accuracy later, to prevent a layer having a conductivity type opposite to that of the substrate or that of the so-called inversion layer from be formed in each of the parts

  of the surface of the Si substrate 101 on which the film

  field oxide should be formed, an im-

  purity having the same type of conductivity as that of the substrate or a P-type impurity in the Si substrate 101, through the exposed portions of the SiO 2 film 102 in the state in which the resin film photosensitive 104 is left, as shown in Figure 7 B ion implantation is a favorable method of introduction of the type of impurity PA type of example, boron ions (B), which leaves the impurity type P, are implanted inside the substrate Si 101 with an implantation energy of 75 ke V The dose of the ions is

  then equal to 3 x 1012 atoms / cm 2.

  (C Operational phase of film formation

the field oxide).

  The field oxide film 105, which is

  above, is formed in the selected areas of the surface of the Si substrate 101. More specifically,

  as shown in FIG. 7C, once the film is

  the photosensitive resin 104 has been removed,

  selectively the surface of the Si substrate 101 in

  The film of Si 3 N 4 103 is masked to form the SiO 2 -105 film having a thickness of about 950 nanometers (hereinafter referred to as

  "field Si O 2 film") During the formation of this

  If the Si O 2 film of field 105, the already implanted boron ions are introduced inside the Si substrate.

  101 by means of so-called penetration diffusion or

  distribution, so that a layer preventing reversal

  type P (not shown) having a predetermined thickness

  completed is formed directly below each

  of the Si O 2 film of field 105.

  (D Process phase of removal of film

  resistant to oxidation and oxide film).

  In order to expose or expose the parts of

  the surface of the Si substrate 101, which are not covered by

  green films by Si O 2 film of field 105, it eliminates

  the film of Si 3 N 4 103 using, for example, a solution of

  lution of hot phosphoric acid (H 30 P 4) Then we elect

  The film of SiO 2 102 is then extracted using a solution of hydrofluoric acid (HF). Next, as shown in FIG. 7D, the selected portions of the surface of the Si substrate 102 are exposed. in terms of the memory network and the fictitious network in 1 '

  state in which the film of Si 3 N 4 103 and the film

  SiO 2 102 have been removed, is shown in FIG. 8A. In other words, sectional views in the case of a cutting of the substrate along the lines X 1 D and X 2 D in FIG. 8 A are respectively represented in

  parts X 1 and X 2 of FIG. 7 D.

  shown in Figure 8A, although a part, in which

  each capacitor Cs in the cell M-CEL must be

  m, differs from the point of view of its shape of a part in which each capacitor Cds in the cell D-CEL must be formed, one gives to said first part a weak

  extent that it has an area equal to the surface

  opposite of the second party mentioned.

  (E.Phase operative training the first

insulating film).

  We cover the surface of the substrate exposed in

  the state of FIG. 7 D by means of a first insulating layer

  lante (film of Si O 2) 140 having a thickness of 75

  nanometers using a heat treatment in a

  oxidizing atmosphere The chemical is removed by chemical etching

  first insulating film 140 corresponding to the region of

  capacitor C 5 in the part {X 1) serving to form the cell.

  1 and the region of the capacitor Cds in the part 4 X 2) for forming the dummy cell Thus the corresponding parts of the Si substrate 101 are exposed as shown in FIG. 7 E, so

  that the first polycrystalline silicon layer can

  in direct contact with the substrate The first film

  Isolating filter 140 serves as a mask for forming N-type semiconductor regions below capacitors Cs and Cds'.

  (F Operating phase of depositing the first

conductive cheek).

  As a first conductive layer for forming the lower electrode of the capacitor Cs of the memory cell, the first polycrystalline silicon layer 141 mentioned above, having a thickness of between 100 and 200 nanometers, is formed on the the entire surface of the device using, for example, the chemical vapor deposition process. Next, N + type semiconductor regions are formed to serve

  electrodes, located on the substrate side, for

  located in the memory cell and for condensing

  located in the fictional cell.

  Implantation of ions with an impurity

  N + type, for example arsenic ions (implant energy).

  : 30 ke V, dose: 1 x 1016 atoms / cm 2), using as mask the first insulating film 140, which is

  below the first polycrystalline silicon layer

  with the result that the semiconducting B regions

  these N + 143 type are formed in the parts of the surface

  that of the Si substrate corresponding to the part of the condensa-

  the memory cell and the capacitor

  of the fictitious cell, as shown in the figure

  FIG. 7 F The value of the resistance of the first polycrystalline silicon layer 141 is reduced by the implantation

of arsenic ions.

  (G Operative phase of selective elimination of

  the first conducting and forming layer of the pel-

nitride filler).

  In order to give the first polycrystalline silicon layer 141 a predetermined electrode shape, this first silicon layer is selectively eliminated

  polycrystalline 141 using the chemical etching process

  photosensitive and leaves it in the form of the electrode 141A of the capacitor Cs, as shown in FIG.

  Figure 7 G Plasma corrosion, which makes it possible to

  Corrosion at high accuracy is favorable

  as a selective process for the elimination of the first

  In FIG. 8B, the configuration obtained in this state, according to FIG.

a plan view.

  Then, in order to make the dielectric layer of the capacitor Cs, a film of Si 3 N 4 142 is formed on the entire surface of the device and this on a

  thickness of 40 nanometers using the process of de-

  chemical vapor phase, as shown in FIG.

  re 7 B This film of Si 3 N 4 142 is formed so as to obtain a dielectric constant different from that

  of the dielectric layer (Si O 2 film) of the condensation

  In this process, the arsenic which has been introduced into the surface of the substrate is subject to the so-called penetration or redistribution diffusion, so that the

  formation of the N + type semiconducting regions 143 of

  to form the lower electrodes of the conden-

Cs and Cds is complete.

  (H Operative phase of removal of the film

of Si 3 N 4 of the fictitious cell).

  The film of Si 3 N 4 of the part (X 2) intended

  to form the fictional cell is subjected to a chemical attack

  selective and is eliminated using as mas-

  that a film of photoresist formed again,

  after which the first insulating film is removed.

  corresponding to the same part Thus, as shown in FIG. 7H, the surfaces of the Si substrate 101 in the X 2 part and the field oxide film

  , who is near, are laid bare.

  (I Operative phase of training of the first

grid insulation film).

  On the exposed or bare surface of the Si substrate 101 in the part (X 2) intended to form the cell

  D-CEL, a first film of grill insulation is deposited

  the 144 in order to realize the dielectric layer of the conden-

  Cds located in the dummy cell That is, as shown in Fig. 7 I, the oxide film 144 having a thickness of about 40 is formed.

  nanometers on the exposed surface of the Si substrate of the

  tie (X 2) of the fictional cell through implementation

  of thermal oxidation Given the thermal oxidation

  the portions of the Si 3 N 4 surface in the portion (X 1) for forming the memory cell and in the portion (X 3) for forming the peripheral circuit

  are oxidized simultaneously so that a pel-

  thin oxide thimble 139 having a thickness of about 4 nanometers, as shown in FIG. 7 I.

  (J Operative phase of depositing the second cou-

conductive cheek)>.

  In order to realize the upper electrodes of the capacitors C a and C d in the memory cell and in the dummy cell, a second polycrystalline silicon layer serving as a second conductive layer 1 '45 is formed on the entire surface of the Si substrate 101. , And this

  to a thickness of 400 nanometers using the procedure

  deposition of chemical vapor deposition The layer is deposited

  of polycrystalline silicon 145 formed on the cell of

  moire, above the film of Si 3 N 4 142, with 1 '

  interposition of the thin oxide film 139

  type N, for example phosphorus, is introduced inside this polycrystalline silicon by means of the diffusion process in order to lower the value of

  the resistance of the second polycrystalline silicon layer

  tallin 145 As a result, the value of the resistance of the polycrystalline silicon layer-takes a value

  equal to about 16 Q / n Then we selectively eliminate

  the second polycrystalline silicon layer 145 by means of a etching treatment which employs a photoresist film forming a masking mask.

  to form a second polycrystalline silicon layer

  tallin 145 A serving as the upper electrode of the capacitor C of the memory cell, a second silicon layer s

  polycrystalline 145B serving as the upper electrode of the con-

  denser of the dummy cell and a second polycrystalline silicon layer 145 C serving as part of the

  between these second polycrystalline silicon regions

  tallin and the line Vss L 'as shown in FIG. 7 J.

  (K Process phase of removal of the film

nitride).

  Using as it is the configuration of the photoresist film used in the previous operating phase, the etch is removed by etching.

  exposed parts of the film of SiO 2 139 and film

  Si 3 N 4 142, namely the film of Si O 2 139 and the film of Si 3 N 4 142 not covered by the second of

  polycrystalline silicon 145 Then, using the same

  photoresist film as a mask,

  chemically removes the first silicone film

  polycrystalline calcium 141 A in a

  naked and given the form which is represented on the

  Thus, the first layer of polycrystalline silicon

  Lin 141 A, which has been put in the form as represented

  FIG. 8B, according to a plan view, takes the form

  me as shown in Figure 6 B that is to say

  that the final shape of the first silicon layer

  lycrystalline 141 A is determined by the shape of the second

  155 A polycrystalline silicon layer, and the etched end portions of the two layers

  corresponding because of chemical attack operations

  that performed with the same mask Therefore we can say that the capacitance of the capacitor Cs is determined by the shape of the second polycrystalline silicon layer

  There is no dispersion of condensate capacity

  Cs because of the positioning error between the

  configuration of the field oxide film and the confi-

  gating of the first polycrystalline silicon layer for forming the upper electrode of the capacitor Cs, and the dispersion of etching of the oxide film for the formation of the first layer of insulator

  grid designed to serve as a dielectric for conden-

  Cs, etc., as in the case of the prior art.

  (L Operative phase of elimination of the first

  insulating film and the first film of insulation

grid).

  Then, using the same film structure

  photosensitive resin as a mask, it eliminates

* by chemical attack all the bare parts of the first

  insulating film 140 (thickness 75 nanometers) and the first film of gate insulator 144 (thickness nanometers), so as to disengage the substrate 101 as shown in FIG. 7 L As a solution for carrying out this chemical attack, one recommends using a chemical attack with hydrofluoric acid or a similar acid, which has a corrosive action on the

  If O 2, but not on silicon, to prevent an attack

-2

  as chemical the surface of the substrate 101.

  In FIG. 8C, a shape obtained in this state, that is to say, is shown in plan view.

  that sectional views in the case of cuts in the-sub-

  trat taken along lines X and X 2 L in figure JL r a igr

  8 C are represented respectively in X 1 and X 2 on the:

  7 L (M Operative phase of training the second

grid insulation film).

  In order to make the film of grill insulation

  the MISFET transistors in the M-CEL cell in the D-CEL cell and in the peripheral circuit, a second gate insulator film 146 is formed on the exposed surface of the Si substrate 101, as shown in FIG. That is, the exposed surface of the Si substrate 101 is thermally oxidized to form the second gate insulator film (Si O 2 film).

  having a thickness of about 50 nanometers Simulta-

  a film of oxide (film of Si O 2) is formed

  147 on the surface of the second poly-silicon layer

  crystalline 145, and this on a thickness of between 100

and 150 nanometers.

  Then, in order to adjust the threshold voltages of the MISFET transistors Q SiQ 53 'Q 56 and Q 57 having low thresholds as shown in FIG. 1,

  implantation of ions of an impurity of ty-

  eg, boron ions, throughout the substrate surface through a second gate O 2 O 2 film 146 (implantation energy: 75 ke V, dose:

2.4 x 1011 atoms / cm 2).

  Subsequently, in order to adjust the threshold voltages of the MISFET transistors having

  high threshold as shown in Figure 1, for example

  of the MISFET transistor Q 1 located in the M-CEL cell, MISFET transistors QD 1 and QD 2 located in the D-CEL cell and MISFET transistors Q 54 and Q 55 located in the part or the active regeneration circuit, form a film of photoresist on the regions of the

  MISFET transistors QS Q 53 'Q 56 and Q 57 as masks

  ion implantation, and an implementation is carried out

  ionization of boron ions in this state (implant energy

  tion: 75 keV, ion dose: 1 x 1011 atoms / cm 2).

  Then we form the contact hole, which is used to

  connect an electrode 25 of each capacitor CD 11 direc-

  to the N + 22 semiconductor region of the tran-

  MISFET Q 54 sistor as explained in reference

  in Figure 4, namely the so-called

  direct tact, by carrying out a selective chemical attack

  of the second film of Si O 2 gate.

  (N Third filing operating phase

  conductive layer and formation of the regions of

this and drain).

  A third conductive layer is formed over the entire surface of the Si substrate 101 so as to use it to form the gate electrodes.

  of all MISFET transistors and cable layers

  As a third conductive layer, a third polycrystalline silicon layer 148 is formed, for example over the entire surface of the Si substrate.

  101, and this to a thickness of 350 nanometers using

  the chemical vapor deposition process Ulte-

  later, an N-type impurity is introduced through

  example of phosphorus in this poly-silicon layer

  crystalline using the method of diffusion of

  re to lower the value of the resistance of this layer

  and this resistance is brought to a value equal to

  10 n / cm The third polycrystalline silicon layer 148 is selectively removed so as to

  give a predetermined form of electrode or cable

  using the photosensitive chemical etching process

  As shown in FIG. 7 N, a

  once the photosensitive chemical attack

  The silicon gate 148 forms the word transmission lines WL 11-WL 1 _ 6, the dummy word transmission lines DWL 1-DWL 1-2 and the control signal transmission lines OO DC-L 2 shown in FIG. Figure 5, and also forms the line 0 rg-L of transmission of signals

  control of the active regeneration circuit, the electri-

  trodes of the capacitors C B11, CB 12 and the gate electrodes of the transistors MISFET Q 1 S-Q 53 shown in FIG.

figure 1.

  In order to prevent contamination of the surface portions in which the source regions and the drain regions of the MISFET transistors are to be formed, the exposed surface of the Si substrate 101 is covered with a film of Si O 2 149 having a thickness of 10 nanometers by means of the thermal oxidation of the surface, as shown in FIG. 7 N At the same time as the formation of the film of Si Oz 149, the surfaces of the lines of transmission of words WL 1 _-WL 6 'dummy word transmission lines DWL 1 1' DWL 1 _ 2, control signal transmission lines O DC-L 1 'O DC-L 2' capacitor electrodes C Bll, CB 12 and electrodes

  of gate transistors MISFET Q 51-Q 53 'which constitute

  killed by the third polycrystalline silicon layer.

  As a result, these surfaces are covered by the Si O 149 film having a thickness of about 30 nanometers, as shown in FIG. 7 N.

  Then, as shown in this figure

  7 N, the implantation of ions of an N-type impurity, for example arsenic, is carried out through the film of SiO 2 149 (implantation energy: 80 keV, dose: 1 x 1016 2 2 atoms / cm) so as to form the source and drain regions 150 of the MISFET transistors. The shape obtained at this time is represented in a plan view in FIG. 8D. That is, the views in FIG. section obtained by cutting the substrate along the lines X 1 N and X 2 N in Figure 8 D are represented at X 1 and X 2 in Figure 7 N.

  (O Operational phase of film formation

  insulating layer between the layers and the contact hole).

  An interlayer insulating film is formed over the entire surface of the Si substrate 101. More specifically, as shown in FIG. 70, an interlayer insulating film is formed, for example a phosphosilicate glass film.

  (PSG) 151 having a thickness of about 800 nanometers

  very over the entire surface of the Si substrate 101.

  This film of PSG 151 also serves as a getter for sodium ions (Na) which have a deleterious influence

  on the characteristics of MISFET transistors.

  Contact holes are then formed in the PSG film 151, i.e., as shown in Fig. 70, the PSG film 151 is subjected to selective etching to form the contact holes. The PSG film 151 was then subjected to thermal treatment at a temperature of about 10,000 ° C. in order to flatten it. As a result of the heat treatment carried out at this time, the impurity formed from implanted arsenic is subject to penetration or redistribution diffusion, so that the formation of semiconductor regions of N + 150 type

  having a pre-determined depth is completed.

  (P Operational phase of training of the

third conductive layer).

  In order to form the Vss-L power supply line and the DL 1-1 DL 11 data transmission lines; DL 1-2 and DL 1-2 shown in the figure

  1, a first conductive layer is first formed.

  this, for example an aluminum layer having a

  1200 nanometers across the entire surface

  this substrate in Si 101 Then we submit to an attack

  that selective chemical this aluminum layer of

  The data transmission line DL 1 and the wiring layer 152 are shown in FIG. 7.

  The formation of the D-1 AM memory of the present

  the embodiment is completed in the manner

previously mentioned.

  The D-RAM memory according to the present embodiment has the following advantages:

  1) The integration density can be increased.

  Si N film whose constant

  Relative scale is equal to 7 8, is used primarily

  to form the dielectric of the capacitor Cs of

  the memory cell and the SiO 2 film, whose composition

  relative dielectric strength is 3.5 4, i.e., about half of the film constant value of Si 3 N 4, is used to serve as a dielectric for the capacitor Cds located

  in the fictional cell, which has the effect that

  Cs and Cds faces can be made essentially equal while maintaining the ratio of their capacitances to the value 2: 1 Therefore the difference in the rates of variation (or variations) of the surfaces of the two

  capacitors, attributed to fluctuations in conditions

  unavoidable manufacturing procedures during the implementation

  of the manufacturing process, can be remarkably reduced, and the limitation of your reduction of

  Cs surface, which was allocated to Cds, is removed.

  That's why we can give to the surface

  of Cs a value equal to about half of that

  both in the prior art Since the surface of Cs

  occupying a significant part of the memory network is

  low, we can give small dimensions to the re-

  memory bucket occupying 50 60% of the surface of the chip, so that the integration density is increased. Since Cs can be formed so that it extends over the field oxide film, bird beak shaped parts can be effectively used.

  and parts of the field and can be increased in this

  sure, the integration density.

  2) The capacity ratio of Cs and Cds can

  to be obtained essentially as a design value.

  In the prior art it was necessary all

  first to eliminate an existing oxide film

  both on the surface of the substrate in order to form the dielectric layers of C and Cds. Given the dispersion of the chemical etching carried out for this purpose in the parts in the form of a bird's beak, the surfaces of the dielectric layers of Cs and Cds had significant fluctuations On the contrary, when Cs is

  made with a stacked structure as in the present

  invention, such a disadvantage does not arise and

  Cs can be given a capacity with a sensible value.

  equal to a theoretical design value.

  In addition, the dispersion of the surface of Cs possesses

  significant capacity per unit area is sup-

  awarded because Cs is given the shape of a

  stacked structure Therefore the ratio of

  of C and C 5 S can be obtained essentially

  as a theoretical design value.

  3) Data inversion due to particles

may be reduced.

  As a result of the surface reduction of C 5, the

  the probability of penetration of particles has decreased.

  Cs capacitor has the sandwich structure of polycrystalline silicon Therefore the neutralization of an N-type inversion layer by holes created by

  the particles a does not occur so that the invert-

  ation of data attributable to particulate matter may be

picked in a remarkable way.

  4) Withholding or maintaining data can

be stabilized using Vss.

  Since the electrodes (silicon

  capacitance C S Cds capacitors are grounded (MASS), stable data can be maintained

  compared to data based on a method according to which

  the electrodes are applied to a supply voltage Vcc

  (5 V) With the method of applying the power supply voltage

  Vcc, there is a variation of the capacity due to a fluctuation in the supply voltage and the data stored in the capacitors Cs, Cds

become unstable.

  > Capacitors can be stabilized using the manufacturing process. According to the present embodiment,

  it is possible to prevent the poly-silicon layer

  crystalline is deposited directly on the film of Si 3 N 4 of the capacitor C s -In order to moderate the thermal stress attributable to the difference between the coefficients

  of thermal expansion of the polycrystalline silicon layer

  and the Si 3 N 4 layer, while simultaneously the film of Si 3 N 4 is thermally oxidized so as to form the thin film of Si O 2 on the surface of said film, the film of Si O 2 is formed. which constitutes the dielectric layer of the capacitor Cds' In addition no independent operating phase

  necessary for this purpose and capacitor C is

  s ble is achieved without any increase in the number of

operating phases.

  Referring now to FIGS. 9-11B,

  the second embodiment of the present invention will be described.

  This embodiment is an example of

  ple in which the structure of the fictivre cell of the

  first embodiment described above (see

  figure 3) is replaced by a structure

  shown in Figure 9 The rest of the construction

  cluding the structure of the memory cell, etc., is

  identical to the case of the first embodiment.

  Consequently, the explanation concerning the present

  me of realization will be focused on the fictional cell.

  Figure 9 shows the structure of the cell

  In FIG. 3, reference C denotes a film of thin SiO 2, references 11 14 denote a N + type semiconductor region, reference 15 ar 'denotes a first layer of polycrystalline silicon, reference 15a. designates a second layer of silicon

  polycrystalline, reference 16 designates a semi-

  conductor-type N +, the references 17 and 18 designate third layers of polycrystalline silicon and the

  reference 19 denotes an aluminum layer.

  A Cds capacitor located in the D-CEL cell

  has an electrode, a dielectric layer and its

  (which are constituted respectively by the first polycrystalline silicon layer 15a, by the surface oxide film (SiO 2 film) 3C of

  the polycrystalline silicon layer i 5 a and by the secon-

  of polycrystalline silicon layer 15 b The semiconductor region

  N + type conductor 16 is formed in direct contact with the lower electrode (the first silicon layer

  polycrystalline a) capacitor Cds' and the upper electrode

  (the second polycrystalline silicon layer 15b)

  is connected to a line Vss (MASS).

  Since the MISFET transistors Q and QD 2 located in the DCEL cell are the same as in FIG. 3, the same parts are affected by the same

  reference numbers and will not be described again.

  Therefore, in this embodiment, the capacitors Cs and Cds are respectively formed by stacked members that are sandwich structures formed of polycrystalline silicon layers including the Si 3 N film and the Si O 2 film as layers. dielectric-Naturally a capacitor

  Cs located in the memory cell uses Si 3 N 4 pos-

  seducing a high electrical dielectric constant with a relative dielectric constant equal to 7 8, as

  dielectric layer acting essentially as

  capacitance, while the capacitor Cds located in the cell

  the fictional uses Si O 2 having a diglec constant

  relatively weak, with a dielectric constant

  3.4, as a dielectric layer

  essentially as capacity The surfaces of these

  are sized to be appro-

approximately equal.

  We will describe with reference to Figures 1 OA-10 G

  the process of manufacturing the D-RAM memory according to the se-

  In the respective figures, the regions X 1, X 3 and X 3 represent sectional views of the same parts as the X 1, X 2 and X 3 regions on the

  Figures 7 to 7 P, according to the order of the operating phases.

  In the manufacture of this second form of embodiment

  the operating phases of manufacture of the first

  first embodiment illustrated in FIGS.

  7 F are performed in a similar way Therefore

  obtains the structure shown in Figure 7 F.

  The following operating phases are successively carried out. (A) Optical phase of selective removal of the first conductive layer and the formation of the

nitride film).

  To give the first layer of polysilicon

  crystalline lens 141 of the predeterminedelectron wavelengths, this first silicon layer is selectively eliminated

  polycrystalline 141 using the chemical attack method

  photosensitive layer while leaving said layer

  in order to form the electrodes 141 A and 141 B of the conden-

  Cs and Cds as shown in Figs. 10A.

  Plasma corrosion allowing a corro-

  high precision is favorable as a selective elimination process

  first polycrystalline silicon layer 141 On the

  FIG. 11 shows, according to a plan view, the confi-

obtained in this step.

  Then, in order to make the dielectric layer of the capacitor Cs, a film of Si 3 N 4 142 is formed on the entire surface, and this over a thickness of nanometers, using a chemical vapor deposition process as shown This film of Si 3 N 4 142 is formed so as to establish a different dielectric constant from that of the dielectric layer (Si O 2 film) of the capacitor Cds'. During this process, the arsenic which has introduced into the surface of the substrate is subjected to penetration or redistribution diffusion, so that the N + type semiconductor regions 143 intended to constitute the lower electrodes of the capacitors

Cs and Cds are formed.

  (B Operative phase of the elimination of pel-

  ficula of Si 3 N of the fictitious cell).

  Selective chemical attack is subjected to

  Si N 4 142 film of the part (X 2) so as to form

  The fictitious cell is removed and removed using a newly formed photoresist film as a mask. Thus, as shown in FIG. 10B, the surfaces of the first polycrystalline silicon layer 14 i B are exposed. of the first insulating film in part X 2 and the film of field oxide 105

in the neighborhood of this part.

  (C Operative phase of formation of the film

of Si O 2 of the fictitious cell).

  On the bare surface of the first layer of

  polycrystalline silicon 141 B in the part (X 2) serving

  to form the D-CEL cell, a second film is

  insulation (Si O 2 film) 144 in order to achieve the

  dielectric layer of the capacitor Cds located in the

  For example, as shown in FIG. 10C, the exposed surface of the first polycrystalline silicon layer 141B in the portion (X 2) of the dummy cell is covered by FIG. an oxide film (SiO2 film) 144 having a thickness of about 40 nanometers, by thermal oxidation of said layer. As a result of this thermal oxidation, the portions of the Si 3 N 4 surface located in the part (X 1) and intended to form the memory cell, and the part (X 3) destiny G to form the peripheral circuit are

  simultaneously oxidized so that the forma-

  thin oxide film 139 having a thickness of

  about 4 nanometers, as shown on

Figure 1 OC.

  (J Operative phase of depositing the second cou-

conductive cheek).

  In order to realize the upper electrodes of capacitors Cs and Cds in the memory cell and in the dummy cell, a second polycrystalline silicon layer 145 is formed as a second conductive layer on

  the entire surface of the substrate, and this on a thick-

  400 nanometer, using the deposit method

  chemical vapor phase The polycrystalline silicon layer

  tallin 145 formed on the memory cell is deposited

  over the film of Si 3 N 4 142 by interpolating

  A N-type impurity, for example phosphorus, is introduced into this polycrystalline silicon by means of the diffusion process in order to lower the resistance value of the second polycrystalline silicon layer 145. as a result

  the value of the resistance of the polysilicon layer

  crystalline becomes about 16 n / a.

  selectively mine the second polycrystalline silicon layer 145 using a chemical etching process which employs as a mask & a film of

  photoresist, so as to form a second layer

  polycrystalline silicon lead 145 A for constituting the upper electrode of the capacitor Cs of the memory cell, and a second polycrystalline silicon layer 145 B serving as upper electrode of the capacitor Cds of the dummy memory cell, and a second layer of

  polycrystalline silicon 145 C serving as a connecting part

  between these second layers of polycrystalline silicon

  lin and the line Vss-L as shown in Figure 10 D.

  (E Conformational process phase of C 5 and Cds).

  Using the shape or structure of the pel-

  photoresist obtained in the preceding

* the operating phase, as it is, we eliminate by attack

  as chemical the exposed parts of the film of Si O 2 139

  and the first insulating film 140 further in use

  reading the same photoresist film as a mask, the first polycrystalline silicon layers 141 A and 141 B are chemically etched away in new-to-bare parts and given shapes as shown in FIG. Thus, the first polycrystalline silicon layers 141 A and 141 B, which have the shapes as shown in FIG.

  in plan, become what is described above.

  my definitive first layers of polysilicon

  141 A and 141 B are determined by the shapes of the second polycrystalline silicon layers 141A and 141B, and the end portions, having undergone the attack.

  chemical, of these two layers correspond, being

  As a result, it can be said that the capacitances of capacitors Cs and Cds are determined by

  the shapes of the second layers of polycrystalline silicon

  flax 145 A and 145 B There are no dispersions of capaci-

  capacitors Cs and Cds due to misalignment between the structure of the oxide film

  field and the structures of the first layers of sili-

  polycrystalline copper constituting the upper electrodes of the capacitors Cs and Cds, nor the dispersion caused by

  the chemical etching of oxide films with a view to

  the first films of grid insulation

  the dielectrics of capacitors Cs and Cds,

  etc., as was the case in the prior art.

  In addition using the same structure or configuration of the photoresist film

  as a mask, all the bare parts of the pel-

  If O 2 are removed by etching, so as to expose the substrate 101 as shown

  in Figure 10 E As a solution for realizing

  of this chemical attack, it is recommended that

  use a chemical attack with fluorhy- acid.

  which has a corrosive action on the SiO 2, but not on the silicon, in order to prevent the surface of the substrate 101 from being subjected to

chemical attack.

  In Figure 11B is shown in a

  plan view, a configuration of the state obtained

  that is to say that the sectional views in the case of a section of the substrate along X 1 K and X 2 K according to Figure 1 l B are respectively represented in Xl and X 2 in Figure E.

  (F Operative phase of formation of pel-

grid insulation filler).

  In order to realize the gate insulator film of the MISFET transistors in the M-CEL cell, in the D-CEL cell and in the peripheral circuit, a gate insulator film 146 is formed on the exposed surface of the substrate. If 101, as shown in Fig. 10 F That is, the exposed surface of the Si substrate 101 is thetmically oxidized, which has the effect of forming the gate insulating film (Si O film). 2) 146 having a thickness of about 50 nanometers Simultaneously an oxide film (SiO 2 film) 147 is formed on the surface of the second polycrystalline silicon layer 145,

  and this on a thickness between 100 and 150 nanometers.

  Thanks to the implementation of the operational phases

  above, we obtain a representative structure

  This structure corresponds to the structure of the first embodiment shown in FIG.

  in FIGS. 7 M Then, in the same way,

  re that in the case of the first embodiment, the ion implantation for adjusting the threshold voltages of the MISFET transistors and the formation of holes

  of direct contact Moreover, we implement

  milaire the manufacturing operating phases illustrated in Figures 7 N-7 P in connection with the first form

of realization.

  The realization of the memory D-RAM of the pre-

  this realization is completed with the modus operandi

indicated previously.

  The D-RAM memory according to the present embodiment of

  The advantages of the first form of

  previous use and furthermore provides the benefits (2)

  and (3) as indicated below.

  2) The capacity ratio of Cs and Cds can be obtained essentially as a theoretical design value.

  In the prior art, it was necessary to remove

  beforehand a film of oxide existing on the

  surface of the substrate in order to form the dielectric layers

  than C 5 and Cds Given the dispersion of the

  that chemical implemented for this purpose in the parts

  in the shape of a bird's beak, the surfaces of dielectric layers

  of C and Cds showed significant fluctuations in

  On the contrary, when Cs and Cds are made

  according to the stacked structures as in the present in-

  vention, such a disadvantage does not arise and capacitors C and Cds can be given capacitance

  essentially equal to the theoretical values of

  tion. The capacitances of the two capacitors C and Cds depend on the condition of the positioning of the second

  polycrystalline silicon layer with respect to the first

  polycrystalline silicon layer that is to say that these capacitances are determined in such a way that the parts

  of the first polycrystalline silicon layer are again

  calf subjected to a chemical attack in relation to the

  structures or configurations of the second layer of silicon

  polycrystalline particles the parts to be

  In the two capacitors Cs and Cds', the two capacitors Cs' and Cds' are closely spaced so that the variations in the respective capacitances themselves, attributed to the positional deviations, can be made small.

  upper and lower of the two capacitors Cs and Cds-

  are formed respectively by means of the same operational phases

  it is possible to make the variation of the

  capacity ratio, attributed to differences in position

  Therefore, it is possible to obtain as a ratio

  quoted from Cs and Cds' theoretical design value.

  3) Data inversion due to particles

can be reduced.

  Given the fact that the surface of Cs is

  smaller than in the case of the prior art, the probability of

  particle penetration rate is decreased in

  in addition to the capacitors Cs and Cds possess the

  Thus, the neutralization of the N-type inversion layers by means of polycrystalline silicon sandwich

  holes created by particles a does not occur

  as the inversion of data attributable to particles

  can be remarkably reduced.

  Hereinafter will be described with reference to the drawings,

  embodiments in which the present invention

  is applied to a line-type D-RAM memory

Open bit transmission.

  Part of a D-RAM memory circuit according to the third embodiment of the present invention

is shown in Figure 2.

  In this figure, to preserve the clarity of the drawing, there is shown a memory cell M-CEL and a dummy memory D-CEL in connection with a pair of lines formed by a word transmission line W and a dummy word transmission line DW and a section of complementary data transmission lines D, D, but respective cells are connected in a manner similar to

  other lines of transmission of words and other

  Data transmission networks The M-CEL cell is con-

  staggered by a storage capacitor or storage Cs

  which is used for stock and charges corresponding to the local value

  logic signal, and by a MISFET transistor, namely a transfer MISFET QM which receives a word signal on its gate and which is connected to a sense or sense amplifier S A via the

  line of data transmission D On the other hand the cell

  the dummy D-CEL, which serves to provide the reference of the comparison of the level with the cell M-CEL, is constituted by a capacitor Cds which possesses a capacity whose

  value is equal to about half the capacity of the con-

  densifier C, a MISFET transistor QD 1 which receives a signal

  fictitious word on its grid and which is connected to the amplifica-

  detection sensor S A via the data transmission line D, and a MISFET transistor QD 2 which

  is used to discharge the loads in the con-

  Cds denser As shown in the figure, in the open bit transmission line type DRAM, the paired complementary data transmission lines D and D extend to the right and to the left from the amplifier. Thus, in accordance with the first and second embodiments, the memory cell and the corresponding dummy cell are arranged at a distance from each other.

  the right and left of the sense amplifier.

  The structure of the M-CEL cell of FIG. 12 according to this third embodiment is shown in FIG.

  FIG. 13 In this figure, reference numeral 1 denotes a sub-

  P-type semiconductor stratum, the reference 2 a film

  the oxide of field, the reference 3 a second film

  of gate oxide, reference 3 has a dielectric film

  that having a high dielectric constant, the

  4 and 5 of the N-type semiconductor regions, the

  reference 6 has a first layer of polycrystalline silicon

  lin, reference 6 b a second layer of polysilicon

  crystalline, the reference 30 a third layer of silicone

  polycrystalline copper and 31 a layer of aluminum

  minium. The storage capacitor C located in the

  M-CEL cell has an electrode, a dielectric layer

  and its other electrode constituted respectively by the first polycrystalline silicon layer 6a, by

  the insulating film of semiconductor nitride 3a, that is,

  that is to say a film of Si 3 N 4, and by the second layer of polycrystalline silicon 6b The upper electrode

  (the second polycrystalline silicon layer 6b) of the

  Cs densifier is placed at a voltage VDD.

  The substrate, the source region, the drain region, the gate insulator film, and the gate electrode of the MISFET transistor QM located in the M-CEL cell

  are constituted respectively by the semiconductor substrate

  type P 1, the N + 4 semiconductor region,

  the N + 5 semiconductor region, the second film

  grid insulator gate formed of a semiconductor oxide

  (Si O 2 film) 3 and the third polycrystalline silicon layer 30, mentioned above.

  sth polycrystalline silicon layer 30 is connected to the aluminum layer 31 as for example-'line

  of the word transmission W shown in FIG.

  The N + type semiconductor region is used as a data transmission line D. FIG. 14 shows the structure of the

  In Figure 14, the reference D-CEL of FIG.

  reference 29 designates a first film of grill insulation

  (Si O 2 film), references 11, 14 and 16

  semiconductor regions of type N +, the reference

  this designates a second layer of polycrystalline silicon

  lin, references 32 and 33 refer to third cou-

  polycrystalline silicon and references 34 and 35

refer to aluminum scoops.

  The capacitor C ds located in the cell D-CEL

  has an electrode, a dielectric layer and its

  electrode respectively constituted by the second

  polycrystalline silicon layer 15, the first layer of

  the gate insulator 29 and a N + type semiconductor region 16 The upper electrode (the second polycrystalline silicon layer 15) of the capacitor Cds is placed

at the voltage VDD.

  Substrate, drain region, source region, gate insulator film and electro

  gate of transistor MISFET Q Dl located in cell D-

  CEL are constituted respectively by the semicon-

  P-type conductor 1, the N-type semiconductor region

  11, the semiconductor region of N + type 16, the second pel-

  grid insulation film (Si O 2 film) 3 and the third

  second polycrystalline silicon layer This third layer of polucrystalline silicon 32 is connected to the aluminum layer 34 as for example line

  fictional word transmission DW represented on the

  FIG. 12 The substrate, the drain region, the source region, the gate insulator film, and the

  gate of transistor MISFET QD 2 located in cell D-

  CEL are constituted respectively by the semicon-

  P 1 type conductor, N + type semiconductor region 14, N + type semiconductor region 16, second gate insulator film (Si O 2 film) 3 and third polycrystalline silicon layer 33 polycrystalline silicon 33 is supplied, from the aluminum layer 35, by a discharging signal O DC represented for example in the cell D-CEL of FIG. 12.

  In this embodiment, the condensation

  Cs located in the M-CEL cell uses Si 3 N 4 pos-

  seducing a high dielectric constant, with constant

  the relative dielectric of 78 as a dielectric layer

  which acts essentially in the manner of a capacitance, while the capacitor Cds located in the cell D-C-EL

  uses Si O 2 having a relative dielectric constant

  of 3, r 4, as a dielectric layer acting

  essentially as capacitance The surfaces of these conden-

  are sized to be approximate-

  The capacitor Cs is formed with the structure

  stacked: polycrystalline silicon Si 3 N 4 silicon

  polycrystalline The surface of the Si 3 N 4 3 a layer is

  covered by the oxide film 3b of this layer and the

  polycrystalline silicon layer surface 6 b is ac-

  covered by the film of Si O 2 36

  the relationship between the memory cell and the cell

  fictional model becomes similar to that provided for in the first

re embodiment.

  Figure 15 is a diagram for explaining the

  configuration or arrangement structure of the cells of

moire and fictitious cells.

  First of all we will describe the agency schema-

  In order to define the data transmission lines formed by the N + type semiconductor regions and the Cs capacitors, the field oxide films 2 are uniformly arranged as indicated by FIG. solid lines and dashed lines as indicated by

  dashed lines with sets of double dots

  intercalated films, the first layers of polycrystalline silicon

  tallin 6a constituting the lower electrodes of the con-

  Cs are formed in the parts of the condensa-

  correspondents Cs As indicated by lines in

  solid lines and by lines in phantom lines, the secon-

  polycrystalline silicon layers 6b which form the upper electrodes of capacitors Cs are in the form of electrodes which are common to all

  capacitors Cs, bringing together two neighboring lines of trans-

  mission, and are connected to a feed line.

  VDDL voltage supply made of aluminum, via a contact hole CH 3 formed in an interlayer insulating film (not shown).

  the VDD voltage is applied to the second silicon layer

  Polycrystallineium 6b The third polycrystalline silicon layers 30 which constitute the gate electrodes

  of the MISFET transistor QM 'are arranged in such a way as to

  regularly farting with polygonal configurations as indicated by solid lines and lines

  dashes, and are connected to the transmission lines

  wording 31 (W) made of aluminum, via

  of CH and CH contact holes in

  i 2 interlayer insulator (not shown) - Aluminum wiring lines extend to intersect

  at right angles the data transmission lines constitute

  killed by the semiconductor regions -

  On the other hand, in the part of the dummy cell, the field oxide films 2 are arranged as indicated by solid lines and dashed lines, so as to define the surfaces of the

  capacitors C ds so that the capacity of each con-

  Cds denser can take about half the capacitance of each capacitor CS As indicated by solid lines and lines

  dashes, the second layers of polysilicon

  15 constituting the upper electrodes of the

  capacitors Cds form electrodes which are

  two capacitors Cds connecting two neighboring lines

  of data transmission, and are also adjacent to

  to the second polycrystalline silicon layers 6 b of

  part of the memory cell Therefore the

  VDD is applied to the second silicon layers

  The third layers of polycrystalline silicon

  crystal 32 and 33 constituting the gate electrodes

  MISFET transistors QD 1 and QD 2 are arranged in such a way that

  re indicated by solid lines and lines

  dashes and are respectively connected to the

  fictitious word transmission system 34 <DW) and to the signal transmission line 35 (O DC-L) made of aluminum, via contact holes CH 4 and CH 5 formed

  in an interlayer insulating film (not shown).

  In addition, the N + type semiconductor regions 14 are connected to the ground potential line VSS via the three CH 6 and CH 7 contact regions, and the N + type semiconductor regions are connected to the regions.

  semiconductors 5 which constitute the transmission lines

data.

  As a method of manufacturing the D-RAM memory of the present embodiment, the manufacturing method of the first embodiment shown in Figs. 7A-7B is used as such. That part of the first silicon layer The polycrystalline phase which remains on the region to become the channel of the MISFET transistor QM 'in the operating phase illustrated in FIG. 7 K is eliminated at the same time as the conformation of FIG.

  second layer of polycrystalline silicon by means of

  illustrated in Figure 7 J This is identi-

  than in the case of the first embodiment The third

  my polycrystalline silicon layers which are formed as gate electrodes of MISFET transistors QM 'QD 1 and QD 2 by means of the process phase illustrated in FIG. 7 N, are stacked on the second polycrystalline silicon layers constituting the upper electrodes of capacitors Cs and Cds via dandruff

  of these layers, as can be seen from the

  As a result, contrary to the first

  realization, no N + type semiconductor region

  formed between the capacitor Cs and the transistor MIS-

  FET QM, or between the capacitor Cds and the MISFET transistor QD 1 or QD 2 Then, with the necessary modifications, the operating phases illustrated in the figures are implemented

  and 7 P Then the realization of the D-RAM memory of the third

  second embodiment is completed.

  The third embodiment presents the advantage

  following stage, in addition to the advantages of the first form of

  embodiment described above.

  ) It is easy to make aluminum wiring.

  Uneco pe of the present embodiment

  corresponding to the section along line X-X in Figure 15,

  is shown in Fig. 16 In accordance with this

  re, the two capacitors C of two reciprocally adjacent memory cells are arranged on the Si O 2 film of field 2 in the form of structures stacked by

  therefore the surfaces of the insulating films between

  37 on the two capacitors Cs near one of the other

  can be realized in the form of plane surfaces of

  a relatively large size

tact between the third polycrystalline silicon layer and the word transmission line 31 can be easily established, and this contact is not much limited from the point

  position as long as it is located on the sili-

polycrystallineium 30.

  Referring now to Figures 17 and 18,

  the fourth embodiment of the present invention will be described.

  This embodiment is an example in which the structure of the dummy cell in the third embodiment described above (see FIG.

  refer to Figure 14) is replaced by a structure

  shown in FIG. 17 The other construction including the structure of the memory cell, etc., is identical

  to that of the third embodiment Therefore the former

  this embodiment will focus on

the fictional cell.

  FIG. 17 represents the structure of the D-CEL cell. In the figure, reference 3 C denotes a film.

  of Si O 2 minde, the "references11 and 14 of the semiconductor regions

  N + type, the reference 15 has a first layer of

  polycrystalline silicon, reference 15a, a second

  polycrystalline silicon, the reference 16 a region

  type N semiconductors, references 32 and 33 of the third

  layers polycrystalline silicon layers and references

34 and 35 aluminum layers.

  The capacitor Cds located in the cell D-CEL

  has an electrode, a dielectric layer and its

  are respectively constituted by the second cou-

  polycrystalline silicon 15b, by the film of oxy-

  of polycrystalline silicon superficial (Si O 2 film)

  3 C and the first polycrystalline silicon layer a.

  The N-type semiconductor region 16 is formed in contact

  directly with the lower electrode (the first layer of

  polycrystalline silicon 15 a) capacitor Cds, and l 4 electro-

  superior (the second polycrystalline silicon layer

b) is placed at a voltage VDD.

  Since the MISFET transistors Q D1 and QD 2 located in the cell D-CEL are identical to those of the

  Figure 14, the same parts are assigned the same numbers

  reference and will not be described again.

  Fig. 18 is a diagram showing the scheme or arrangement structure of memory cells and dummy cells as indicated by a solid line and dashed lines with

  interspersed double points, the first layers of sili-

  Polycrystallineium 15 a forming the lower electrodes of the capacitors C ds are formed in the parts of the

  corresponding capacitors Cds' Since the

  parts are the same as in figure 15, they are assigned the same reference numbers and no

  will give again no explanation.

  Therefore, in this embodiment, the capacitors Cs and Cds are respectively formed by stacked members that are sandwich structures of the polycrystalline silicon layers including the film

  of Si N and the film of Si O 2 as dielectric layers

3 42

  Of course, the capacitor Cs located in the

  memory lule uses Si 3 N 4 having a constant

  dielectric constant, with a dielectric constant

  7, as a dielectric layer acting essentially as a capacitance, while the capacitor Cd in the dummy cell uses

  If O 2 has a relatively low dielectric constant

  with a relative dielectric constant of 3.7 4, as a dielectric layer acting essentially in the manner of a capacitance The surfaces of these capacitors

  are dimensioned so that they are approximately

  Therefore, the relationship between the cell of

  moire and the fictional cell in this embodiment

  becomes similar to that existing in the case of the second

of embodiment.

  As a method of making memory

  D-RAM of the fourth embodiment, it is possible to use

  as such the manufacturing process of the second form

of realization.

  The fourth embodiment presents the

  advantages of the second and third forms of

previously described.

  On the basis of the technical idea of the present invention, it is furthermore possible to modify as follows:

  the previous embodiments.

  As will be understood from the forms of

  According to the prior art, unlike the prior art, the capacitance of the capacitor Cs is determined by the first polycrystalline silicon layer and the second polycrystalline silicon layer and is quite independent of the shape of the oxide film. Therefore, the shape of the field oxide film located in the portion of the memory cell need not have the configuration shown in Figure 6A, which can be

  on the contrary modified at will as long as the elec-

  with the first polycrystalline silicon layer, which constitutes the lower electrode of the capacitor Cs, can be maintained by direct contact

  It is also possible to delete the

  type N semiconductor

  the regions of capacitors Cs and Cds * In this case the

  VDD is applied to the second layers of silicon

  lycrystalline which are the upper electrodes of Cs and Cds' In addition one can use, as materials for the

  electrodes and dielectric materials for conden-

  other materials than those mentioned above.

  It is also possible to use for a part of the conductive layer (in particular the word transmission line), a silicon-aluminum alloy, any

  materials such as molybdenum, tungsten, chromium,

  me, tantalum, etc., or a metal resistant to

  them, such as a silicide of these elements and to use as a conductive layer, a stacked structure that is

  consisting of such a metal and a layer of silicon

  In addition, each transistor MISFET trans-

  The invention described above may be a P-channel type MISFET transistor, and a transfer MISFET transistor described above may be a P-channel MISFET transistor and a P-channel MISFET transistor is provided for example in a well. N-type formed in a P-type substrate.

  In this case it is desirable that the peripheral circuits

  are performed by N-channel MISFET transistors.

Claims (15)

  1 Solid state memory device   characterized in that it comprises networks (M-ARY)   memory cells each of which has several   memory cells (M-CEL) arranged in rows and columns on a semiconductor substrate (1) and each of which has a first capacitor (Cs) for   storing charges and a MISFET (QM) transistors   in series with said capacitor (Cs) which consists of first and second conductive layers (6 a,   6 (b) formed on an area of a main surface of the sub-   semiconductor tracer (1), and a first dielectric film   3 (3a) interposed between said conductive layers, fictitious networks (D-ARY) each of which comprises several   dummy cells (D-CEL) formed on said semi-substrate   1 and a second capacitor (Cds) for storing charges and constituted by a third conductive layer (16; )   a second dielectric film (29,3 c) formed on the   said third conductive layer and a fourth conductive layer (15; 15b) formed on said second film   dielectric and having a capacity less than   capacitance of said first capacitor, while the second dielectric film has a dielectric constant   less than that of said first dielectric film   that several lines of data transmission (D, D; DL 11,   DL 1) which are arranged along lines and which are ac-   coupled with memory cells (M-CEL) and fictitious cells.   (D-CEL) distributed in the corresponding lines,   any word transmission lines (W, DW; W Li_, 1 WL 16) which are arranged in columns and which are coupled   memory cells (M-CEL) or fictitious cells (D-   CEL) distributed according to the corresponding columns, and a sense amplifier (SA 1; S A) which receives signals in a pair formed of the data transmission line   the selected memory cell (M-CEL) and the   data transmission pattern of the dummy cell (D-CEL) selected. 2 Solid state memory device   according to claim 1, characterized in that the first   first capacitor (Cs) occupies a surface substantially equal to the surface of the second capacitor (Cds)   3 Solid state memory device   according to claim 2, characterized in that the   dielectric constant of the second dielectric film   that is essentially equal to half that of the first dielectric film.   4 Solid state memory device   according to claim 1, characterized in that the third conductive layer is constituted by a part said semiconductor substrate (1).   Integrated semiconductor memory device according to claim 1, characterized in that the third conductive layer is formed on an insulating film which covers the main surface of said substrate semiconductor (1).   6 Solid state memory device   according to claim 4, characterized in that the cou-   data transmission lines (DL 11, DL 1 1) which   connected to said detector amplifier (SA 1) extends   tooth in the same direction.   7 Solid state memory device   according to claim 4, characterized in that the cou-   data transmission lines (D, D), which are   coupled to said sense amplifier (S A) extends   tooth in opposite directions from each other.   8 Solid state memory device   according to claim 5, characterized in that the cou-   data transmission lines (DL 1 L 1 DL 1) 'which   coupled to said sense amplifier (SA 1) extends   tooth in the same direction.   9 Solid state memory device   according to claim 5, characterized in that the cou-   of the data transmission lines (DD) which are coupled to said sense amplifier (S A) extend   in opposite directions to each other.   Integral semiconductor memory device   according to claim 1, characterized in that the   your first and second conductive layers (6a, 6b) are   constituted by polycrystalline silicon.   11 Solid state memory device   according to claim 1, characterized in that the   the first and second dielectric films (3a, 29.3c) consist respectively of silicon nitride and by silicon dioxide.   12 Semiconductor memory device inte-   A device according to claim 1, characterized in that said first conductive layer (6a) of said first capacitor   (C) is placed in direct contact with a semiconductor region   trice (4,5,7) which is provided in the semiconductor substrate (1) of   13 Integral semiconductor memory device   A device according to claim 12, characterized in that said semiconductor region (4,5) is a source or drain region of said MISFET transistor (Q).   14 'Method for manufacturing a measuring device   Integrated semiconductor memory with   the memory (M-CEL) each of which comprises a MISFET transistor (QM) and a storage capacitor (Cs) and several dummy cells (D-CEL) each comprising MISFET transistors (QD 1 'QD 2) and a capacitor fictitious cell (Cds), characterized in that it includes   (a) the operational phase of forming a first   conductive layer (141) on each of the first zones   selected from a main surface of a semi-   conductor (1), in which capacitors of ckage (Cs) must be formed;   (b) the operational phase of training a first   insulating film (142) on said first conducting layer (141) of each first zone;   insulation film (144) on each of the second zones   selected from the main surface of the semiconductor substrate.   1), which are spaced apart from said first zones and in which the capacitors (C ds) are to be formed,   said second insulating film (144) having a constitution   less dielectric power than that of the first film   (142), and (d) the operative phase of forming a second   conductive layer (145) on said first insulating film   (142) in each first zone, and   said second insulating film (144) in each sec- zone.   A method of manufacturing a device for   integrated semiconductor memory according to claim 14, characterized in that, during the operating phase (a), the   conductive layer (141) is formed on each second zone.   16 Method of manufacturing a device for   integrated semiconductor memory according to one of the claims   14 and 15, characterized in that said first pel-   insulating tip (142) is a film of silicon nitride   and said second insulating film (144) is a silicon dioxide film.   17 Method of manufacturing a device for   integrated semiconductor memory according to any one of   claims 14 and 15, characterized in that it comprises   in addition the operational phase of forming a third   conductive layer (148) extending over an insulating film   lant formed on each second conductive layer and which   serves to form the gate electrodes of the MIS-transistors FET. e