KR100940112B1 - Method for forming the analogue capacitor of stack structure - Google Patents

Abstract

In the method of manufacturing an analog capacitor of a semiconductor device of the present invention, a capacitor pattern in which a first polysilicon film, a first insulator, a second polysilicon film, a second insulator and a third polysilicon film are sequentially stacked is formed on a semiconductor substrate. Forming an impurity doping concentration of the second polysilicon film higher than the impurity doping concentration of the first polysilicon film and the third polysilicon film, forming an insulating film on the side of the second polysilicon film, and forming a second polysilicon film. Forming a fourth polysilicon film to surround the capacitor pattern including the insulating film formed on the side surface, so that the first and third polysilicon films are electrically connected by the fourth polysilicon film, and on the fourth polysilicon film. Forming a photoresist pattern defining a contact hole region, and using the photoresist pattern as a mask, a fourth polysilicon film, a third polysilicon film, and a second insulator Etching to form a contact hole exposing the second polysilicon layer.

Capacitor, Stacked Structure, Bottom Electrode, Capacitive

Description

Method for manufacturing analog capacitor of semiconductor device {Method for forming the analog capacitor of stack structure}             

1A to 1D are cross-sectional views sequentially illustrating an analog capacitor manufacturing method of a composite semiconductor device according to the prior art.

2A through 2F are cross-sectional views sequentially illustrating a method of manufacturing an analog capacitor of a semiconductor device according to an exemplary embodiment of the present invention.

 -Explanation of symbols for the main parts of the drawing-

105: silicon substrate 110: first polysilicon film

120: first insulator film 130: second polysilicon film

140: second insulator film 150: third polysilicon film

155 capacitor pattern 160 oxide film

170: fourth polysilicon film 180: photosensitive film pattern

190: contact hole

The present invention relates to a method of manufacturing an analog capacitor of a semiconductor device, and more particularly, in the process of simultaneously forming a gate electrode and an analog capacitor of a memory cell, the analog capacitor is a PIP (Poly Insulator Poly) type, that is, a stacked structure The present invention relates to a method of manufacturing an analog capacitor of a semiconductor device in which the lower electrode, the insulating film, and the upper electrode are formed, thereby increasing the surface area of the lower electrode within the same area, thereby improving the capacitance.

Recently, due to the emergence of a composite semiconductor device in which a memory cell array unit and a logic circuit unit are one-chip, analog devices require high-speed and high-capacity capacitors due to various uses of integrated circuits. In order to reduce the thickness of the insulating film between the lower electrode and the upper electrode, which are the electrodes of the capacitor, or to increase the surface area of the capacitor lower electrode by using an insulator having a high dielectric constant as the dielectric film.

Capacitors commonly used in semiconductor integrated circuits include MOS structures, PN junction structures, polysilicon-insulator-polysilicon (PIP) structures, metal-insulator-metal (MIM) structures, and the like.

Meanwhile, in forming an analog capacitor having a PIP structure, a logic circuit part is formed by stacking a gate oxide layer and a doped polysilicon and then forming a gate electrode in an active area of a substrate of a memory cell array by a photomask and an etching process using a gate mask. The lower electrode of the analog capacitor is simultaneously formed on the field oxide film of the film, and the polysilicon for forming the insulating film and the upper electrode is sequentially stacked to form the capacitor. However, since the lower electrode of the capacitor formed at the same time as the gate electrode is formed in the same plane as the gate electrode, there is a limit to increasing the capacitance of the capacitor within the same area, and thus, it is difficult to manufacture a capacitor requiring a large capacity. There was a problem.

Hereinafter, with reference to the accompanying drawings, it will be described in more detail the problems appearing in the analog capacitor manufacturing method of the semiconductor device according to the prior art as described above.

1A to 1D are cross-sectional views sequentially illustrating an analog capacitor manufacturing method of a semiconductor device according to the prior art.

According to the analog capacitor manufacturing method according to the related art, first, as shown in FIG. 1A, a field oxide film (A) as a device isolation region for distinguishing an active region and an isolation region between devices is formed on a silicon substrate 10 as a semiconductor substrate. 12).

Subsequently, after the gate oxide layer and the doped polysilicon are stacked on the silicon substrate 10, the gate electrode 14a is formed in the active region of the silicon substrate 10 of the memory cell array unit 200 by a photolithography and etching process using a gate mask. ) And at the same time the lower electrode 14b of the analog capacitor is formed on the field oxide film 12 of the logic circuit unit 100. At this time, since the lower electrode 14b of the analog capacitor is formed in the same plane as the gate electrode 14a, the area of the lower electrode 14b should be increased to improve the capacitance of the capacitor. If the area is increased, the chip size is increased, resulting in difficulty in high integration of the semiconductor device.

In addition, a spacer 16 made of an insulating material is formed on sidewalls of the gate electrode 14a and the lower electrode 14b, and conductive impurities are ionized through the gate electrode 14a in the active region of the memory cell array. The implanted source / drain regions 18 are formed.

As shown in FIG. 1B, the insulator 20 is deposited on the resultant to be used as the dielectric of the analog capacitor. Meanwhile, the insulator 20 may increase the capacitor capacitance depending on the material, and may also prevent the boron dopant of the BPSG from penetrating into the lower memory cell as the interlayer insulating layer to be formed.

Next, as illustrated in FIGS. 1C and 1D, the doped polysilicon 22 is deposited on the insulator 20, and then the stacked doped polysilicon 22 is patterned by performing a photo and etching process. As a result, the upper electrode 22 'of the analog capacitor is formed.

That is, according to the analog capacitor manufacturing method of the composite semiconductor device according to the prior art, while forming the gate electrode 14a in the active region of the silicon substrate 10 of the memory cell array unit 200, the logic circuit unit 100 of the The lower electrode 14b of the analog capacitor is simultaneously formed on the field oxide film 12 in a plane, and then the insulator 20 and the doped polysilicon 22, which is the upper electrode forming material, are sequentially stacked thereon to form an analog capacitor. Therefore, when a large capacity capacitor is required, the area of the lower electrode should be increased to improve the capacitance of the capacitor. However, when the area of the planar lower electrode is increased, the chip size becomes large. The problem is that high integration of the device becomes difficult.

In order to solve the above problems, in the capacitor forming method of the PIP structure in which the lower electrode, the insulating film and the upper electrode are formed by the stacked structure, the surface area of the lower electrode is increased within the same area to improve the capacitance. Accordingly, an object of the present invention is to provide an analog capacitor manufacturing method of a semiconductor device that enables high integration of the semiconductor device.

In order to achieve the above object, the present invention forms a capacitor pattern in which a first polysilicon film, a first insulator, a second polysilicon film, a second insulator and a third polysilicon film are sequentially stacked on a semiconductor substrate. 2 the impurity doping concentration of the polysilicon film is higher than the impurity doping concentration of the first polysilicon film and the third polysilicon film; forming an insulating film on the side of the second polysilicon film; and on the side of the second polysilicon film. Forming a fourth polysilicon layer to surround the capacitor pattern including the formed insulating layer, so that the first and third polysilicon layers are electrically connected by the fourth polysilicon layer, and contact holes on the fourth polysilicon layer Forming a photoresist pattern defining a region, and etching the fourth polysilicon film, the third polysilicon film, and the second insulator by using the photoresist pattern as a mask; It provides a method of manufacturing an analog capacitor of a semiconductor device comprising the step of forming a contact hole exposing the silicon layer.

In the method of manufacturing an analog capacitor of a semiconductor device according to the present invention, the first polysilicon film and the second polysilicon film are formed to have the same thickness, and the third polysilicon film has a thickness of the first polysilicon film or the second polysilicon film. It is preferable to form the thickness of about 3/5, and to form a 4th polysilicon film later about 2/5 of the thickness of a 1st polysilicon film or a 2nd polysilicon film. Accordingly, the thickness of each of the lower electrode and the upper electrode is formed to be the same when the capacitor including the lower electrode and the upper electrode is formed by a later process.

delete

In the method of manufacturing an analog capacitor of a semiconductor device according to the present invention, the first polysilicon film and the third polysilicon film are formed by depositing a polysilicon film having the same doping concentration, and the second polysilicon film is formed of the first, second, and third polysilicon films. It is preferable to form so as to have a higher doping concentration than the third polysilicon film. Accordingly, an oxide film, which is an insulator grown during the wet oxidation process, is formed on the sidewalls of the first polysilicon film and the third polysilicon film, and the sidewalls of the first and third polysilicon films are formed on the sidewalls of the second polysilicon film. A thicker oxide film is formed so that the first polysilicon film and the third polysilicon film are insulated by a subsequent etching process.

In the method of manufacturing an analog capacitor of a semiconductor device according to the present invention, the step of forming an insulating film on the side of the second polysilicon film may be performed by oxidizing the semiconductor substrate on which the capacitor pattern is formed. Forming an oxide film on a side surface of the polysilicon film, and forming an oxide film thicker than side surfaces of the first and third polysilicon films on the side surface of the second polysilicon film, and remaining only on the side surface of the second polysilicon film; Etching the oxide film formed on the side surface of the first to third polysilicon film. The etching of the oxide film formed on the side surfaces of the first to third polysilicon films may be performed by a wet etching process.

Hereinafter, with reference to the accompanying drawings, it will be described in detail an embodiment of an analog capacitor manufacturing method of a semiconductor device according to the present invention. However, the scope of the present invention is not limited thereto, but is presented as an example.

2A to 2F are cross-sectional views sequentially illustrating a method of manufacturing an analog capacitor of a semiconductor device according to the present invention.

Referring to FIG. 2A, a first polysilicon film 110, a first insulator film 120, a second polysilicon film 130, a second insulator film 140, and a third poly on the silicon substrate 105 may be used. The silicon film 150 is sequentially stacked and then patterned to form a capacitor pattern 155. The first insulator film 120 and the second insulator film 140 may be formed of a thermal oxide film, a nitride film, or a high dielectric constant. At least one of the films formed by the combination thereof is selected and formed. In this case, the first, second and third polysilicon films 110, 130 and 150 are formed of polycrystalline silicon, and the second polysilicon film 130 is formed of the first and third polysilicon films 110 and 150. Formed by implanting more P ions or increasing the concentration of PH ₃ gas when the second polysilicon layer 130 is deposited, so as to have a higher doping concentration than the first and third polysilicon layers 110 and 150. To form. Accordingly, in the subsequent wet oxidation process, the growth rate of the oxide film is changed according to the doping concentration, so that more oxide films are grown on the sidewalls of the second polysilicon film 130, so that the wet etching process proceeds following the wet oxidation process. As a result, the first polysilicon film 110 and the third polysilicon film 150 can be insulated from each other.

In addition, the first polysilicon film 110 and the second polysilicon film 130 are formed to have the same thickness, and the third polysilicon film 150 is the first polysilicon film 110 or the second polysilicon film. 130 is formed to a thickness of about 3/5 of the thickness. Accordingly, a fourth polysilicon film (not shown) for reconnecting the first polysilicon film 110 and the third polysilicon film 150 insulated by a subsequent process by securing a thickness margin of about 2/5. ) To be deposited.

After the process of forming the capacitor pattern 155, as shown in FIG. 2B, a wet oxidation process is performed on the entire product on which the capacitor pattern 155 is formed to form an oxide film as an insulating film on the outer wall of the capacitor pattern 155. At this time, the oxide layer 160 is formed thicker than the sidewalls of the first and third polysilicon layers 110 and 150 on the sidewalls of the second polysilicon layer 130 having a high doping concentration. .

Subsequently, as shown in FIG. 2C, the oxide layer 160 formed on the outer wall of the capacitor pattern 155 is exposed to the sidewalls of the first and third polysilicon layers 110 and 150 by the wet oxidation process. Wet-etch using the above diluted HF solution. Accordingly, the first polysilicon film 110 and the third polysilicon film 150 are insulated by the oxide film 160 remaining on the sidewalls of the second polysilicon film 130. That is, the second polysilicon film 130 is blocked from the first and third polysilicon films 110 and 150 by the first and second insulator films 120 and 140 and the oxide film 160 to form an upper portion of the capacitor. It serves as an electrode.

As illustrated in FIG. 2D, only the thickness of the third polysilicon layer 150 is 3/5 on the resultant product in which the first polysilicon layer 110 and the third polysilicon layer 150 are insulated. The second polysilicon film 170 having a thickness of 2/5, which is left, is deposited. Accordingly, the insulated first polysilicon film 110 and the third polysilicon film 150 are made of fourth polysilicon. The lower electrode of the analog capacitor including the first polysilicon film 110, the third polysilicon film 150, and the fourth polysilicon film 170 is formed by the film 170. Therefore, the capacitor lower electrode of the laminated structure of the present invention formed in the same area as the planar capacitor lower electrode formed by the prior art is formed to surround the upper electrode, thereby increasing the surface area of the lower electrode of the capacitor. The capacitance can also be improved.

Subsequently, as shown in FIG. 2E, the photoresist is applied to the entire product on which the fourth polysilicon film 170 is deposited, and then an exposure and development process is performed to contact the central portion of the fourth polysilicon film 170. The photoresist pattern 180 defining the hole area is formed.

After the process of forming the photoresist pattern 180, as shown in FIG. 2F, the process of etching the photoresist pattern 180 using an etching mask is performed to form the fourth and third polysilicon layers 170 and 150. The second insulator film 140 is sequentially dry-etched to form the contact hole 190.

Therefore, as described above, when the analog capacitor manufacturing method of the semiconductor device according to the present invention is used, the first and third polysilicon films forming the lower electrode of the capacitor surround the second polysilicon film forming the upper electrode. By forming an analog capacitor so as to increase the surface area of the lower electrode in the same area, it is possible to improve the capacitance, thereby enabling high integration of the semiconductor device.

Claims (8)

On the semiconductor substrate, a capacitor pattern in which a first polysilicon film, a first insulator, a second polysilicon film, a second insulator, and a third polysilicon film are sequentially stacked is formed, wherein the impurity doping concentration of the second polysilicon film is increased. Forming an impurity doping concentration of the first polysilicon film and the third polysilicon film; Forming an insulating film on a side of the second polysilicon film; Forming a fourth polysilicon film to surround the capacitor pattern including an insulating film formed on a side surface of the second polysilicon film so that the first and third polysilicon films are electrically connected by the fourth polysilicon film; Forming a photoresist pattern defining a contact hole region on the fourth polysilicon film; And Forming a contact hole exposing the second polysilicon layer by etching the fourth polysilicon layer, the third polysilicon layer, and the second insulator by using the photoresist pattern as a mask; Way. The method of claim 1, wherein the first polysilicon film and the second polysilicon film are formed to have the same thickness, and the third polysilicon film is formed to a thickness of 3/5 of the thickness of the first polysilicon film or the second polysilicon film. An analog capacitor manufacturing method of a semiconductor device, characterized in that. The method of claim 1, wherein the first polysilicon film and the third polysilicon film are formed by depositing a polysilicon film having the same doping concentration. The analog capacitor of claim 1, wherein the first insulator and the second insulator are formed by selecting at least one of a film formed by a thermal oxide film, a nitride film, a high dielectric constant film, and a combination thereof. Manufacturing method. delete The method of claim 1, wherein the fourth polysilicon film is formed to a thickness of about 2/5 of the thickness of the first polysilicon film or the second polysilicon film. The method of claim 1, Forming an insulating film on the side of the second polysilicon film, Oxidation is performed on the semiconductor substrate on which the capacitor pattern is formed to form an oxide film on the side surfaces of the first to third polysilicon films, and an oxide film thicker than the side surfaces of the first and third polysilicon films on the side surfaces of the second polysilicon film. To be formed, and Etching the oxide films formed on the side surfaces of the first to third polysilicon films so as to remain only on the side surfaces of the second polysilicon film. The method of claim 7, wherein Etching the oxide film formed on the side of the first to third polysilicon film, An analog capacitor manufacturing method of a semiconductor device, characterized in that the wet etching process.

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