KR0176267B1 - Manufacture of semiconductor storage device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, wherein an effective area that can be used as capacitance compared to an existing MVP or SMVP cell is formed by forming a multilayered storage electrode layer by alternately depositing polycrystalline silicon and an insulating material to a predetermined thickness. Because of the wideness, the height of the fleece may be low, thereby reducing the short circuit during wiring, thereby improving reliability, and also simplifying the process, such as no need for flattening due to the step, and protecting the fleece. There is no need, and since process control is easy, there is an effect of improving productivity and yield.

Description

Manufacturing Method of Semiconductor Memory Device

1 is a cross-sectional view showing a method for manufacturing an MVP cell.

2 is a cross-sectional view showing a method of manufacturing an SMVP cell.

3 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

10 gate electrode 20 insulating film

30: first contact hole 40: first polycrystalline silicon layer

40 ': second polycrystalline silicon layer 40' ': third polycrystalline silicon layer

50: first nitride film 50 ': second nitride film

60: island etching mask 70: second contact hole

80: polysilicon stud

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device capable of increasing capacitance, facilitating process control and improving yield.

Since semiconductor random memory (DRAM) has been developed, semiconductor memory devices form storage electrodes on transistors composed mainly of source / drain and gate electrodes to obtain more capacitance in the same area. A stack type cell using the area or a trench formed on the substrate to form a shape of the storage electrode or to improve the dielectric material around a trench type using the groove area. The method has improved the density almost three times every four years, and recently, researches are actively underway to use 256 mega DRAM.

In particular, in the case of the stack type, the surface of the storage electrode is treated at a low temperature, such as unevenness such as HSG. ), The effective area is increased by increasing the effective area or the storage electrode is etched to a certain depth with the uneven shape as a mask. For example, 1992 pp.12 pp of Symphosium on VLSI Technology Digest of Technical Papers Referring to the Micro Villus Patterning (MVP) Technolgy for 256Mb DRAM stack cell described in .13 as follows.

First, in FIG. 1A, a field oxide film 1 is formed on the semiconductor substrate 100 to distinguish between an active region and an inactive region, and then a gate electrode 2 is formed by applying and patterning a conductive material on the active region. After forming a gate insulating film to insulate the gate electrode 2, the transistor is completed by forming a source / drain by injecting impurities onto the substrate 100 using a gate insulating film as a mask.

In order to protect the structures from the subsequent etching process, an insulating material is coated to form an insulating film, and then the insulating film is selectively etched to expose a lower substrate to form a contact hole, and then a spacer 3 is formed on the insulating film side. On top, an insulating material such as BPSG (Boro-Phospho-Silicate Glass) is applied to a predetermined thickness to form the planarization layer 4.

Subsequently, a polysilicon doped with an impurity, for example, a dopant is applied to the entire surface of the resultant, and the lower part is in the form of a column connected to the source / drain through the contact hole, and the upper part is on top of the planarization layer 4. A polysilicon layer 5 is formed so as to be positioned, an oxide film 6 is formed on the polysilicon layer 5 again, and a photoresist is applied, exposed and developed on the oxide film 6 to form a photolithography mask. After the etching process, the oxide layer 6 and the polysilicon layer 5 are etched to remove the photolithography mask.

Thereafter, as shown in (b) of FIG. 1, polycrystalline silicon is grown on the oxide film 6 at low temperature to form HSG (Hemi-Spherical Grain) 7.

Thereafter, as shown in (c) of FIG. 1, the oxide film 6 is etched by applying the HSG 7 as an etch mask, and the etched oxide film 6 is applied as a mask to the polysilicon layer 5. The upper portion is etched to a predetermined depth to complete the storage electrode 5 'having a plurality of villis on the upper portion.

Thereafter, as shown in (d) of FIG. 1, the oxide layer 6 and the planarization layer 4 are removed to use the lower surface of the upper portion of the storage electrode 5 'exposed to the planarization layer 4 as an effective area.

Capacitance when MVP type stack cell formed by the above method is applied to 256Mb DRAM of 0.6μ㎡ ~ 0.8μ㎡ by increasing the effective area available for capacitors per same area by forming the upper structure of storage electrode as a plurality of filaments. Can be improved by 30 fF or more.

However, to obtain more sufficient capacitance, it is necessary to increase the number of fleece or lengthen the fleece. In this case, the longer fleece is more likely to break, and it is difficult to improve the density when increasing the number instead of shortening the fleece. Due to the capillary phenomenon, the etchant (etchant) used during etching of the fleece is difficult to control, such as difficult to control the process.

So, in 1993, A New Stacked Rounded Micro Villus Patterning (SMVP) Cell for 256 Mega and 1 Giga DRAMs, published at pp.886 to pp.888, International Conference on Solode State Device and Materials, Was enclosed by a wall, which will be described with reference to FIG.

First, as shown in FIG. 2A, a transistor is formed on the semiconductor substrate 100 in the same manner as in FIG. 1A, and then an insulating film for protecting the transistor from the subsequent etching process and the insulating film are selectively selected. Etching to form a contact hole, and then a spacer 3 is formed on the insulating film side, and a planarization layer 4 is formed on the insulating film, and a material such as silicon nitride is deposited between the insulating film and the planarization layer 4. To form an etch stop layer.

Subsequently, the lower portion is formed of a pillar connected to the source / drain through the contact hole, and the upper portion is formed of the polysilicon layer 5 so as to be positioned above the planarization layer 4, and the oxide layer is formed on the polysilicon layer 5 again. After forming (6), the HSG 7 is formed on the oxide film 6 differently from the first diagram, and then a photoresist mask 8 is formed by applying, exposing and shaping the photoresist. A PE (Plasma Enhanced) oxide film is applied to the entire surface of the resultant at a low temperature of about 200 ° C. and then etched back to form a spacer 9 surrounding the side of the photolithography mask 8. By etching the oxide film 6 and the polysilicon layer 5 so as to maintain a predetermined distance S from the adjacent cells by applying the photolithography mask 8 and the spacer 9. Remove the photo-etch mask (8).

Thereafter, as shown in (c) of FIG. 2, the oxide film 6 is etched by applying the HSG 7 and the spacer 9, and then the polysilicon layer 5 is applied by applying the etched oxide film 6. The storage electrode 5 'is completed by etching to a depth.

Then, as shown in (d) of FIG. 2, the completed SMVP cell is observed at a predetermined angle from above by removing the spacer 9, the oxide film 6, and the planarization layer 4, and a plurality of fleece outer walls 5 You can see that it is surrounded by protection.

However, even in the SMVP cell as described above, if the length of the fleece is sufficiently long, the fleece is easily damaged, and the step difference is increased, resulting in a high defect rate of the wiring, which lowers the reliability. There is a problem.

Accordingly, an object of the present invention, in order to solve the above problems, by stacking polysilicon and nitride alternately to form a storage electrode pattern and then forming a fleece to increase the effective area of the multi-layer polycrystalline silicon to increase the capacitance It is to provide a method of manufacturing a semiconductor memory device that can be improved.

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor memory device of the present invention for achieving the above object comprises forming a transistor comprising a gate electrode and a source / drain region on a semiconductor substrate, and forming an insulating film for protecting the transistor from subsequent etching. Selectively etching the insulating layer to form a first contact hole to electrically connect a source / drain region and an upper structure; and forming the first contact hole through the contact hole on the entire surface of the resultant after forming the first contact hole. Applying a conductive material to be in contact with the drain region to form a conductive layer forming a lower pillar and a lower layer of the storage electrode; and alternately forming a conductive layer and an insulating material with a predetermined thickness so that the uppermost layer becomes a conductive layer on the conductive layer. Forming a storage electrode layer by laminating; Forming an etch mask, forming a storage electrode pattern mask on the storage electrode layer on which the etch mask is formed, etching the storage electrode layer by applying the storage electrode pattern mask, and etching the storage electrode layer. Selectively etching the center region to expose the lowermost conductive layer, forming a second contact hole, connecting each conductive layer with a conductive material, and applying the grouping etching mask to the lowermost conductive layer. And etching the storage electrode layer until the layer is exposed.

Hereinafter, the present invention will be described in more detail with reference to FIG. 3.

In the method of manufacturing a semiconductor memory device of the present invention, first, as shown in FIG. 3A, a conductive material is coated and patterned on the active region of the semiconductor substrate 100 to include the gate electrode 10 and the source / drain regions. After the transistors are formed, the insulating film 20 is formed to a predetermined thickness to protect the transistors from subsequent etching.

Then, as shown in (b) of FIG. 3, an etching mask is formed on the insulating film 20 and the contact hole 30 is formed by etching the insulating film 20 to expose the lower semiconductor substrate by applying the etching mask.

After the formation of the contact hole 30 as shown in (c) of FIG. 3, polycrystalline silicon, for example, doped with impurities, as a conductive material on the entire surface of the resultant to contact the source / drain region through the contact hole 30. Is applied to form the first polycrystalline silicon layer 40 which forms the lower pillar and the lowest layer of the storage electrode.

Thereafter, as shown in (d) of FIG. 3, the first polysilicon layer 40 on the insulating layer 20 is etched to have a thickness of about 1000 GPa and flattened.

Then, as shown in (e) of FIG. 3, a conductive material such as polycrystalline silicon doped with impurities, for example, and an insulating material such as an oxide film or nitride are deposited on the first polycrystalline silicon layer 40. The first polycrystalline silicon layer 40, the first insulating layer 50, the second polysilicon layer 40 ', the second insulating layer 50', and the third polycrystalline silicon layer are alternately stacked with a predetermined thickness. After forming the storage electrode layer 55 made of 40, polycrystalline silicon is grown on the storage electrode layer 55 at a low temperature of 550 ° C. to 580 ° C. to form an etch mask 60 with HSG.

Thereafter, as shown in FIG. 3B, a photoresist is formed by applying, exposing and developing a photoresist on the storage electrode layer 55 on which the etch mask 60 is formed, and applying the same to the storage electrode layer 55. ) To define the capacitor area.

Thereafter, as shown in FIG. 3, the center portion of the etched storage electrode layer 55 is etched to expose the first polysilicon layer 40 to form a contact hole 70.

The contact hole 70 forming process may be performed in the process of FIG. 3 (bar) as long as only the capacitor region is guaranteed.

Thereafter, as shown in (a) of FIG. 3, a polysilicon stud (STUD) 80 is formed as a conductive material such that each of the polysilicon layers 40, 40 'and 40 is connected through the contact hole 70. As shown in FIG. 3A, a group of etching etching mask 60 on the storage electrode layer 55 is applied to etch the storage electrode until the first polysilicon layer 40 is exposed. Complete the storage electrode with the fleece of.

As described above, according to the present invention, since the polysilicon and the insulating material are alternately deposited to a predetermined thickness to form a multi-layered storage electrode layer, since the effective area that can be used as a capacitance is wider than that of the existing MVP or SMVP cells, It is possible to reduce the height of the wire, thereby reducing the short circuit during wiring, thereby improving the reliability, and also simplifying the process, such as no need for flattening due to the step, and no need for a shield to protect the fleece. Since the process control is easy, there is an effect that can improve the productivity and yield.

Claims (5)

Forming a transistor comprising a gate electrode and a source / drain region on a semiconductor substrate, forming an insulating film for protecting the transistor from subsequent etching, and selectively etching the insulating film to form a source / drain region and an upper portion Forming a first contact hole to electrically connect the structure, and applying a conductive material to contact the source / drain region through the contact hole on the entire surface of the resultant after forming the first contact hole, thereby forming a lower pillar of the storage electrode; Forming a storage electrode layer by alternately stacking a conductive material and an insulating material with a predetermined thickness so that the uppermost layer becomes a conductive layer on the conductive layer, and forming a storage electrode layer on the storage electrode layer; Forming an etch mask, and forming an etch mask Forming a storage electrode pattern mask on the storage electrode layer, etching the storage electrode layer by applying the storage electrode pattern mask, and selectively etching the center region of the storage electrode layer to expose the lowermost conductive layer. Forming a second contact hole, connecting each conductive layer through the second contact hole, and applying the group etch mask to etch the storage electrode layer until the lowermost conductive layer is exposed Method of manufacturing a semiconductor memory device, characterized in that consisting of. The method of claim 1, wherein each of the conductive layers is formed of polycrystalline silicon doped with impurities having a thickness of about 1000 GPa. The method of claim 1, wherein the insulating layer is formed of a nitride or an oxide film having a thickness of about 1000 GPa. The method of claim 1, wherein the connecting of each conductive layer comprises forming a polysilicon stud in a second contact hole after forming the second contact hole. . The method of claim 1, wherein the group etching mask is formed by applying polysilicon at a temperature of 550 ° C. to 580 ° C. 7.