JPS62163374A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device enabling the formation of a second conductivity type impurity diffusion region of high concentration which does not contact with a p-pocket and realizing the simultaneous achievement of high speed and control of a short channel effect, by forming a spacer on the side wall of a gate electrode and by ion-implanting a second conductivity type impurity for activation with these elements used as a mask, etc. CONSTITUTION:After a thin insulation film 23, a polycrystalline silicon film 25 and a conductive film 26 are formed in an insular region of a semiconductor layer 21 of a first conductivity type, a resist pattern is formed, and the periphery thereof is etched selectively to form a gate electrode 29 and an opening 28. Next, an impurity of a first conductivity type is doped through the opening 28 to form a pocket region 30 of high concentration. Then, the conductive film 26, the polycrystalline silicon film 25 and the insulation film 23 other than the gate electrode 29 are removed, and an impurity of a second conductivity type is doped with the gate electrode 29 and an element isolating region 22 used as a mask, so as to form two low concentration impurity diffusion regions 32. Subsequently, a spacer 33 is formed on the side wall of the gate electrode 29, and the impurity of the second conductivity type is doped with the gate electrode 29, the spacer 33 and the element isolating region 22 used as a mask, so as to form two high concentration impurity diffusion region 35.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing a NIO3 type semiconductor device.

[Conventional technology]

In recent years, MO8 type semiconductor integrated circuits have been increasing in density and speed at a color speed. In such integrated circuits, the gate length has been miniaturized, but short channel effects and breakdown voltages have become problems as a result.

5eiki Ogura @tal'''A is a method for manufacturing MOS type semiconductor devices that improves these problems.
T(ALF MICROMOSFET USING DU
BLE IMPLANTED LDD 'rEDM'
82. PP 7 ] 8 to 721 are proposed.

This 21'I will be explained below with reference to the second chapter 1(a) and (b).

1. After selectively forming a field oxide film 2 as an element isolation region on the surface of a p-type silicon substrate 1, a +-2K thermal oxide film 3 is formed on the substrate 1 separated by the field oxide film 2.
form. Subsequently, an impurity-doped polycrystalline silicon film is deposited on the entire surface and patterned to form a gate electrode 4. Using the gate electrode 4 and field oxide film 2 as a mask, p-type impurity ions are implanted into island regions. A p-type region 51r52 is formed in the island region using the same r-type region 4 as a mask, and an n-type region with a shallower junction depth and lower concentration than the p-type region is formed in the island region.
Form regions 61+62 (as shown in FIG. 2(a)).

Next, using the gate electrode 4 as a mask, the thermally dredged film 3 is selectively etched to form an f-) oxide film 7, and a CVD-8IO7 film is further deposited on the entire surface, followed by reactive ion etching (RIE). CvD-8I02 by law
A spacer 8 is formed on the side surface of the r-to-ff electrode 4 by etching the film to the same thickness. Next, gate it pole 4.
Using spacer 8 and field oxide M2 as a mask, n-type impurity is ion-implanted and activated to form n-type regions 91+92.
form. With this step, n-type region 6! and a source region 10 consisting of an n+ type region 91. Arranged Vcn type region 62
and a drain region 11 consisting of an n+ type region 9z are formed. Also, an n-type region 61.

A p-type region is formed in the lower layer of 62 (p blur, to region H) y:zl.

122 remain. Subsequently, a platinum film is deposited on the entire surface and heat treated to form a n+ type region 9 of the substrate 1.
After forming the 1*92 platinum silicide layers 131 and 132, the unreacted platinum film is removed (as shown in FIG. 2(b)). Thereafter, although not shown, a CVD-8R02 film (interlayer insulating film) is deposited according to a conventional method, contact holes are opened, and metal wiring is patterned to complete a MOS type semiconductor device.

In the MOS type semiconductor device manufactured by the method described above, the breakdown voltage is set to the n-type region 6 of the LDD structure.
2 improves the short channel effect by adding n-type region 6
p pocket region 1 additionally provided in the lower layer of 1+62
It can be improved by angles of 21 and 12 degrees.

[Problem that the invention seeks to solve]

However, the above conventional method has the following problems.

(1) p pocket region 12. ．． 12. The purpose of this is to suppress the expansion of the depletion layer from the strain region 11 to the channel region, and to suppress the short channel effect.
Higher concentrations are desirable. However, p
i-ticket area 121, 12. As shown in FIG. 2(b), the p pocket region 121. No2. and n+ type region 919
Since ゜ is in contact with pyJrket area 12! .

If the concentration of 122 is increased, the junction capacitance between them will increase, which will impede speeding up. Therefore, if you try to suppress the short channel effect, you will sacrifice the speed increase, and conversely, if you try to maintain the high speed, you will not be able to suppress the short channel effect.

(2) In the step of forming the n+ type regions 91+92, it is possible to prevent junction capacitance from occurring throughout between the r-type regions 91+92 and the p-type regions 51+52, which are the p&ticket regions formed in the previous step. In order to
It is necessary to make it deeper than the joint depth xj). As a result, a problem arises in that the width of the Qn type regions 61+62 becomes narrower or disappears in some cases due to lateral diffusion caused by the deeper junction depth of the n+ type regions 91+92.

(3) p-type regions 51.5 to become p-pocket regions 121, 122; Since the n-type region fxr62rI'i is formed by double ion implantation, damage to the island region occurs. Although such damage can be recovered by high-temperature heat treatment, a problem arises in which sufficient recovery is not possible due to the shift to a low-temperature process that accompanies the shallowing of the source and drain regions.

The present invention was made to solve the above drawbacks, and
MO8 type semiconductor that can form pocket regions and high-concentration impurity diffusion regions with good control to prevent the generation of junction capacitance, increase speed, and at the same time suppress the short channel effect that accompanies miniaturization. The present invention aims to provide a method for manufacturing semiconductor devices such as integrated circuits.

[Means for solving problems]

The present invention comprises: a step of selectively forming an element isolation region on the surface of a conductive type semiconductor layer; a step of forming a thin insulating film on an island region of the semiconductor layer separated by the element isolation region; After forming a conductive film having selective etching properties around the resist pattern 7 on the entire surface, a process of forming a resist pattern on the patterned film e-) in the area where the electrode is to be formed; The conductive film and polycrystalline silicon film around the turns are selectively processed and etched.
- forming an opening for forming a p/ticket in the second well for forming a gate electrode; doping a first conductivity type impurity into the semiconductor layer deeper than the surface thereof through the opening; After the step of forming a p-high concentration blur region in the layer and removing the conductive film and polycrystalline silicon film other than the gate electrode, unnecessary insulating film is removed to form a gate insulating film. a step of doping the island region with a second conductive 1i type impurity using the yh electrode and the element isolation region as a mask to form two low concentration impurity diffusion regions electrically isolated from each other; forming a spacer on a sidewall of the gate electrode so as to cover at least a surface of the semiconductor layer above the pocket region; a gate electrode;
doping the island region with a second conductivity type impurity using the spacer and the element isolation region as a mask to form two high-concentration impurity diffusion regions electrically isolated from each other. It is something.

The above-mentioned semiconductor layer refers to a semiconductor substrate, a semiconductor layer formed directly or through an insulating layer on a substrate, or a semiconductor layer exposed on an insulating substrate.

Examples of the conductive film include a molybdenum film and a molybdenum silicide film.

[Effect]

According to the present invention described above, spacers are formed on the side walls of the gate electrode, and a second conductive M-type impurity is ion-implanted and activated using these spacers as a mask. A type impurity diffusion region can be formed, and a semiconductor device can be obtained which simultaneously achieves high speed and suppression of the short channel effect as described above.

[Embodiments of the invention]

Hereinafter, an example in which the present invention is applied to the manufacture of an n-channel MO8-IC will be described with reference to FIGS.

First, a field oxide film 22 as an element isolation region was selectively formed on the surface of a p-type silicon substrate 2 by selective oxidation technology. Subsequently, a thermal oxidation process is performed to separate fl from the field oxide film 22, and then a thermal oxide film 23 with a thickness of 2,501 cm, for example, is grown on the island region of the substrate 2, and then boron is applied to the island region for threshold control. A boron ion layer 24 was formed by ion implantation. Thereafter, polycrystalline silicon 25 was deposited, for example, at 4000X on the entire surface, and a molybdenum film 26 at 2000X was further deposited (evaporated) (as shown in FIG. 1(a)).

Next, as shown in the same figure (b), polycrystalline silicon M2
5. A resist pattern 22 was formed on the molybdenum film 26 at a portion where the gate electrode was to be formed by photolithography. Continuing, CC24+02 (70%), 0.28W/cIF?
, 4 pa conditions. At this time, as shown in (c), Regis) /? Only the base (molybdenum film 26) around the turn 27 is etched, and by further etching the exposed polycrystalline silicon, a p-pocket opening 28 is formed and the polycrystalline silicon separated by the opening 28 is etched. An r-to-electrode 29 consisting of a silicon film 25' and a molybdenum film 26' is formed.

The width of this opening 28 can be varied from submicrons to several microns depending on the etching time. The selective etching technique for the underlying layer is described in, for example, the document "5IRIE and Peripheral Etching" by Satoshi Fukano, Sem1conduc.
torWorld, 1983.10.

Next, p-pocket impurities, such as boro/, were ion-implanted at an acceleration voltage of 100 keV and a dose of 5X]O (m).At this time, as shown in FIG. The film 26', the polycrystalline silicon film 25', and the resist pattern 27 act as a mask for the pilon implant, and a p-pocket region 301 is formed which has an undesirable performance peak at 0.25 μm from the surface of the island region exposed from the opening 28. , 302 was formed. In this ion implantation, pyrons were implanted through the thermal oxide film 23, which was used as a mask when removing the remaining molybdenum film 26' and polycrystalline silicon film 25' other than the gate electrode. It's for a reason.

Next, using the resist pattern 27 as a mask, normal etching, for example CC24+02 (30%) RIE, is performed to remove the exposed remaining molybdenum film 26' and polycrystalline silicon film 25', and then the exposed oxide film 23 is selectively etched. A gate oxide film 31 was formed by etching.

Subsequently, the resist pattern 27 is removed, and using the gate electrode 29 and field oxide film 22 as a mask, an n-type impurity such as phosphorus is added at an acceleration voltage of 30 keV and a dose of M.
After ion implantation under the condition of 2.times.10.sup.13 (m2), the ions were activated by heat treatment to form low-degree n-type regions 321 and 322 separated from each other in the island region (as shown in FIG. 3(e)).

Next, the entire surface was coated with c'VD-8Io to a thickness of about 4000X.
After depositing two films, 8102M is etched to the same thickness by RIE to form the p pocket regions 301, 30 . A spacer 33 was formed to cover the surface area of the upper substrate 21.

Next, using the y-to* electrode 29, spacer 33, and field oxide film 22 as masks, ions of an n-type impurity, such as arsenic, are implanted under conditions of accelerated normal pressure of 40 keV and dose of 5X]Ocm, and are activated to mutually interact. Separated high concentration n+ type regions 35t35° were formed. In this step, a source region 36 consisting of an n-type region 321 and an n + type region 351 and a drain region 37 consisting of an n-type region 322 and an n + type region 352 were formed, respectively. In addition, in this example, during the n+ type region activation heat treatment, I”
-Polycrystalline silicon constituting 329 on 11:/'a25
' and MoI)f reacted with each other to form a molybdenum silicide film 34. As a result, a gate electrode 29' made of molybdenum silicide M34 and a polycrystalline silicon film 25' was formed (as shown in FIG. 3(f)).

Next, an insulating film 38 for reflow is deposited on the entire surface, heat treatment is performed at 900° C. for smoothing, opening of the first contact hole 39, deposition of an At film, and formation of source and drain A2 wirings 40 and 41 by pakuning. An n-channel MO8-IC was manufactured by forming an n-channel MO8-IC (as shown in the same figure (g)).

However, according to the method of the present invention, the resist
Molybdenum film 26 with selective etching properties on the surrounding substrate
By etching the underlying polycrystalline silicon film 25 using etching, the gate electrode 29 and the p pocket opening 28 are etched.
can be formed in a self-consistent manner. As a result, pTIF! After forming the ket regions 301 and 302, n-type impurity ions are implanted and activated using the gate electrode 29 as a mask to reduce the concentration of the n-type region 32! , 32
When forming the n-type region 32. .

The pZket region 301 is located at the bottom of the channel region side of 322.
, 302 can be positioned in a self-aligned manner. Therefore, a spacer 33 is formed on the side wall of the gate electrode 29,
Using these as a mask, ng impurities are ion-implanted and activated, resulting in a highly doped n+ type region 351 that does not come into contact with the p pocket 301 +30x. Since 5□ can be formed, it has the following effects.

(1) P pockets 301, 302 and n+ type region 351
．． 35. Since there is no contact with the n+ type region 35135
．． #p pocket region 3 without considering the junction capacitance between
01.302 concentration can be increased. Therefore, the short channel effect that accompanies miniaturization of dimensions can be suppressed as much as possible without hindering the increase in speed.

(2) The depth of the n+ type region 351352 can be freely selected without depending on the depth of the p pocket regions 301 and 302. Therefore, the junction depth of the n+ type region 351352 can be made shallow, and the low concentration n type regions 321, 32 . The width of the regions 321 and 322 is reduced or erased by lateral diffusion.
, and in turn, it is possible to reliably realize the LDD vJ structure, thereby improving the breakdown voltage and improving the Inno 9
It is possible to achieve mitigation of ionization, etc.

(3) For formation of p, 1'P ketone? When performing a single implant, the remaining polycrystalline silicon film 25' and molybdenum film 26' serve as a mask to prevent implant damage to the island region of the substrate 2.

(4) Finally formed goo) [Since the pole 29' is composed of a polycrystalline silicon film and a molybdenum silicide film 34 (polycide structure), its resistance value can be lowered,
This makes it possible to increase the speed.

(5) p pocket, g region 301, 30 . The male type area 351
, 35. By making the depth deeper, it becomes a stopper against the downward wraparound of the depletion layer, making it possible to realize a structure that is even more resistant to the short channel effect.

(6) For pJ ticket generation? Lon in plastic and olx
f-) Boron ions may penetrate through the lower part of the electrode due to channeling, impairing the controllability of vTH.However, in the present invention, since it has a three-layer structure of polycrystalline silicon, molybdenum, and resist, the boron ions can penetrate through the lower part of the electrode. It has a strong structure against

(7) Because of polycide feeding, the experience of conventional polycrystalline silicon gates can be utilized as is.

Note that in the above embodiment, the junction depth of the p pocket region is n+
Although the mold region is made deep, there is no problem in making it the same depth as the n-type region or slightly shallower.

In the above embodiment, the spacer was left as is and used as a part of the interlayer insulating film, but it may be removed by etching before depositing the interlayer insulating film. Su'-san CV'D-S i
For the O2 layer, a material having selective etching properties with respect to the Y-toe electrode material, such as 515N4, may be used.

In addition, in the above embodiment, a molybdenum film is used, and n
Although silicide was performed when activating the + layer, fc may be silicided when activating both the n+ layer and the n1 layer.

In the above embodiment, molybdenum silicide was formed by using a molybdenum film and reacting with polycrystalline silicon, but molybdenum silicide may be used from the beginning instead of molybdenum. In this case, the film thickness of the polycrystalline silicon film, etc. must be optimized separately from the case of molybdenum.

In the above embodiments, the description has focused on a p-pocket, but in the case of a p-channel transistor, VC becomes an n-pocket, which can be manufactured using a similar process.

〔Effect of the invention〕

As described in detail above, according to the present invention, the pocket region and the high-concentration impurity diffusion regions constituting the source and drain regions are formed with good controllability to prevent the generation of junction capacitance therebetween, and to increase the speed. It is possible to improve the breakdown voltage and suppress the short channel effect accompanying miniaturization, and furthermore, it is possible to provide a method for manufacturing semiconductor devices such as MO8 type integrated circuits with high integration, high speed, and high reliability.

[Brief explanation of drawings]

Figures 1 (al to g) are cross-sectional views showing the manufacturing process of an n-channel MO8-IC in an embodiment of the present invention, and Figures 2 (iL) and (b) are cross-sectional views showing the manufacturing process of the conventional MO8-IC. 21... p-type silicon substrate, 22... field oxide film, 25... polycrystalline silicon film, 26... molybdenum film, 27... resist pattern, 28... p2
socket opening, 29.29'...ff-) electrode, 30
1.30g...p pocket, to area, 32! . 322...n fii area, 33... Spacer, 34
...Molybdenum silicide film, 351. 35.・・・
- N+ type region 36... source region, 37... drain/region. Applicant's agent Patent attorney Takehiko Suzue No. 11; 11 1 Figure i) 2 Figure

Claims (4)

[Claims] (1) A step of selectively forming an element isolation region on the surface of a semiconductor layer of a first conductivity type, a step of forming a thin insulating film on an island region of the semiconductor layer separated by this element isolation region, and a step of forming a thin insulating film on an island region of the semiconductor layer separated by the element isolation region. A step of forming a polycrystalline silicon film and a conductive film on the film, a step of forming a resist pattern on the film at a portion where the gate electrode is to be formed, selectively etching the conductive film around the resist pattern, and further etching the exposed polycrystalline silicon film to form a gate electrode and forming an opening for forming a p-pocket; and introducing impurities of a first conductivity type into the semiconductor layer through the opening to a region deeper than the surface thereof. a step of doping to form a pocket region with a higher concentration than the semiconductor layer; a step of removing a conductive film other than the gate electrode and then removing an unnecessary thin insulating film to form a gate insulating film; The island regions are doped with a second conductivity type impurity using the gate electrode and the element isolation region as a mask to electrically isolate the two regions from each other.
forming a spacer on the sidewall of the gate electrode so as to cover at least the surface of the semiconductor layer above the pocket region; 2
A method of manufacturing a semiconductor device, comprising the step of doping the island region with a conductive type impurity to form two high concentration impurity diffusion regions electrically isolated from each other. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the conductive film is made of molybdenum. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the conductive film is made of molybdenum silicide. (4) The method for manufacturing a semiconductor device according to claim 1, wherein the depth of the p-pocket region is equal to or greater than the depth of the high concentration impurity diffusion region.