JPS62179157A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the implantation of impurity ions into a channel region so as to prevent the deterioration of a transistor by a method wherein ion implantation is conducted to form source and drain regions, with an ion-resistant film left on the upper side of a gate forming material. CONSTITUTION:A gate insulation film 3a, a polycrystalline silicon film 4, an ion-resistant film 9 and a resist film 10 are deposited sequentially on the main surface of a semiconductor substrate 1, and the resist film 10 in the uppermost layer is patterned in a desired form. With the resist film 10 used as a mask, the ion-resistant film 9, the polycrystalline silicon film 4 and the gate insulation film 3a positioned in lower layers are removed by etching, and thereafter the resist film 10 is exfoliated. Impurities 7 are implanted by ion-implantation from the surface of the semiconductor substrate 1 and diffused by heating, so as to form an impurity region 6. Then, the ion-resistant film 9 is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a silicon gate MOS transistor.

[Technical background of the invention and its problems]

FIGS. 3 and 4 show new structures of MOS transistors widely used in semiconductor devices.

The transistor shown in FIG. 3 is a normal transistor, and near the surface of a semiconductor substrate 1 there are source and drain regions 1j! of opposite conductivity type to that of the substrate 1. 2.2' are formed, and a gate electrode 4 is formed on the surface of the substrate 1 between the source and drain regions 2, 2' with an insulating film 3 interposed therebetween.

The transistor shown in FIG. 4 is L D D (1,,ig
It is called a doped drain) type 1-transistor, and is used when high breakdown voltage and high reliability are required as elements become smaller. This transistor region is a normal source/drain region 1a2.2'
A source/drain region 2゜2 is placed between the gate electrode 4 and the gate electrode 4.
It has a structure in which an offset region 5.5' having the same conductivity type as ' and having a lower impurity concentration is provided.

Source/drain region [2, 2' and offset region 5
, 5' are formed in a self-aligned manner by ion implantation using the gate electrode 4 as a mask.

FIG. 5 is a cross-sectional view of an element according to steps for explaining a method of manufacturing the MOS transistor shown in FIGS. 3 and 4. FIG.

The semiconductor substrate 1 is thermally oxidized to form a thermally oxidized layer 1113, and polycrystalline silicon, for example, to be an electrode material is deposited on the surface of the thermally oxidized layer 1113 by CVD.
After deposition by the D method, patterning is performed by photolithography to obtain a structure in which this polycrystalline silicon is used as the gate electrode 4, as shown in FIG. 5(a).

Next, as shown in FIG. 5(1)), this gate electrode 4
Using as a mask, impurity 7 is implanted from the surface of substrate 10 by ion implantation technique to form impurity region 6 of the opposite conductivity type to substrate 1. This impurity initial stage t116 becomes source/drain regions 2, 2' or offset regions 5, 5' by a subsequent annealing process.

FIG. 6 is a cross-sectional view of the device for explaining problems in forming the impurity region 6 by ion implantation.

Generally, when forming the source/drain regions 2, 2' and the offset regions 5, 5' in a self-aligned manner, the impurity 7 introduced by ion implantation is also incident on the gate electrode 4, and the impurity 7 is introduced at a certain depth from the surface of the gate electrode 4. The distribution is centered around the

At this time, the implanted impurity 7 penetrates through the gate electrode 4 and the gate oxide film 3 and reaches the channel region 8 in the underlying layer.
The ion implantation process must be designed so as not to degrade the characteristics of the OS transistor.

For this purpose, it is conceivable to make the thickness of the gate electrode 4 sufficiently thick so as to have ion resistance.

However, when miniaturization of elements is required, the surface of the semiconductor substrate 1 needs to be flat, so the thickness of the gate electrode 4 is designed to be as thin as possible.

In such a case, there is a tendency for the impurity implanted into the gate electrode 4 to reach the interface between the gate electrode 4 and the gate oxide film 3, or even to be implanted into the channel fA[8, as shown in FIG. Become stronger.

For example, if the II thickness of the polycrystalline silicon electrode 4 is 1,000, and phosphorus atoms P+ with an energy of 60 ev are implanted as an impurity, then according to LSS theory, 16% of the implanted atoms will be in the gate 1i14 and gate oxide. It reaches the interface with membrane 3. At this time, the thickness of the gate oxide film 3 is 300 mm.
Even if there is A, half of it will reach the channel region 8.

Furthermore, in the case of the LDD type transistor shown in FIG. 4, as the channel becomes longer and the distance 1 between the offset regions 5.5' becomes shorter due to miniaturization, the offset region 5.5' with lower concentration becomes smaller.
It becomes necessary to reduce the parasitic resistance of ′ and maintain the current drive capability. For this reason, it is necessary to increase the number of impurity atoms implanted into the offset region 5.5', thereby increasing the number of impurity atoms that penetrate through the gate electrode 4 and reach the channel region 8.

In this way, in conventional semiconductor device manufacturing methods, impurities are implanted into the channel region depending on the IIN of the gate electrode and gate oxide film, their materials, the type of ions to be implanted, and the ion implantation energy. There is a problem that the control becomes complicated.

Additionally, the following structure has been proposed to prevent implanted ions from reaching the channel region.

This is shown in FIG. 7. After forming a gate insulating film 3a and a conductive II 4 on the surface of a silicon substrate 1, a resist 10 is deposited, and this resist 10 is patterned into a desired pattern. Formed resist g! 10 as a mask, the gate electrode 4 in the lower layer, the goo 1 to the insulation Il! J3a is removed (Fig. 7 (
a)).

Generally, the resist 10 sufficiently absorbs the energy of the ions 7 implanted during the ion implantation shown in FIG. Because it has the ability to prevent the
Deterioration of the MoS transistor can be prevented.

However, in the 0MO3 process, one photolithography process is required for each of the ion implantation process for forming the n+ diffusion layer and the ion implantation process for forming the p+ diffusion layer. At this time, the resist 10 may be left on the gate electrode 4 as shown in FIG. 7 above (see FIG. 8).
a)) For example, in one photolithography step for forming an n+ diffusion layer, a p+ diffusion layer or a region that will become a p+ diffusion layer in the future is shielded with a resist 11 having an etching selectivity that is the same as or sufficiently close to that of the resist 10. When attempting to do this, first, the entire surface is covered with resist 11 (FIG. 8(b)), and when the resist 11 is developed, the resist 10 on the gate electrode is also etched. Put it away. If ion implantation is performed in this state, since there is no material to shield the implanted ions on the gate electrode 4, the implanted ions will penetrate through the gate electrode and reach the channel region of the transistor, degrading the characteristics of the transistor. There is a problem as shown in Figure 8 (C)).

[Purpose of the invention]

The present invention has been made in consideration of the above-mentioned circumstances, and is a method for manufacturing a semiconductor device in which impurities do not penetrate through the gate electrode serving as a mask and enter the channel region when manufacturing a self-aligned MO8T transistor. The purpose is to provide

[Summary of the invention]

In order to achieve the above object, according to the method for manufacturing a semiconductor device according to the present invention, a first step is performed in which a gate insulating film, a Goo 1 to Ti electrode material film, an ion-resistant film, and a resist film are sequentially deposited on the main surface of a semiconductor substrate. a second step of patterning the resist film into a desired shape and etching away at least the underlying ion-resistant film and gate electrode material film using the patterned resist film as a mask; A third step of performing ion implantation using the removed fast ion-resistant film as a mask to form an impurity region on the main surface of the semiconductor substrate adjacent to the gate electrode material film, and a third step of removing the patterned ion-resistant film. It has four steps.

As a result, during ion implantation, the ion-resistant film prevents ions from entering the gate or channel portion, so that deterioration of the MOS transistor can be prevented.

(Embodiments of the Invention) The present invention will be described in detail below based on illustrated embodiments.

FIG. 1 is a cross-sectional view of an element according to steps to explain an embodiment of the present invention. Note that the same parts as in the drawings shown in FIG. 3 and subsequent figures are given the same reference numerals.

First, as shown in FIG. 1(a), a gate insulating film 3a, a polycrystalline silicon film 4, an ion-resistant film 9, and a resist film 10 are sequentially deposited on the main surface of a semiconductor substrate 1, and the uppermost resist film 10 is deposited as desired. pattern into the shape of. Note that a thermal oxide film obtained by thermally oxidizing the semiconductor substrate 1 is normally used as the gate insulating film 3a.

Next, using this patterned resist film 10 as a mask, the underlying ion resistance II 9, polycrystalline silicon film 4, and gate insulating film 3a are removed by etching, and then the resist film 10 is peeled off to form the pattern shown in FIG. 1(b). ) to obtain the structure shown in

Note that here, the gate insulating film 3a, which is the lowest layer, is removed by etching, but if it is possible to implant ions into the semiconductor substrate 1 through this gate insulating film 3a in the subsequent ion implantation process, There is no need to etch the gate insulating film 3a.

Next, as shown in FIG. 1C, impurities 7 are implanted from the surface of the semiconductor substrate 1 by ion implantation, and are diffused by heating to form an impurity region 6 of the impurities implanted into the surface of the semiconductor substrate 1. do.

Thereafter, the ion-resistant film 9 is removed to obtain a structure as shown in FIG. 1(d). Here, the ion-resistant film 9 is used to prevent impurity ions from being introduced into the underlying polycrystalline silicon film 4 during ion implantation, and is made of a material similar to photoresist. It uses a different membrane.

As an ion-resistant film, resist 1-I formed in the upper layer
PJ 10, good visibility, and resist film 10
Therefore, it is necessary to have a large etching selectivity.

Furthermore, when an oxide film is used as the gate insulation 11R3a, the ion-resistant film is the gate insulation 1t! It is also necessary to have a large selection ratio with respect to J3a.

In other words, if the ion-resistant IFli 9 is made of a silicon oxide film, it is not preferable to use such a film as the ion-resistant film 9 because the selectivity with the gate oxide film 3a cannot be achieved and the gate oxide 113a will be side-etched. .

As the ion-resistant film 9 that satisfies these requirements, it is possible to use a film containing the above-mentioned organic substances and metals such as aluminum, titanium, and molybdenum.

In this way, an ion-resistant film is formed to a desired thickness on the top surface of the gate electrode formed of a polycrystalline silicon film to prevent impurities from being implanted into the gate electrode during ion implantation. Ions are prevented from penetrating the gate electrode and entering the channel region.

Furthermore, since the ion-resistant film 9 is peeled off after ion implantation, it is advantageous for miniaturization. This is based on the fact that the gate electrode can be formed thin because there is no fear that impurities will penetrate.

Note that the present invention can be applied to both n-channel MO3) transistors and p-channel MOS transistors.

FIG. 2 is a cross-sectional view showing an example in which the present invention is applied to the 0MO3 process, in which an ion-resistant wA9 with a sufficiently high etching selectivity is formed on the polycrystalline silicon film 4 in the same process as in FIG. It shows.

In this step, since the ion-resistant film is always deposited on the gate electrode 4 during ion implantation, there is no fear that the implanted ions will penetrate through the gate electrode 4.

Although polycrystalline silicon is used as the gate electrode in the above embodiment, a film containing a metal such as aluminum, titanium, or molybdenum, or a metal such as molybdenum, tungsten, or titanium may also be used.

[Effects of the Invention] As described above in detail based on the embodiments, in the present invention, the ion-resistant film is left on the upper surface of the gate forming material and ions are implanted to form the source/drain 9[. Therefore, impurity ions are not implanted into the channel region, thereby preventing deterioration of the transistor.

Furthermore, since the thickness of the polycrystalline silicon film for forming the gate electrode can be formed sufficiently thin, miniaturization can be achieved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an element according to steps for explaining an embodiment of the present invention, FIG. 2 is a cross-sectional view of a cable showing an example of application of the present invention, and FIGS. 5 is a cross-sectional view of the element by process to explain the conventional manufacturing method, FIG. 6 is a cross-sectional view of the element to explain the problems of the conventional manufacturing method, and FIG. 7 is a cross-sectional view of the element during ion implantation. FIG. 8 is a cross-sectional view showing another structure for preventing deterioration of the structure. FIG. 8 is a process-by-step cross-sectional view showing problems that occur when the structure shown in FIG. 7 is applied to the 0MO8 process. 1... Semiconductor substrate, 3a... Gate isolation @ film, 4...
・Polycrystalline silicon film, 6... impurity gA region, 7...
Impurity, 8...Channel region, 9...Ion resistant film, 10°11...Resist film. Applicant's agent Sato-yu 61 Figure 2 Figure (b) Tag 7 z b3 Prisoner 64 Figure (01(b) also 5 Figure Card 6 Prisoner (C) Hi 8 Figure

Claims (1)

[Claims] 1. A first step of sequentially depositing a gate insulating film, a gate electrode material film, an ion-resistant film, and a resist film on the main surface of a semiconductor substrate, and patterning the resist film into a desired shape. a second step of etching away at least the underlying ion-resistant film and the gate electrode material film using the patterned resist film as a mask; A semiconductor comprising: a third step of performing implantation to form an impurity region on the main surface of the semiconductor substrate adjacent to the gate electrode material film; and a fourth step of subsequently removing the patterned ion-resistant film. Method of manufacturing the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a film containing an organic substance or a metal is used as the ion-resistant film.