434707 五、發明說明（1) 5-1發明領域： 本發明係有關於一種具有自我對準金屬矽化製程的高 壓與低壓金屬氧化半導體電晶體的製造方法。本發明的主 要目的在於藉由N+罩幕，其可提供高壓金屬氧化半導體電 晶體上形成金屬矽化物（s a 1 i c i d e ) 5-2發明背景： 近來在半導體元件的需求因大量的使用電子零件而快 速的增加。特別是電腦快速的普及增加了半導體元件的需 求。由=需要數百或是數千電晶體組成很複雜的積體電路 製造在早一半導體晶片上，所以獲得高品質半導體元件是 处Λ °'甬了強化接合崩潰（junction breakd0的434707 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a high voltage and low voltage metal oxide semiconductor transistor with a self-aligned metal silicidation process. The main purpose of the present invention is to provide a high-voltage metal oxide semiconductor transistor to form a metal silicide (Sa 1icide) through an N + mask. Background of the Invention: Recently, the demand for semiconductor elements is due to the large number of electronic components. Fast increase. In particular, the rapid spread of computers has increased the demand for semiconductor components. A complex integrated circuit consisting of = hundreds or thousands of transistors is manufactured on a previous semiconductor wafer, so obtaining high-quality semiconductor components is achieved by strengthening junction breakdown.
子區域到"型梯度摻雜區域，而植入N 的能量通常相當高(大於，因此傳 、冼閘極夕日日矽層中的自我對準 寻 N型梯度掺雜離子的以，晉蔣合夕J匕製fe(sallclde) ’植人 的间此量將會植入到閑極多晶矽層下的 434707 五、發明說明（2) ---- 通道，而造成高電壓元件起始電壓（Vt)漂移； N型梯度摻雜區域不能形成自我對準矽化製程，若形 成自我對準石夕化製程將會使電面㈣而降低接合崩 潰（junction breakdown)的能力 第一A圖與第一β圖係一傳統高壓金屬氧化半導體電晶 體，低壓金屬氧化半導體電晶體，其包含半導體基底1〇〇 、場氧化層1 2 0、多晶矽層1 4 0與梯形摻雜區1 6 〇。假如高 壓金氧電晶體形成自我對準矽化製程，電流將延表面流動 而降低接合崩潰（junction breakdown)的能力。 因此，亟待一種提供具有自我對準金屬矽化製程的高 壓與低壓金屬氧化半導體電晶體的製造方法。 5 - 3發明目的及概述： 鑒於上述之發明背景中，傳統的高壓元件與低壓元件 整合之差異性，而產生的諸多問題，在本發明的目的在於提 供一種方法，達到高壓元件與低壓元件整合的需求，以逐漸 朝向多晶片（multi-chip)整合功能的發展^ 本發明的另一目的在提供一種具有自我對準金屬梦化 製程的高壓與低壓金屬氧化半導體電晶體的製造方法。利Sub-regions to the " type gradient doped region, and the energy of implanting N is usually quite high (greater than, so the self-alignment of the N-type gradient doped ions in the silicon layer is passed through the gate electrode), Jin Jiang He Xi J dagger fe (sallclde) 'This amount will be implanted under the leisure polycrystalline silicon layer 434707 V. Description of the invention (2) ---- Channel, which will cause the high voltage element initial voltage ( Vt) drift; N-type gradient doped regions cannot form a self-aligned silicidation process. If a self-aligned petrified process is formed, the electrical plane will be reduced and the ability to junction breakdown will be reduced. The β picture is a traditional high-voltage metal-oxide semiconductor transistor and a low-voltage metal-oxide semiconductor transistor, which includes a semiconductor substrate 100, a field oxide layer 120, a polycrystalline silicon layer 140, and a trapezoidal doped region 160. If high voltage Metal oxide transistors form a self-aligned silicidation process, and the current will flow across the surface to reduce the ability of junction breakdown. Therefore, it is urgent to provide a high-voltage and low-voltage metal-oxide semiconductor with a self-aligned metal silicide process. Crystal manufacturing method 5-3 Purpose and summary of the invention: In view of the above-mentioned background of the invention, there are many problems caused by the differences between the integration of traditional high-voltage components and low-voltage components. The object of the present invention is to provide a method to achieve high voltage The need for the integration of components and low-voltage components is gradually moving towards the development of multi-chip integration functions. Another object of the present invention is to provide a high-voltage and low-voltage metal-oxide semiconductor transistor with a self-aligned metal dream process. Manufacturing method.
434707 五、發明說明（3) 用此發明，其可提供高壓金屬氧化半導體電晶體上形成金 屬矽化物（sal icide)。 本發明的再一目的在閘極上方提供氮化矽層，其氮化 矽層可防止N型梯度摻雜離子植入時的穿透（channei ing) 效應-'再者，本發明的又一目的在提供一種N+罩幕的設計， 以提供具有自我對準金屬矽化製程的高壓與低壓金屬氧化 半導體電晶體的製造方法。 根據以上所述的目的，本發明提供一種具有自我對 金屬矽化製程的高壓與低壓金屬氧化半導體電晶體的製 方法。其包含半導體基底，其半導體基底定義為高壓金 氧化半導體電晶體與低壓金屬氧化半導體電晶體區域 者，形成複數個場氧化層於半導體基底上方，其兩場 層用以隔離該金屬氧化半導體電晶體□接著，沉積多晶 層於該高壓低壓金屬氧化半導體電晶體之半導體基底^ 。：:後’沉積第-介電質層於多晶矽層上方。❿成光 ?第二介電質層上方’且光阻層用以定義高壓與低壓 乳化半導體電晶體之閘極位置。接著，形成第二光阻屛 低壓金屬氧化半導體電晶體半導體基底上方，利用第丄^ 阻層為硬罩幕植入第一導電離子於高壓金屬氧化半導體 晶體半導體基底内部，即於高壓金屬氧化半導體電晶體之 434707 度摻雜 於閘極 氧化半 高壓與 案與第 接著， 二介電 再利用 氧化半 導體電 後，形 區^緊接 結構兩側 導體電晶 低壓金屬 二圖案於 利用第三 質層直至 第三光阻 導體電晶 晶體之半 成金屬石夕 著，移 ’且形 體之半 氧化半 兩壓金 光阻層 多晶矽 層為罩 體之梯 導體基 化物於 五、發明說明（4) 半導體基底 層。其後， 質層於高壓 方。形成第 上方，分別 化半導體電 刻部分第一 雜區之上表 二導電離子 内部與低壓 著移除第三 第二導電離 内部形成梯 形成間隙壁 與低壓金屬 三光阻層於 定義第一圖 晶體上方’ 電質層與第 面暴露出。 於高壓金屬 金屬氧化半 光阻層。最 子區域上方 除第二光阻 成第二介電 導體基底上 導體電晶體 低壓金屬氧 為罩幕，蝕 層與梯度摻 幕，植入第 度摻雜區域 底内部，接 多晶石夕層與 5-4圖式簡單說明： 第一A圖與第一B圖係一 體電晶體。 習知高壓與低壓金屬氧化半導 第二Α圖與第二Β圖係本發明 氧化半導體電晶體之各步驟的動 構與場氧化層之形成。 實施例中高壓與低壓金屬 作示意圖，其包含閘極結 第三A圖與第三B係本發明 化半導體電晶體之各步驟的動 壁與半導體基底上方二氧化碎 第四A圖與第四B係本發明 實施例中高壓與低壓金屬氧 作示意圖，其包含閘極間隙 之形成。 實施例中高壓與低壓金屬氧 434707 五、發明說明（5) 化半導體電晶體之各步驟的動作示意圖，其包含第三光阻 層之形成。 第五A圖與第五B係本發明實施例中高壓與低壓金屬氧 化半導體電晶體之各步驟的動作示意圖，其包含源/汲極 、金屬矽化物與接觸窗之形成。 主要部分之代表符號： 100半導體基底 1 2 0場氧化層 140多晶矽層 1 6 0 梯形摻雜區 180 源/汲極 2 0 0 氮化矽層 10半導體基底 1 2場氧化層 1 4多晶矽層 1 6 氮化石夕層 18B第二光阻層 20A第一導電離子 2 0 N型梯形摻雜區 2 2閘極之閒隙壁 2 4二氧化矽層 26A、26B第三光阻層 28 N+塱源/汲極區434707 V. Description of the invention (3) With this invention, it can provide a high-voltage metal oxide semiconductor crystal to form a metal silicide (salicide). It is still another object of the present invention to provide a silicon nitride layer over a gate, the silicon nitride layer can prevent a channei ing effect during N-type gradient doped ion implantation-'Further, another aspect of the present invention The purpose is to provide an N + mask design to provide a method for manufacturing high-voltage and low-voltage metal-oxide semiconductor transistors with a self-aligned metal silicidation process. According to the above-mentioned object, the present invention provides a method for manufacturing a high-voltage and low-voltage metal oxide semiconductor transistor having a self-silicon metallization process. It includes a semiconductor substrate. The semiconductor substrate is defined as a region of a high voltage gold oxide semiconductor transistor and a low voltage metal oxide semiconductor transistor region. A plurality of field oxide layers are formed on the semiconductor substrate, and two field layers are used to isolate the metal oxide semiconductor transistor. □ Next, a polycrystalline layer is deposited on the semiconductor substrate of the high-voltage and low-voltage metal-oxide semiconductor transistor ^. :: Post 'deposits a first dielectric layer over the polycrystalline silicon layer. The photoresist layer is “above the second dielectric layer” and the photoresist layer is used to define the gate positions of the high-voltage and low-voltage emulsified semiconductor transistors. Next, a second photoresistor is formed over the low-voltage metal oxide semiconductor transistor semiconductor substrate, and the first conductive layer is used as a hard mask to implant the first conductive ion into the high-voltage metal oxide semiconductor crystal semiconductor substrate, that is, the high-voltage metal oxide semiconductor. The transistor 434707 degrees is doped to the half-high voltage of the gate oxide. After the second dielectric reuses the oxidized semiconductor electricity, the shape region ^ is next to the conductor transistors on both sides of the structure and the low-voltage metal two pattern is used in the third layer. Until the half of the third photoresistor transistor crystal is semi-metallic, the shape of the semi-oxidized half-pressurized gold photoresist layer and the polycrystalline silicon layer is used as the ladder conductor of the cover. 5. Description of the invention (4) Semiconductor substrate Floor. After that, the stratum is on the high-pressure side. Form the upper part, separate the upper part of the semiconductor engraved part above the first impurity region. The second conductive ion inside and the low voltage are removed. The third second conductive ion is formed inside to form a ladder to form a barrier wall and a low voltage metal three photoresist layer. The top layer and the first surface are exposed. For high-voltage metal metal oxide semi-resistive layer. Above the most sub-region, the second photoresist is removed to form a conductive transistor on the second dielectric conductor substrate. The low-voltage metal oxygen is used as a mask. The etching layer and the gradient doped curtain are implanted inside the bottom of the first doped region and connected to the polycrystalline layer Brief description with Figure 5-4: Figure A and Figure B are integrated transistors. Conventional high-voltage and low-voltage metal oxide semiconductors The second A and second B diagrams are the kinematics of each step of oxidizing a semiconductor transistor of the present invention and the formation of a field oxide layer. Schematic diagrams of high voltage and low voltage metal in the embodiment, which include the gate junction, the third A picture and the third B series of each step of the semiconductor transistor of the present invention. B is a schematic diagram of high voltage and low voltage metal oxygen in the embodiment of the present invention, which includes the formation of a gate gap. High voltage and low voltage metal oxygen in the embodiment 434707 V. Description of the invention (5) A schematic diagram of the operation of each step of the semiconductor transistor, including the formation of a third photoresist layer. The fifth diagram A and the fifth diagram B are schematic diagrams of operations of each step of the high-voltage and low-voltage metal oxide semiconductor transistors in the embodiment of the present invention, which include the formation of a source / drain, a metal silicide, and a contact window. Representative symbols of main parts: 100 semiconductor substrate 1 2 0 field oxide layer 140 polycrystalline silicon layer 1 6 0 trapezoidal doped region 180 source / drain 2 0 0 silicon nitride layer 10 semiconductor substrate 1 2 field oxide layer 1 4 polycrystalline silicon layer 1 6 Nitride layer 18B Second photoresist layer 20A First conductive ion 2 0 N-type trapezoidal doped region 2 2 Gate gap 2 2 Silicon dioxide layer 26A, 26B Third photoresist layer 28 N + Er / Drain region
件 元 的 同 相 成體 形晶 ，電 中體 例導 施半 實化 一氧 的屬 明金 發壓 本低 明與 說體 是晶 圖電 體 顯不，晶片提供半 金屬氧化半導體電 6接著，形成複數 場氧化層用以隔離 片送入氧化爐管内 度約在1 0 0到2 5 0埃 氧化矽將作為半導 著以低壓化學氣相 閘氧化層上，以埶 鱗或神，摻入剛沉 。形成氮化砍層1 6 500埃。緊接著， 且第一光阻層用以 434707 五、發明說明（6) 3 0金屬矽化物 32A、32B内金屬介電層 3 4接觸窗 第二A圖與第二B圖 半導體基底定義為高壓 氧化半導體電晶體區域 半導體基底上方1〇，兩 體電晶體。然後，將晶 將表面上的矽氧化成厚 顯示於圖中），這層二 化層（gate oxide)。接 約3000埃的多晶矽14在 入的方式，將高濃度的 ，以降低閘極的電阻率 構上方，其該厚度約為 將晶片經過微影製程， 第10頁 導體基底10，其 晶體與低壓金屬 個場氧化層1 2於 該金屬氧化半導 ’以乾式氧化法 的二氧化矽（未 體電晶體的閘氧 沉積法沉積厚度 擴散法或離子植 積的多晶矽層裡 於多晶矽層1 4結 疋義閉極區域， 定義高壓與低壓 434707 五'發明說明α) Ϊ屬體電晶體之閘極位置β然後將晶片送入蝕刻 ^ ,,Ζ ,未有光阻保護的氮化矽層16、多晶矽層14與 閘氧層加以去除，以形成閘極結構。再著，形成 光 阻層18Β於低壓金屬氧化半導體電晶體區 利用第二光阻層為硬軍幕植入第一導 於南、金屬氧化半導體電晶體之半導體基底1 0内部，即形 成一梯度摻雜區域2 〇於高壓金屬氧化半導體電晶體之半導 體基底1 〇内4。其多晶石夕層1 4上方的氮化;ε夕層1 6用以防止 Ν型梯度摻雜的穿透效應。 第三Α圖與第三β圖顯示，移除該低壓金屬氧化半導體 電晶體其半導體基底上方之第二光阻層18B。接著，利用 低壓化學氣相沉積法（LPCVD)沉積一層二氧化矽（si丨ic〇n dioxide)在晶片上，其厚度約1〇〇〇到2〇〇〇埃。接著，利用 非等向性蝕刻方式將二氧化矽蝕刻，形成閘極〗4側壁上的 間隙壁22。再者，以熱氧化法形成一層二氧化矽層24於高 壓與低壓金屬氧化半導體電晶體之半導體基底上方。 >第四A圖與第四b圖顯示，形成第三光阻層26A與26B於 尚壓與低壓金屬氧化半導體電晶體上方，分別定義第一圖 案與第二圖案於高壓與低壓金屬氧化半導體電晶體上方。 接著，第五A圖與第五β圖顯示，利用該第三光阻層26A與 2 6 B為罩幕，蝕刻部分氮化矽層丨6與二氧化矽2 4層直至該 多晶石夕層16與N型梯度摻雜區域2〇的上表面暴露出。再者The in-phase crystals of the element are formed in the same phase, and the electricity is used to induce semi-realization of oxygen. The low-temperature and low-temperature are the same as the crystals. The wafer provides semi-metal oxide semiconductors. Then, a complex field is formed. The oxide layer is used to separate the separator into the oxidation furnace tube. The silicon oxide is about 100 to 250 angstroms. The silicon oxide will act as a semiconducting low-pressure chemical vapor barrier oxide layer, mixed with steel scales or gods. A nitride cut layer of 16 500 angstroms was formed. Then, the first photoresist layer is used for 434707 V. Description of the invention (6) 3 0 Metal silicide 32A, 32B Inner metal dielectric layer 3 4 Contact window Second A and second B semiconductor substrate is defined as high voltage Oxide the semiconductor transistor region 10 above the semiconductor substrate, two bulk transistors. Then, the silicon is oxidized on the surface to a thickness shown in the figure), which is a gate oxide layer. The polycrystalline silicon 14 with a thickness of about 3000 angstroms is placed in a high concentration to reduce the resistivity of the gate. The thickness is about the thickness of the wafer through the lithography process. Page 10 A metal field oxide layer 12 is deposited on the polycrystalline silicon layer 1 in the metal oxide semiconducting silicon dioxide (dry silicon oxide gate oxide deposition method using a thickness diffusion method or ion-implanted polycrystalline silicon layer). Definition of closed-electrode area, defining high voltage and low voltage 434707 V. Description of the invention α) Gate position β of the metal transistor and then sending the wafer to etching ^ ,, Z, silicon nitride layer without photoresist protection 16, The polycrystalline silicon layer 14 and the gate oxygen layer are removed to form a gate structure. Then, a photoresist layer 18B is formed in the low-voltage metal oxide semiconductor transistor region, and a second photoresist layer is used to implant a hard military curtain into the semiconductor substrate 10, which is first guided to the south and the metal oxide semiconductor transistor, to form a gradient. The doped region 20 is within the semiconductor substrate 10 of the high-voltage metal oxide semiconductor transistor 4. Nitriding over its polycrystalline layer 14 and ε layer 16 is used to prevent the penetration effect of N-type gradient doping. Figures A and B show that the second photoresist layer 18B above the semiconductor substrate of the low voltage metal oxide semiconductor transistor is removed. Next, a layer of silicon dioxide (SiO 2) dioxide is deposited on the wafer by a low pressure chemical vapor deposition (LPCVD) method to a thickness of about 1000 to 2000 angstroms. Next, the silicon dioxide is etched by anisotropic etching to form a spacer 22 on the sidewall of the gate electrode 4. Furthermore, a silicon dioxide layer 24 is formed by a thermal oxidation method over a semiconductor substrate of a high-voltage and low-voltage metal oxide semiconductor transistor. > Figures 4A and 4b show that the third photoresist layers 26A and 26B are formed above the high voltage and low voltage metal oxide semiconductor transistors, and the first pattern and the second pattern are defined on the high voltage and low voltage metal oxide semiconductors, respectively. Above the transistor. Next, the fifth A and fifth β images show that the third photoresist layers 26A and 26B are used as a mask to etch a part of the silicon nitride layer 6 and the silicon dioxide layer 24 to the polycrystalline silicon The upper surface of the layer 16 and the N-type gradient doped region 20 is exposed. Further
第11頁 434707 五、發明說明（8) ’利用該第三光阻層26 A與26B為罩幕，植入第二導電離子 於高壓金屬氧化半導體電晶體之N型梯度摻雜區域2〇内部 與低壓金屬乳化半導體電晶體之半導體基底内部，以形 成半導體電晶體之源/没極，其第二導電離子是以災^離 子表示之。著’移除該第三光阻層。然後， 以磁控直流濺度方式沉積， 其厚度約20ϋΙτί 〇〇〇埃，接著利用高溫，將部分沉積的鈦 膜與高壓與低壓金屬氧化半導體電晶體之半導體汲/源極 28上的石夕及閘極14上的多晶矽反應，形成鈦化矽，而未參 與反應或反應後所剩餘的鈦，以濕蝕刻方式加以去除，在 閘極與源/汲極28三極表面上留下金屬矽化物，即鈦化矽 二用以作為接觸金屬化製程。最後，利用電漿助長型化學 氣相沉積（CVD)沉積—層内金屬介電層32Α與32Β，接著以 微影與蝕刻的製程定義出高壓與低壓金屬氧化半導體電晶 體接觸窗30的位置。 …以上所述僅為本發明之較佳實施例而已，並非用以限 二=發明之申請專利範圍；凡其它未脫離本發明所揭示之 神下所完成之等效改變或修飾應包含在 專利範圍内。 . 甲明Page 11 434707 V. Description of the invention (8) 'Using the third photoresist layers 26 A and 26B as a mask, implanting a second conductive ion into the N-type gradient doped region 20 of the high voltage metal oxide semiconductor transistor The semiconductor substrate of the semiconductor transistor is emulsified with a low-voltage metal to form the source / inverter of the semiconductor transistor, and the second conductive ion is represented by the ion. To remove the third photoresist layer. Then, it is deposited in a magnetron DC sputtering method with a thickness of about 20τΙτί 00 Å. Then, using a high temperature, a part of the deposited titanium film and the high-voltage and low-voltage metal oxide semiconductor transistor semiconductor sink / source electrode Shi Xi are deposited. And the polycrystalline silicon on the gate 14 reacts to form silicon titanate, and the titanium that has not participated in the reaction or remaining after the reaction is removed by wet etching, leaving metal silicidation on the gate and source / drain 28 triode surfaces Material, namely silicon titanate II, is used as a contact metallization process. Finally, plasma-assisted chemical vapor deposition (CVD) deposition-in-layer metal dielectric layers 32A and 32B are used, and then the positions of the high-voltage and low-voltage metal oxide semiconductor electro-crystalline contact windows 30 are defined by lithography and etching processes. … The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the patent Within range. Jia Ming
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