TW449809B - Method of forming semiconductor device by two-step process of metal silicide - Google Patents

Abstract

This invention provides a method of forming a semiconductor device by a two-step process of metal silicide, which consists of following steps: firstly, forming two shallow trench isolation areas in a semiconductor substrate; forming a gate oxide layer on the substrate; forming a polysilicon layer on top of the gate oxide layer; forming a barrier layer on top of the polysilicon layer; defining and etching part of the barrier layer, the polysilicon and the gate oxide layer to expose the underlying substrate; implanting the first ion into the substrate; forming a dielectric layer to cover the gate area and the substrate; then, etching back the dielectric layer to form a dielectric spacer on the side wall of the gate area; implanting the second ion into the substrate; forming the first metal silicide area in the source and drain area; forming a middle layer to cover the substrate and the gate area; then, etching back the middle layer and barrier layer; finally, forming a second metal silicide area in and on top of the polysilicon.

Description

4 4 9 8 0 9 _ES_ 88121743 5. Description of the invention (1) 5 ~ 1 Field of the invention One modification The present invention relates to a method for forming a semiconductor element by a metal silicide process, especially using two metal silicides. Step process to form. 5 ~ 2 Background of the Invention ... Over time, the integration of integrated circuits is getting higher and higher, and the size of semiconductor devices is getting smaller. Therefore, even if the semiconductor device is small enough to measure in Angstroms, it must still be in good condition. The state of use is important. In the past, many complex steps were required in the fabrication of passive components. Especially in the manufacturing of logic circuits for passive components, multi-layer wiring within metal is the main technical key. With the progress of process technology, the future component size will increasingly tend to minimize atomic size. At present, the line width on the production line has reached the width of sub-micron, such as 0.18 micron. At the same time, the goal of manufacturing finished products is also moving towards the high integration of semiconductors. Therefore, with the miniaturization of semiconductor components, a tiny geometric and highly efficient metal oxide semiconductor manufacturing process is difficult.

As shown in Figures A through E, it is a cross-sectional view of a conventional CD crystal structure. In the first A, there is a semiconductor substrate 10 separated from a shallow trench 11 ′, and there may be a P-type well region and an N-type well region (not shown in each figure). 449 80 Case No. 88121743

V. Description of the invention (2) In the first figure B, a gate oxide layer 2 and a gate conductor layer 3 (such as a polycrystalline silicon layer) are formed on a semiconductor substrate by a conventional deposition method, and the oxide layer is formed. 12 performs a pattern transfer procedure with the gate conductor layer 丨 3. A As shown in the first c diagram, a lightly doped source / drain region 14 is formed by a lightly doped source method (LDD). And in the first D picture, a gap wall is formed! 5. Then, the source / drain region 16 is formed by ion implantation and the like, and the source / drain region 6 is annealed. Then, as shown in the first E diagram, a silicide 7 (self-aligned lithography) is simultaneously formed on the source / drain region 16 and the surface of the gate conductor layer 3. For Ultra-Shallow Junction Drain / Source

Sou ^ ce / Drain) lower contact leakage (Junction Leakage) current. ’The thickness of the self-aligned silicide reduces Q. So, in the polycrystalline dream (

The thickness of self-aligned Saiicik on Polysilicon) will also decrease. This will increase the actual chip resistance. Therefore, in the semiconductor process, the above problems should be effectively improved. At the same time, in the process of very large integrated circuits, it is easy to widely use the self-aligned silicide process. 5-3 Invention Purpose and Overview:

449 80 V. Description of the invention (3) In view of the many shortcomings of the traditional process in the above background of the invention, the present invention provides a two-step metal silicide process to form a source / drain and polycrystalline silicon gate structure. One of the objectives of the present invention is that the source / drain electrodes will not be bridged together, because there is a relatively common occurrence of Product i on Widow. The sheet resistance of the polycrystalline stone sluice can be completely removed. And in the new-generation 0.25 micron process, the sheet resistance of the source / drain can be optimized. Titanium self-aligned silicide (Ti SaHcide) process can be applied to the new generation semiconductor device process of 0.25 micron. A method using silicon metal includes a semiconductor substrate. Then a gate silicon layer is formed in the semi-conductive region and the semi-conductive region is respectively implanted into the semiconductor substrate. The side wall of the gate is oxidized and etched between the body substrate as a body substrate cover. Then, go on. According to the above-mentioned purpose, the present invention provides a method for forming a semiconductor element by a two-step process of chemical compounds. The following steps: First, form two shallow trench isolation regions within. The shallow trench isolation regions are separated from each other by an active region for oxidation. Layer on a semiconductor substrate. Thus, a polycrystalline layer is formed. Following this, a barrier layer is formed on the polycrystalline silicon layer. A gate region formed by the damaged barrier layer 'polycrystalline stone layer and the gate oxide layer until exposed' is generally located in a shallow trench trench where the source region is between the shallow trench isolation region and the gate oxide layer. With a drain region. Re-implantation of the first-in-ion 'system uses the gate region and the shallow trench isolation region as one to form a dielectric layer covering the gate region and the semiconductor residual dielectric layer to form a dielectric gap wall on the gate. And a second ion is implanted into the semiconductor substrate to lock the brake

Page 7 449809 _ Case No. 88121743 V. Description of the Invention (4) The concentration of the conductive type of the dielectric gap wall and the sub-concentration is greater than that of the source and drain substrates. The medium.然 Surface. The final square ’is borrowed by heating the drain region.

After the shallow trench is separated from the polar region of the second ion, the inner region and the non-polar region will not interact with the substrate, and the etch-back region will be a conductive type. The reforming is a heating region, in which the first metal is reversed to a gate-retaining region of a second interposer. The interposer and the barrier metal silicide metal are polycrystalline and do not produce implanted photomasks. To form a first reaction, the first gate region should be β, so it acts as a multi-barrier layer to display a region that is superior to the poly-silicon layer. Among them, the first metal silicon and the metal barrier form a crystal dream and a polycrystalline crystal. The semiconductor layer of the source ionization region and the intermediary metal of the intermediate layer of the stone layer and the upper region and In order to make the above description and other purposes of the present invention 'features and advantages easier, only' the preferred embodiments are listed below in conjunction with the accompanying drawings' for detailed description. 5 to 4 diagrams are briefly explained: the first A to the first E diagrams, showing the traditional structure diagrams; and the first A to the second g diagrams showing the cross-section and structure diagrams of the present invention. Representative symbols of the main parts of the present invention: 10 semiconductor substrate 11 shallow trench isolation

Page 8 4 Sentence 809 _ Case No. 88121743_ Year Month Date _ V. Description of the invention ⑸ 12 N-type and P-type source / drain 13 Gate oxide layer 14 Gate oxide layer 15 Source / drain region 16 Gap wall 17 Gold metal compound 21 Semiconductor substrate 22 Shallow trench isolation 23 Gate oxide layer 24 Polycrystalline silicon layer 25 Barrier layer 26 Barrier wall 27 First ion source / drain region 28 Second ion source / drain region 29 Dielectric layer 30 First metal silicide region 31 Second metal silicide region 5-5 Detailed description of the invention: The following is a description of the present invention. The description of the present invention will first be made with reference to an exemplary structure. Some variations and advantages of the invention will be described later. The preferred method of manufacture will be discussed later.

Page 9! R! Se4 4 · 狰 稃 j 瘛 88121743___ Car month B Amendment r 5. Description of the invention ⑹ '--- Further' Although the present invention is taught in several embodiments, these interpolations do not limit the present The scope or application of the invention. Moreover, although this is the case, it is clear that the main part may be replaced by the relevant part. Therefore, the semiconductor element of the present invention does not limit the description of the structure = 'These elements include proof of the utility and usefulness of the present invention and the preferred embodiments presented. And even though the present invention is described by way of example and by citing a preferred embodiment, the present invention is not limited to the illustrated embodiment. In addition, 'anything that does not depart from the spirit disclosed by the present invention All equivalent changes or modifications are included in the scope of patent application of the present invention. The broadest definition should be used to explain the scope of the present invention 'to include all of these modifications and similar structures' " In the present invention, such a two-step process for forming a semiconductor device using a metal silicide, includes the following: Steps: First, as shown in the second A diagram, two shallow trench isolation areas 22 are formed in a semiconductor substrate 21, and the shallow trench isolation areas 22 are mutually opened by an active area. 2 For another example, as shown in FIG. 2B, a gate oxide layer 23 is formed on the semiconductor substrate 1 β, and then a polycrystalline silicon layer 24 is formed on the gate oxide layer 23. 25 followed by the formation of a barrier layer 25 on the polycrystalline silicon layer 24. Forming the barrier layer The material is a silicon oxide and the thickness of the barrier layer 25 is about 100 to 700. At this time, h Μ

The barrier layer 25 of the meaning and the engraved part on page 10, the polycrystalline silicon layer 24 and the gate oxide 449809 _η amendment number 8812] 7α 5. Description of the invention (7) Layer 2 3 until the semiconductor substrate 2 1 is exposed. A gate region is formed generally between the shallow trench isolation regions 22, and the regions between the shallow trench isolation regions 22 and the gate oxide layer 23 are used as a source region 27 and a drain region 27, respectively. Therefore, a first ion is implanted into the semiconductor substrate 21 again, and the gate region and the shallow trench isolation region 22 are used as an implanted photomask. Then the semiconductor is etched back. Then, the region 2 region 2 region 2 2 conductance concentration. The well area is separated first, such as the substrate 21. The dielectric layer is formed by implanting a beta phase, which is an implanted electrical phase. The gate and the second and second C patterns are formed into a dielectric layer to cover and form the dielectric material. The electrical spacer 26 is used as a mask in the gate region of the second ion on the semiconductor substrate, and the same type, and at the same time, the closed region of the second oxide layer 23 is formed with the shape of the dielectric spacer 26 and the conductivity of the first ion. Before the concentration of the conductive ions is larger than the area 2 2, there is a conductive type in the isolation area, and the conductive type of the ions. Gate area with a silicon oxide. Then on the side wall of the domain, a source / modest shallow trench isolation type is formed between the second ion and the first ion, as opposed to the first D picture, and then a first-metal silicide region 30 is formed on the source. In the electrode and drain regions, this is the first metal and semiconductor substrate that reacts thermally in the source and drain regions, where the gate region is protected by a barrier layer and a dielectric spacer without contacting the first Metal reaction. The first metal is metal titanium, and the thickness of the first metal silicide region is about 2000 to 600 Angstroms. Therefore, as shown in the second E diagram, the interposer 29 is formed to cover the semiconductor substrate. # 21㈣ 才 圣 H U is used as the dielectric of the polycrystalline silicon and the gold shoulder. Page 1 44 44 8

The silver return interposer 29 and the barrier layer 25 are displayed and then 'as in the second F picture, the surface β of the polycrystalline silicon layer 24, and finally as in the second G picture, a second metal silicide region is formed in and above the silicon. The second metal and the polycrystalline silicon layer are reacted by thermal reaction, and the middle: the extremely non-polar region is protected by the interposer and does not react: while the first metal is condensed, and the thickness of the second metal silicide region is about 400 to 1,000 DJ 4υυ According to the preferred embodiment of the present invention, the advantages of the present invention will be: ^ 1 · The source / infinity will not be bridged together because of the wider generation window (

Production Window). 2. The sheet resistance of the polysilicon gate can be effectively reduced. 3. In the new generation 0-25 micron process, the sheet resistance of the source / drain can be optimized. 4. The Chi Sal self-aligned silicide (Ti Salicide) process can be applied to the semiconductor device process of the new generation of 0.25 microns. Therefore, in the present invention, the method for forming a semiconductor device by a two-step process of metal silicide may briefly include the following steps: first, forming two shallow trench isolation regions in a semiconductor substrate; the shallow trench isolation regions are mutually Separate by an active area. A gate oxide layer is formed on the semiconductor bottom

Page 12

Wood. Thus, a polycrystalline silicon layer is formed on the gate oxide layer. Subsequently, a barrier layer is formed on the polycrystalline silicon layer. The barrier layer is defined and etched. The polycrystalline stone layer and the oxide layer are exposed until the semiconductor substrate is exposed. The formed-electrode region is generally located between the shallow trench isolation regions, and the shallow trench isolation regions and The regions between the gate oxide layers serve as a source region and a drain region, respectively. Re-implanting a first ion into the semiconductor substrate 'uses a gate region and a shallow trench isolation region as an implanted photomask. Next, a dielectric layer is formed to cover the gate region and the semiconductor substrate. Then, the etch-back dielectric layer forms a dielectric spacer on the sidewall of the gate region. Then, a second ion is implanted in the semiconductor substrate, and the gate region is used. The dielectric spacer wall isolation region is an implanted photomask. The conductive type of the first ion is the same, and the concentration of the second ion is the same. Greater than the concentration of the first ion. A first metal silicide region is formed in the source and drain regions, and the first metal and semiconductor substrate are reacted in the source and drain regions by thermal reaction. The gate region is formed by a barrier layer and a dielectric. The bulkhead is protected from reacting with the first metal. Thus, an interposer is formed to cover the semiconductor substrate and the gate region 'as a dielectric between polycrystalline silicon and metal. Then 7 times of silver interposer and barrier layer to reveal the surface of the polycrystalline silicon layer. Finally, the second metal petroxide region is inside and above the polycrystalline silicon, and the second metal and the polycrystalline silicon layer are thermally reacted. The source region and the drain region are protected by the interposer layer without reacting. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed in the present invention 2 should be included in the following Application

Year Month Amendment 449 80, I SB12ma V. Description of Invention (10) Within the scope of patent 〇 page 14

Claims (1)

449809 __Case No. 88121743__ Year, Month, and Day Amendment_ 6. Application Patent Scope 1. A metal sanding process at least includes: forming two shallow trench isolation areas in a semiconductor substrate, and then forming a gate oxide layer on the substrate On the substrate, and a conductive layer is formed to cover the active area of the semiconductor substrate, a barrier layer is formed to cover the conductive layer, and a gate region formed by the barrier layer is defined and etched It is roughly located between the shallow trench isolation regions, where the areas between the two shallow trench isolation regions and the gate oxide layer are respectively used as a source region and a drain region; a dielectric gap wall is formed between On the sidewall of the gate region; forming a first metal silicide region in the source and the drain region to thermally react the first metal and the semiconductor substrate in the source region and the drain Region, wherein the gate region is protected by the barrier layer and the dielectric gap wall without reacting with the first metal; a dielectric layer covers the semiconductor substrate and the gate region; forming, 〆, kiss ( 2Z Qi, return name The dielectric layer and the barrier layer to reveal the surface of the conductive layer; and forming a second metal silicide region within the polycrystalline silicon to react with the upper system, a second metal and the conductive layer, wherein the source The electrode drain region is protected by the dielectric layer and does not react. 20% of the material is required; == trench :; the isolation region is structured in which the above conductive layer includes at least 3. If the scope of the patent application is the first item The manufacturing process includes polycrystalline bite. 449809 _Case No. 88121743_Year_Month_Revision _ VI. Patent application scope Contains silicon oxide. 5. As in the process of applying for the scope of item 1 of the patent, wherein the above dielectric spacers contain at least silicon oxide. 6. For the process of applying for the scope of patent application item 5, wherein the dielectric spacer is formed by a silicon oxide layer, which surrounds and covers the gate area, and then etches back the silicon oxide layer until the source and drain portions This semiconductor substrate is exposed. 7. For the process of applying for item 1 of the patent scope, wherein the thickness of the barrier layer 层 is about 100 to 700 angstroms. 8. For the process of applying for item 1 of the patent scope, wherein the first metal and the second metal are metal donations. 9. For the process of claim 1 in the scope of patent application, wherein the thickness of the first metal silicide region is about 2000 to 600 Angstroms. 10. The process according to item 9 of the scope of patent application, wherein the thickness of the second metal dream region is about 40 to 1,000 angstroms. 11. A method for forming a semiconductor element by a two-step process of metal silicide, comprising at least: forming two shallow trench isolation regions in a semiconductor substrate, and forming a gate oxide layer on the semiconductor substrate to form a polycrystalline silicon layer Oxidation at the gate Page 16 ^ ^ 9 8 0 q ....... --88121743 _ month date ___ repair thousand __ VI. Patent application scope layer 'form a barrier layer on the polycrystalline silicon layer, definition A gate region formed by the barrier layer 'the polycrystalline silicon layer and the gate oxide layer until the semiconductor substrate is exposed' with the etched portion is generally located between the shallow trench isolation regions', in which the two shallow trenches The region between the trench isolation region and the gate oxide layer is used as a source region and a gate region, respectively; a first ion is implanted into the semiconductor substrate, and the gate region is used to isolate the shallow trench. A region is an implanted photomask; a dielectric layer is formed to cover the gate region and the semiconductor substrate; silver is returned to the dielectric layer to form a dielectric gap wall on a sidewall of the gate region; implanted A second ion in the semiconductor substrate uses the gate region, the dielectric gap wall and the shallow trench isolation region as an implanted photomask, wherein the special electric type of the first ion and the second ion The conductivity type is the same, and the concentration of the second ion is greater than that of the first ion. Concentration; forming a first metal silicide region in the source and the drain region 'to react thermally with the first metal and the semiconductor substrate in the source region and the drain region', wherein the gate region Protected by the barrier layer and the dielectric spacer without reacting with the first metal; forming an interposer to cover the semiconductor substrate and the gate region as a medium between polycrystalline silicon and metal; An interposer and the barrier layer to reveal the surface of the polycrystalline silicon layer; and forming a second metal silicide region inside and above the polycrystalline silicon to thermally react the second metal and the polycrystalline silicon layer, wherein the source electrode The region and drain region are protected by the interposer and do not react. Page 17 Che Yueyue No. 4 · 4 9 8 ι ?. ΐ 7 六. Method of applying for patent Fan Yuan patent scope No. 12 'where the above barrier layer is at least 13. Such as the method of patent scope No. 11 'Wherein the above-mentioned medium contains oxidized stone. Stomach at least 14. The method of claim 11 in which the above resistance is about 100 to 700 angstroms. Thickness of the sacrificial layer 15. The method according to item 11 of the scope of the patent application, wherein the first metal and the second metal are metal convergence. 16. The method according to item 11 of the scope of patent application, wherein the thickness of the first metal silicide region is about 200 to 600 angstroms. 17. The method of claim 16 in which the thickness of the second metal silicide region is about 4,000 to 10,000 angstroms. The method further includes forming a well region between the gate and the oxygen, wherein the well region is opposite to the first ion and the second ion. 1 8. According to item 丨 2 of the scope of patent application, there is a conductive type in the area of the isolation region, and the conductive type is a conductive type of ions.