TW451422B - A metal-oxide semiconductor field effect transistor and a method for fabricating thereof - Google Patents

A metal-oxide semiconductor field effect transistor and a method for fabricating thereof Download PDF

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TW451422B
TW451422B TW087118740A TW87118740A TW451422B TW 451422 B TW451422 B TW 451422B TW 087118740 A TW087118740 A TW 087118740A TW 87118740 A TW87118740 A TW 87118740A TW 451422 B TW451422 B TW 451422B
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TW087118740A
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Jeong-Seok Kim
Yong-Jik Park
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

Disclosed are an improved source/drain junction configuration in a metal-oxide semiconductor field effect transistor and a novel method for fabricating thereof which utilizes double sidewall spacers so as to provide double heavily doped source/drain junction regions i.e. first heavily doped shallow junction region and second heavily doped deep junction region. The double heavily doped source/drains region are advantageously formed to suppress short channel effect, prevent current leakage, and reduce sheet resistance. The double heavily doped junction regions are fabricated by depositing a first and a second insulating layer over the gate electrode configuration and over the semiconductor substrate at high energy, etching the second insulating layer to form a first sidewall spacer, first implanting impurities into the semiconductor substrate, removing the first sidewall spacer, etching the first insulating layer to form a second sidewall spacer, second implanting impurities into said semiconductor substrate at relative low energy in comparison to the first implanting, and annealing to form a heavily doped shallow junction region and a heavily doped deep junction region.

Description

1514 21514 2

4073pir.d〇c/00S A7 B7 發明説明（I ) 發明領域 本發明是有關於一種半導體元件及其製造方'法’且 特別是有關於一種金氧半場效電晶體及其製造方法° 皆景說明 DRAM記億胞元件是由記憶胞陣列區以及週邊邏輯 區所組成。記憶胞陣列區包含了金氧半場效電晶體以及與 金氧半場效電晶體的源極/汲極區電性連接的儲存電極 (Storage Nodes)，以岌具有由PMOS電晶體與NMOS電晶 體所組成之CMOS區域的週邊邏輯區。 隨著近來半導體工業所生產的積體電路漸趨複雜， 積體電路元件不但在平面的尺寸上減小，同時在垂直於元 件表面的厚度上也有減小的現象。如果金氧半場效電晶體 的厚度不隨著平面尺寸的減小而減小，那麼就會產生一些 問題，例如電子擊穿現象等。因此，除了縮小的平面尺寸 之外，如何製作一個具有較淺介面之源極/汲極區的金氧 半場效電晶體就成爲一個重要的課題。 雖然淺介面可以減少短通道效應的發生’但是減小 介面的截面積卻會增加源極/汲極區的片電阻（Sheet Resistance)値。 第1圖繪示習知的一種在N型半導體基底的表面上 具有場效電晶體之DRAM元件的剖面示意圖。 請參照第1圖，其中，記憶胞陣列區’ NM0S電晶 體區以及PMOS電晶體區，這三個元件區的周圍都被場氧 化層12所環繞，並且在NMOS電晶體區形成有一個P井 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297公楚） 】.-.+ I1.. I Ι|· ·ί·ί-|'ι | 1 . .«^.ιί·.·Γι·>νί·» · (諳先閱讀背面之注意事項再"寫本頁 .裝. 訂 A7 B7 4 514 2 24073pir.d0c / 00S A7 B7 Description of the Invention (I) Field of the Invention The present invention relates to a semiconductor element and a method for manufacturing the same, and more particularly to a metal-oxide-semiconductor field-effect transistor and a method for manufacturing the same. This shows that the DRAM memory cell element is composed of a memory cell array area and a peripheral logic area. The memory cell array area includes metal-oxide-semiconductor half-field-effect transistors and storage nodes (Storage Nodes) electrically connected to the source / drain regions of the metal-oxide half-field-effect transistors. The peripheral logic area of the CMOS area. With the recent increasing complexity of integrated circuits produced by the semiconductor industry, integrated circuit elements are not only reduced in size in a plane, but also reduced in thickness perpendicular to the surface of the element. If the thickness of the metal-oxide half-field effect transistor does not decrease as the plane size decreases, then some problems will occur, such as electron breakdown. Therefore, in addition to the reduced planar size, how to make a gold-oxygen half field-effect transistor with a shallower source / drain region has become an important issue. Although a shallow interface can reduce the occurrence of short channel effects ’, reducing the cross-sectional area of the interface will increase the sheet resistance in the source / drain region 区. FIG. 1 is a schematic cross-sectional view of a conventional DRAM device having a field effect transistor on the surface of an N-type semiconductor substrate. Please refer to FIG. 1, in which the memory cell array region 'NM0S transistor region and the PMOS transistor region are surrounded by the field oxide layer 12, and a P well is formed in the NMOS transistor region. 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297).】 .-. + I1 .. I Ι | · · ί · ί- | 'ι | 1.. «^. Ιί ·. · Γι · ≫ νί · »· (谙 Please read the precautions on the back before writing this page. Equipment. Order A7 B7 4 514 2 2

4073pii'.doc/00S 五、發明説明（>) (P-type Well)14。而在各個元件區上方都具有一個閘極結 構16，且這個閘極結構16是由第一導電層I 6a，第二導 電層16b以及絕緣層16c重疊所構成。以習知技藝在閘極 結構16與半導體基底10之間沉積一層閘極氧化層（未繪 示於圖中），並且形成間隙壁緊接於閘極結構16的側邊。 並且，分別在NMOS區形成深度較淺且具有N型導電性 的輕摻雜源極/汲極介面區18與濃摻雜介面區20，以及在 PMOS區形成深度較淺且具有P型電性的輕摻雜源極/汲極 介面區與濃摻雜介面區。之後，形成一層絕緣層22覆蓋 於半導體基底與場效電晶體上。絕緣層22在整個半導體 基底10上的厚度並不一定，這是由於其下方的半導體基 底10的表面上具有特定元件，因此半導體基底10的表面 不平坦所造成。接著，在絕緣層22形成一個到達淺源極/ 汲極區18與20的接觸窗開口 23，並且以導電物質塡滿接 觸窗開口 23以形成一個接觸電極24。 在蝕刻絕緣層22以形成接觸窗開口 23的製程步驟 中，由於絕緣層22受到半導體基底10的表面結構的高度 不同而具有不同的厚度，因此發生過度鈾刻到淺源極/汲 極區18的現象發生。在過度蝕刻較爲嚴重的例子中，具 有歐姆式接觸的重摻雜介面區20會被蝕刻到，以至於使 接觸電阻與介面的漏電流都會增加。 根據上述形成淺介面的方法，在形成接觸窗開口 23 時會有缺點，而且會因爲重摻雜區的深度較淺而有較高的 片電阻値，而高片電阻値則會降低電晶體的電流。 5 本紙張尺度適州中國國家^準（CNS ) A4規格(210X297公釐Γ (請先閱讀背面之注意事項再填寫本頁) ”裝- 訂 .良 4514 2 4073pif.dac/008 A7 B7 五、發明説明（b) 發明槪沭 因此，本發明的目的就是在提供一具有較佳之源極/ 汲極結構組態的金氧半場效電晶體及其製造方法。這種製 造金氧半場效電晶體的方法可以防止短通道效應，並且抑 制接觸電阻與漏電流的增加。本發明的主要特徵爲利用雙 重間隙壁技術，且在不增加微影製程步驟的情況下，形成 一個第一重摻雜淺介面區緊接於通道區以及一個與金屬接 觸插塞連接的第二重摻雜深介面區。 根據本發明之上述及其他目的，提出一種製作金氧 半場效電晶體的方法，此方法包括在半導體基底上形成一 個閘極結構。此閘極結構包括一個閘極氧化層與一個閘極 導電層。之後，以閘極結構爲罩幕，將低濃度的第一離子 雜質植入半導體基底，以形成一個輕摻雜汲極區。第一離 子雜質可爲N型或是P型，較佳的方式是以lOkev到201cev 的能量植入濃度在1X1012到lxl〇l4atoms/cm2的磷或是砷 等N型離子。之後，在閘極結構與半導體基底上沉積厚度 分別爲20nm至lOOnm的第一絕緣層與第二絕緣層，第一 絕緣層與第二絕緣層之間具有不同的蝕刻選擇率。第一絕 緣層的材質比如爲氮化矽，而第二絕緣層的材質比如爲氧 化物。接著，蝕刻第二絕緣層以形成第一間隙壁。以閘極 結構，第一絕緣層與第一間隙壁爲罩幕，進行第二次離子 摻雜，對半導體基底植入與第一次離子摻雜具有不同導電 型的高濃度離子 > 使得在比輕摻雜汲極區距離半導體基底 更遠的位置形成第一重摻雜深介面區。對於N型基底而 6 (請先閱讀背面之注意事項再填寫本頁) -裝' 、一s° 本紙張尺度適扣中國國家標準（CNS ) A4規格（210X297公釐） fs. 4 4073 pii\doc/008 B7 五、發明説明（It ) 言，以25kev至40kev的高能量，植入濃度約爲1X1015 到5X1015 atoms/cm2的P型雜質，其中，P型雜質比如爲 二氟化硼。另一方面，如果半導體基底爲P型，則植入N 型雜質，比如爲砷。接著，移除第一間隙壁，並且回蝕刻 第一絕緣層，在閘極結構的側邊形成第二間隙壁。以閘極 結構與第二間隙壁爲罩幕，對半導體基底植入與第二離子 摻質具有相同電性的第三離子摻質。第三次離子植入是以 比第二次離子植入的25kev至40kev還低的能量，lOkev 至 20kev 進行，以在第一摻植層(Firstlmpurities-Implanted Layer)與第二摻植層之間形成一個第二重摻雜淺介面。. 在本發明中，以雙重間隙壁技術形成的第一重摻雜 淺介面區與第二重摻雜深介面區，具有抑制短通道效應， 防止漏電流以及降低片電阻的優點。 本發明所揭露的金氧半場效電晶體包括：一個位於 具有第一導電型的半導體基底上的閘極結構；一個位於半 導體基底之中，並且從閘極結構的側邊延伸出去的輕摻雜 淺介面區；一個間隙壁，與閘極結構的側邊連接並沿著輕 摻雜介面區的上表面延伸；一個第一重摻雜介面區，具有 與第一導電型不同的第二導電型，位於深度比輕摻雜淺介 面區深的半導體基底中，與輕摻雜介面區相連接並形成第 一垂直界面，此第一垂直界面與間隙壁的側邊相連接；一 個具有第二導電型的第二重摻雜介面區，位於深度比第一 重摻雜介面區深的半導體基底中，與第一重摻雜介面區相 接，並且在距離間隙壁之側邊一段特定距離的位置形成第 7 A7 (請先閱讀背面之注意事項再磕窍本頁) 裝·4073pii'.doc / 00S V. Description of the Invention (P-type Well) 14. A gate structure 16 is provided above each element region, and the gate structure 16 is formed by overlapping the first conductive layer 16a, the second conductive layer 16b, and the insulating layer 16c. A gate oxide layer (not shown in the figure) is deposited between the gate structure 16 and the semiconductor substrate 10 by a conventional technique, and a gap wall is formed next to the side of the gate structure 16. In addition, a lightly doped source / drain interface region 18 and a heavily doped interface region 20 having a shallow depth and N-type conductivity are formed in the NMOS region, and a shallow depth and P-type electrical characteristics are formed in the PMOS region. Lightly doped source / drain interface region and heavily doped interface region. After that, an insulating layer 22 is formed to cover the semiconductor substrate and the field effect transistor. The thickness of the insulating layer 22 over the entire semiconductor substrate 10 is not necessarily because the surface of the semiconductor substrate 10 below has specific elements, and therefore the surface of the semiconductor substrate 10 is uneven. Next, a contact window opening 23 is formed in the insulating layer 22 to reach the shallow source / drain regions 18 and 20, and the contact window opening 23 is filled with a conductive material to form a contact electrode 24. In the process step of etching the insulating layer 22 to form the contact window opening 23, the insulating layer 22 has different thicknesses due to different heights of the surface structure of the semiconductor substrate 10, so that excessive uranium is etched into the shallow source / drain region 18. The phenomenon happened. In the case where the over-etching is more serious, the heavily doped interface region 20 with ohmic contact will be etched, so that both the contact resistance and the leakage current of the interface will increase. According to the above-mentioned method for forming a shallow interface, there are disadvantages in forming the contact window opening 23, and because the depth of the heavily doped region is shallow, the sheet resistance 値 is high, and the high sheet resistance 降低 will reduce the transistor's Current. 5 This paper is suitable for the China National Standard (CNS) A4 size (210X297mm) (Please read the precautions on the back before filling out this page) "Binding-Good. 4514 2 4073pif.dac / 008 A7 B7 V. Description of the invention (b) Invention 槪 沭 Therefore, the object of the present invention is to provide a metal-oxide-semiconductor field-effect transistor with a better source / drain structure configuration and a method for manufacturing the same. The method can prevent the short channel effect, and suppress the increase of contact resistance and leakage current. The main feature of the present invention is to use the double gap wall technology and form a first heavily doped shallow layer without increasing the lithography process steps. The interface region is immediately adjacent to the channel region and a second heavily doped deep interface region connected to the metal contact plug. According to the above and other objectives of the present invention, a method for fabricating a gold-oxygen half field effect transistor is provided. The method includes A gate structure is formed on the semiconductor substrate. The gate structure includes a gate oxide layer and a gate conductive layer. After that, the gate structure is used as a mask to reduce the first concentration of the first ion. Implanted into the semiconductor substrate to form a lightly doped drain region. The first ionic impurity can be N-type or P-type. The preferred method is to implant the energy at a concentration of lOkev to 201cev at a concentration of 1X1012 to lxl0latoms / cm2 of phosphorus or N-type ions such as arsenic. Then, a first insulating layer and a second insulating layer with a thickness of 20 nm to 100 nm are deposited on the gate structure and the semiconductor substrate, respectively, between the first insulating layer and the second insulating layer. It has different etching selectivity. The material of the first insulating layer is, for example, silicon nitride, and the material of the second insulating layer is, for example, oxide. Then, the second insulating layer is etched to form a first spacer. With a gate structure, The first insulating layer and the first gap wall are used as a curtain, and the second ion doping is performed, and the semiconductor substrate is implanted with a high concentration of ions having different conductivity types from the first ion doping. The polar region is farther from the semiconductor substrate to form the first heavily doped deep interface region. For N-type substrates, 6 (please read the precautions on the back before filling out this page) Chinese National Standard (CNS) A4 (210X297 mm) fs. 4 4073 pii \ doc / 008 B7 V. Description of the invention (It): With a high energy of 25kev to 40kev, implant a P-type impurity with a concentration of about 1X1015 to 5X1015 atoms / cm2, of which The P-type impurity is, for example, boron difluoride. On the other hand, if the semiconductor substrate is a P-type, an N-type impurity, such as arsenic, is implanted. Then, the first spacer is removed, and the first insulating layer is etched back. A second gap wall is formed on the side of the gate structure. A third ion dopant having the same electrical properties as the second ion dopant is implanted into the semiconductor substrate with the gate structure and the second gap wall as a cover. The third ion implantation was performed at a lower energy, lOkev to 20kev, than the 25kev to 40kev of the second ion implantation, between the first implanted layer (Firstlmpurities-Implanted Layer) and the second implanted layer. A second heavily doped shallow interface is formed. In the present invention, the first heavily-doped shallow interface region and the second heavily-doped deep interface region formed by the dual spacer technology have the advantages of suppressing short channel effects, preventing leakage current, and reducing sheet resistance. The metal-oxygen half field-effect transistor disclosed in the present invention includes: a gate structure on a semiconductor substrate having a first conductivity type; and a lightly doped material located in the semiconductor substrate and extending from a side of the gate structure Shallow interface region; a gap wall connected to the sides of the gate structure and extending along the upper surface of the lightly doped interface region; a first heavily doped interface region having a second conductivity type different from the first conductivity type Is located in a semiconductor substrate deeper than the lightly doped shallow interface region, is connected to the lightly doped interface region and forms a first vertical interface, the first vertical interface is connected to the side of the spacer; one has a second conductivity Type second heavily doped interface region is located in a semiconductor substrate deeper than the first heavily doped interface region, is in contact with the first heavily doped interface region, and is located at a certain distance from the side of the gap wall Form 7 A7 (please read the precautions on the back first, and then click this page)

、1T % 本紙張尺A速用中國國家標準（CNS ) A4規格（2I0X297公釐） 4514 2 4073pir.doc/008 A7 B7 五、發明説明（k) 二垂直界面 在上述的金氧半場效電晶體中，第一導電型爲N型， 第二導電型爲P型。第一重摻雜介面區是以lOkev至20kev 的能量，植入濃度爲I X 到5 X 1015 atoms/cm2的砷所 形成，而第二重摻雜介面區則是以25kev至40kev的能量， 植入濃度爲1 X 1_〇[5到5 X 1015 atoms/cm2的砷所形成。 如果第一導電型是P型，則第二導電型爲N型。本 發明中的第一重摻雜介面區是以lOkev至20kev的能量， 植入濃度爲1Χ1〇[5到5XlOi5 atoms/cm2的二氟化硼所形 成；而第二重摻雜淺介面區則是以25kev至40kev的能量， 植入濃度爲1X1015到5X1015 atoms/cm2的二氟化硼所形 成。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知一種具有輕摻雜源極/汲極區的金氧 半場效電晶體的剖面示意圖； 第2A圖至第2G圖繪示爲依照本發明一較佳實施例 的一種具有雙重重摻雜源極/汲極介面的金氧半場效電晶 體的製程流程剖面圖；以及 第3圖繪示爲依照本發明一較佳實施例的一種具有 雙重重摻雜源極/汲極介面的金氧半場效電晶體的剖面示 意圖。 8 (請先閱讀背面之注意事項再填寫本頁) 裝. 丁 、-'fl 本紙張尺度適扣中國國家標準（CNS ) A4規格（210X297公釐） 5] 4、 1T% This paper ruler A is a Chinese national standard (CNS) A4 specification (2I0X297 mm) 4514 2 4073pir.doc / 008 A7 B7 V. Description of the invention (k) Two vertical interface in the above-mentioned metal-oxygen half field effect transistor Among them, the first conductivity type is N-type, and the second conductivity type is P-type. The first heavily doped interface region is formed with an energy of lOkev to 20kev and implanted with arsenic at a concentration of IX to 5 X 1015 atoms / cm2, while the second heavily doped interface region is formed with an energy of 25kev to 40kev. It is formed by arsenic at a concentration of 1 X 1_〇 [5 to 5 X 1015 atoms / cm2. If the first conductivity type is a P-type, the second conductivity type is an N-type. In the present invention, the first heavily doped interface region is formed by implanting boron difluoride with a concentration of 1 × 10 [5 to 5 × 10 × 5 atoms / cm2 at an energy of 10kev to 20kev; and the second heavily doped shallow interface region is It is formed by implanting boron difluoride with an energy of 25kev to 40kev at a concentration of 1X1015 to 5X1015 atoms / cm2. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 A conventional cross-sectional schematic diagram of a gold-oxygen half field-effect transistor with a lightly doped source / drain region is shown. Figures 2A to 2G show a double-doped layer with double doping according to a preferred embodiment of the present invention. Process flow sectional view of a metal-oxygen half field-effect transistor with a hybrid source / drain interface; and FIG. 3 illustrates a gold with dual heavily doped source / drain interface according to a preferred embodiment of the present invention A schematic cross-sectional view of an oxygen half field effect transistor. 8 (Please read the precautions on the back before filling out this page) Packing. Ding, -'fl This paper size is suitable for China National Standard (CNS) A4 specification (210X297 mm) 5] 4

4073pif\d〇c/00S A7 B7 五 '發明説明（（）標記之簡單說明z 10、100 :半導體基底 1 2、1 0 2 :場氧化層 14 ' 104 : P 井 16、10 6 :聞極結構 10a、106a :第一導電層 16b、106b :第二導電層 16c、22、106c、124 :絕緣層 18 ' 108、〗08a :輕摻雜介面區 20 :濃摻雜介面區 23 ' 125 :接觸窗開口 24、126 :接觸電極 110 :第一絕緣層 110a、丨10b :第二間隙壁 112 :第二絕緣層 112a、丨12b :第一間隙壁 U4a :第一光阻圖案 114b :第二光阻圖案 116、116a、120a :第一重摻雜深介面區 、1 18a、]22a :第二重摻雜淺介面區 實施例爲了說明本發明的金氧半場效電晶體，以下將對形 成金氧半場效電晶體的方法做詳細的描述。請參照第2A圖，其繪示一個在表面具有一個閘極結 本紙永尺度適用中國國家標隼（CNS ) A4現格（210X297公鐘:〉 〈請先閣讀背面之注意事項再填寫本页) .装· *ΐτ 45M22 40 73 pH', doc/(J08 A7 B7 射浐部屮戎i.?.準XJ’U消赀合作ii印？^ 五、發明説明（0) 構的半導體基底的剖面示意圖。在包括第2A圖的下列圖 式中，半導體基底具有N型導電型，而在半導體基底具有 P型導電型的例子中，構成源極/汲極之介面區的導電型 也都要跟著做修正。請參照第2A圖，其中，記憶胞陣列 區，NMOS區以及PMOS區等三個元件區周圍都被場氧化 層102所環繞。場氧化層102是以習知的方法，比如是區 域氧化法或是溝渠隔離法所形成。在N型基底100的NMOS 區中形成一個P井丨04。在每一個兀件區上形成一個由第 一導電層106a，第二導電層106b與絕緣層106c所組成的 閘極結構】,06。其中，閘極氧化層（未繪示於圖中）是以習 知的方法沉積於閘極結構106與半導體基底之間。第 一導電層l〇6a的材質通常爲複晶矽，而第二導電層爲了 要與之後覆蓋的金屬層有較好的接觸，其材質以矽化物爲 較佳。在閘極結構106下方有一個區域的基底100則作爲 通道。 以閘極結構1〇6作爲罩幕’對基底植入第一離 子摻質，在閘極結構〗06之一邊形成第一摻植層108，以 形成輕摻雜汲極(Lightly Doped Drain ; LDD)結構。此第一 離子摻質植入步驟可以使用N型或是P型的摻質’但是以 N型摻質，比如爲磷或砷爲較佳，而爲了使輕摻雜區的深 度變淺，第一次離子摻質植入步驟是以1〇kev至20kev的 能量，植入濃度約爲1 X 1〇12到丨X丨〇14 atoms/cm2之摻質 的方式來進行。 以下的製程步驟對本發明是非常關鍵的。請參照第2 本紙張尺度通扣中國國家橾準（CNS > A4規格（210X297公漦） (却先閲讀背面之注意事項再填寫本頁) $ 裝 訂 線 45】422 4073p*r.d〇c/00« A7 B7 五、發明说明（飞） (誚先閲讀背面之注意事項再填艿本頁) 圖’沉積厚度分別爲2〇nm到丨〇0nm的第一和第一絕緣層 110與112，覆蓋於閘極結構106與半導體基底100上。 其中，這兩層絕緣層丨10與Π2分別具有不同的蝕刻選擇 率。第一絕緣層Π0比如爲氮化矽層，而第二絕緣層112 比如爲氧化層。 請參照第2C圖’以第一絕緣層110爲終止層’利用 等向性蝕刻法回蝕刻第二絕緣層Π2，在形成於閘極結構 106之側邊的第一絕緣層110的側邊形成第一間隙壁112a 與 112b 。 請參照第2D圖，在第2C圖中所顯示的結構上形成 第一光阻圖案I 14a，並暴露出NMOS區。以第一間隙壁112a 與第一光阻圖案M4a爲罩幕，進行第二次摻植製程。第 二次摻植步驟是以25kev至40kev的能量植入比第一次摻 植步驟之濃度更大的濃度1X1015到5X1015 atoms/cm2的 N型摻質，比如爲砷來進行。在距離暴露出來的半導體基 底1〇〇表面比第一摻植層108爲遠的位置，形成具有N型 導電型的第二摻植層Π6。 請參照第2E圖，在進行第二次摻植步驟之後，以濕 式蝕刻法移除第-間隙壁112a。之後，回蝕刻第一絕緣層 110,以在閘極結構106的側邊形成第二間隙壁110a。接 著，以第二間隙壁110a與第一光阻圖案114a爲罩幕，對 被第一光阻圖案114a所暴露出來的NMOS區進行第三次 摻植。第三次摻植所使用的摻質與第二次摻植所使用的摻 質具有相同型的導電型。第三次摻植是以丨Okev至20kev 本紙張尺度適用中阐國家標準（CNS) A4規格（210X29?公釐} A7 B7 4073pif.doc/008 五、發明説明（q) 的能量植入濃度爲1 X 1〇15到5X 1015原子/平方公分的N 型摻質，以在第一摻植層〗08與第二摻植層】〗6之間形成 第三接植層，Π8。其中，N型雜質比如爲砷，且摻質的濃 度比第二次摻植的摻質濃度大。 後續的步驟是形成PMOS場效電晶體，其步驟除了 使用P型雜質進行植入之外，都與形成NMOS的步驟相同’ 其中P型的雜質比如爲二氟化硼。 請參照第2F圖，在移除第一光阻圖案114a之後’ 形成一個第二光阻圖案114b覆蓋半導體基底1〇〇 ’並暴露 出PMOS區。以第二光阻圖案114b與第一間隙壁112b爲 罩幕，進行第四次摻植步驟，以大約爲25kev至4〇kev的 能量，將濃度大約爲1 X 1〇15到5 X 1015原子/平方公分的p 型摻質植入，以在比第一摻植層1〇8距離被暴露出的基底 表面更遠的位置形成第四摻植層120。其中，第四次摻植 步驟所使用的P型摻質比如爲二氟化硼。 請參照第2G圖，在進行第四次摻植之後，以濕式蝕 刻法移除第一間隙壁112b。之後，回蝕刻第一絕緣層11〇 ’ 以在閘極結構106的側邊形成第二間隙壁ll〇b。之後，以 第二間隙壁110b與第二光阻圖案U4b爲罩幕，對被第二光 阻層114b所暴露出來的PMOS區進行第五次摻植步驟。 其中第五次摻植步驟所使用之摻質與第四次雜質植入所使 用的摻質具有相同的導電型。第五次摻植是以l〇kev至 20kev的能量植入濃度爲1 X 1015到5 X 1015 atoms/cm2的P 型摻質，以在第一摻植層108與第四摻植層120之間形成 本紙张尺度適州中國國家標準（CNS ) A4規格（2】0父297公釐） (請先閲讀背面之注意事項再填寫本育) .裝.4073pif \ d〇c / 00S A7 B7 Five 'invention description (simple description of () mark) z 10, 100: semiconductor substrate 1 2, 1 0 2: field oxide layer 14' 104: P wells 16, 10 6: Wen pole Structures 10a, 106a: first conductive layers 16b, 106b: second conductive layers 16c, 22, 106c, 124: insulating layer 18 '108, 08a: lightly doped interface region 20: heavily doped interface region 23' 125: Contact window openings 24, 126: contact electrode 110: first insulating layer 110a, 10b: second gap wall 112: second insulating layer 112a, 12b: first gap wall U4a: first photoresist pattern 114b: second Photoresist patterns 116, 116a, 120a: first heavily doped deep interface region, 118a, 22a: second heavily doped shallow interface region Example In order to illustrate the gold-oxygen half field effect transistor of the present invention, the formation of The method of metal-oxide half-field effect transistor is described in detail. Please refer to FIG. 2A, which shows a paper with a gate junction on the surface. The permanent scale is applicable to the Chinese National Standard (CNS) A4 (210X297):> 〈Please read the precautions on the back before filling in this page.】 * 装 τ 45M22 40 73 pH ', doc / (J08 A7 B7 射 浐 部 屮 荣 i .?. Quasi-XJ'U elimination cooperation ii printed? ^ V. Description of the invention (0) cross-sectional view of a semiconductor substrate structure. In the following drawings including Figure 2A, the semiconductor substrate has an N-type conductivity type, and In the case where the semiconductor substrate has a P-type conductivity type, the conductivity type constituting the source / drain interface region must be modified accordingly. Please refer to FIG. 2A, which includes a memory cell array area, an NMOS area, and a PMOS area. Each element region is surrounded by a field oxide layer 102. The field oxide layer 102 is formed by a conventional method, such as a region oxidation method or a trench isolation method. A P-well is formed in the NMOS region of the N-type substrate 100. 04. A gate structure composed of a first conductive layer 106a, a second conductive layer 106b, and an insulating layer 106c is formed on each element area], 06. Among them, the gate oxide layer (not shown in the figure) Middle) is deposited between the gate structure 106 and the semiconductor substrate by a conventional method. The material of the first conductive layer 106a is usually polycrystalline silicon, and the second conductive layer is to be compared with the metal layer to be covered later. For good contact, the material is preferably silicide. The substrate 100 with a region under the gate structure 106 serves as a channel. The gate structure 106 is used as a mask to implant a first ion dopant into the substrate, and a first implanted layer is formed on one side of the gate structure 06. 108 to form a lightly doped drain (LDD) structure. This first ion dopant implantation step may use an N-type or P-type dopant. However, an N-type dopant such as phosphorus or arsenic is preferred. In order to make the depth of the lightly doped region shallow, the first The primary ion dopant implantation step is performed with an energy of 10 kev to 20 kev, and implantation of a dopant at a concentration of about 1 X 1012 to X X 〇14 atoms / cm2. The following process steps are critical to the invention. Please refer to the 2nd China Paper Standard (CNS > A4 size (210X297)) (but please read the precautions on the back before filling this page) $ Gutter 45】 422 4073p * rd〇c / 00 «A7 B7 V. Description of the invention (flying) (诮 Read the precautions on the back before filling this page) Figure 'First and first insulating layers 110 and 112 with a thickness of 20nm to 丨 00nm, respectively, covering On the gate structure 106 and the semiconductor substrate 100. The two insulating layers 10 and Π2 have different etching selectivity. The first insulating layer Π0 is, for example, a silicon nitride layer, and the second insulating layer 112 is, for example, Oxide layer. Please refer to FIG. 2C, “take the first insulating layer 110 as a stop layer”, and etch back the second insulating layer Π2 using an isotropic etching method. The first insulating layer 110 formed on the side of the gate structure 106 First spacers 112a and 112b are formed on the sides. Referring to FIG. 2D, a first photoresist pattern I 14a is formed on the structure shown in FIG. 2C and the NMOS region is exposed. A photoresist pattern M4a is a mask, and the second doping process is performed. The second time The implantation step is performed by implanting an N-type dopant at a concentration of 1X1015 to 5X1015 atoms / cm2, such as arsenic, at an energy of 25kev to 40kev than the concentration of the first doping step. The semiconductor substrate exposed from a distance 1 〇〇The surface is farther from the first implant layer 108 to form a second implant layer having an N-type conductivity. Please refer to FIG. 2E. After the second implant step, the wet etching method is used. The first spacer wall 112a is removed. Then, the first insulating layer 110 is etched back to form a second spacer wall 110a on the side of the gate structure 106. Then, the second spacer wall 110a and the first photoresist pattern 114a are The mask is used for the third doping of the NMOS region exposed by the first photoresist pattern 114a. The dopant used for the third doping has the same type of conductivity as the dopant used for the second doping. The third type of implantation is based on 丨 Okev to 20kev This paper size is applicable to the National Standard (CNS) A4 specification (210X29? Mm) A7 B7 4073pif.doc / 008 V. Energy description of the invention (q) N-type dopants at a concentration of 1 X 1015 to 5X 1015 atoms / cm 2 Planting layer [08 and second doped layer] [6] A third graft layer is formed between Π8. Among them, the N-type impurity is, for example, arsenic, and the concentration of the dopant is higher than that of the second doping. The next step is to form a PMOS field-effect transistor. The steps are the same as those for forming an NMOS except that the P-type impurity is used for implantation. 'The P-type impurity is, for example, boron difluoride. Please refer to Figure 2F, After removing the first photoresist pattern 114a, a second photoresist pattern 114b is formed to cover the semiconductor substrate 100 'and the PMOS region is exposed. Using the second photoresist pattern 114b and the first gap wall 112b as a mask, the fourth implantation step is performed, and the concentration is about 1 X 1015 to 5 X 1015 atoms with an energy of about 25 kev to 40 kev. A p-type dopant is implanted per cm 2 to form a fourth implanted layer 120 at a position farther than the exposed surface of the substrate from the first implanted layer 108. Among them, the P-type dopant used in the fourth doping step is, for example, boron difluoride. Referring to FIG. 2G, after the fourth implantation, the first spacer 112b is removed by wet etching. After that, the first insulating layer 110 ′ is etched back to form a second gap wall 110b on the side of the gate structure 106. After that, using the second spacer 110b and the second photoresist pattern U4b as a mask, a fifth implantation step is performed on the PMOS region exposed by the second photoresist layer 114b. The dopant used in the fifth implantation step has the same conductivity type as that used in the fourth impurity implantation. The fifth implantation was performed by implanting a P-type dopant at a concentration of 1 X 1015 to 5 X 1015 atoms / cm2 at an energy of 10 kev to 20 kev, so that the first implant layer 108 and the fourth implant layer 120 were implanted. The paper size is in accordance with the China National Standard (CNS) A4 specification (2) 0 parent 297 mm (please read the precautions on the back before filling in this education).

*1T (51422 A7 B7 407.1 pif. doc/008 五、發明説明（（ο ) (諳先閲讀背面之注意事項再功寫本頁) 第五摻植層122。其中，P型植質比如爲二氟化硼，且植 入摻質的濃度比第一次雜質植入的雜質濃度大。接著，以 傳統習知的方法移除第二光阻圖案114b。 之後，對各個摻雜層進行回火步驟。回火步驟比如 在700t至80(TC的高溫爐中進行30分鐘，或是以快速高 溫回火製程以900°C至1500°C的高溫進行大約10到30秒。 接著，就分別形成了 PMOS電晶體與NMOS電晶體。 NMOS電晶體的結構包括：一個閘極結構106，位於具有 第一導電型的基底100上；一個輕摻雜淺介面區108a，位 於半導體基底1〇〇之中，從閘極結構106的側邊向外延伸； 一個間隙壁，從閘極結構106的側邊沿著輕摻雜介面 區I08a的表面延伸；一個N型的第二重摻雜淺介面區 118a，位於半導體基底100中，其介面深度比輕摻雜介面 區108a深，與輕摻雜介面區108a相連接並形成第一垂直 界面，此第一垂直界面與間隙壁110a的側邊相連接；一 個具有第二導電型的第一重摻雜深介面區I16a，位於半導 體基底100中，其介面深度比第二重摻雜介面區118a來 的深，與第二重摻雜介面區118a相接，並且在與間隙壁110a 之側邊有一段特定距離的位置形成第二垂直介面。 而在PMOS電晶體結構中，與NMOS電晶體結構不 同的只有源極/汲極介面區122a與120b的導電性。 如第3圖所示，形成一層介電層覆蓋於先前形成之 結構上。在層間介電層124中彤成一個到達源極/汲極介 面區的接觸窗開口 125。在接觸窗開口 125中沉積一層導 本紙張尺度遍別中國國家標準（CNS ) A4規格（210X297公釐）* 1T (51422 A7 B7 407.1 pif. Doc / 008 V. Description of the invention ((ο) (谙 Read the precautions on the back before writing this page)) The fifth implant layer 122. Among them, the P-type plant material is Boron fluoride, and the implanted dopant has a higher concentration than the first implanted impurity. Then, the second photoresist pattern 114b is removed by a conventional method. Then, each doped layer is tempered. Step. The tempering step is performed in a high-temperature furnace at 700t to 80 ° C for 30 minutes, or in a high-temperature tempering process at a high temperature of 900 ° C to 1500 ° C for about 10 to 30 seconds. Then, separate formation is performed. PMOS transistor and NMOS transistor are included. The structure of the NMOS transistor includes: a gate structure 106 on the substrate 100 having the first conductivity type; a lightly doped shallow interface region 108a on the semiconductor substrate 100; Extending outward from the side of the gate structure 106; a gap wall extending from the side of the gate structure 106 along the surface of the lightly doped interface region I08a; an N-type second heavily doped shallow interface region 118a Is located in the semiconductor substrate 100, and its interface depth is deeper than a lightly doped interface 108a deep, connected to the lightly doped interface region 108a and forming a first vertical interface, the first vertical interface is connected to the side of the spacer 110a; a first heavily doped deep interface region I16a having a second conductivity type Is located in the semiconductor substrate 100, the interface depth of which is deeper than that of the second heavily doped interface region 118a, is in contact with the second heavily doped interface region 118a, and is at a certain distance from the side of the spacer 110a A second vertical interface is formed. In the PMOS transistor structure, the only difference from the NMOS transistor structure is the conductivity of the source / drain interface regions 122a and 120b. As shown in FIG. 3, a dielectric layer is formed to cover On the previously formed structure, a contact window opening 125 reaching the source / drain interface region is formed in the interlayer dielectric layer 124. A layer of a guide paper is deposited in the contact window opening 125 throughout the Chinese National Standard (CNS) A4 specifications (210X297 mm)

Claims (1)

ABCD 經濟部中央標隼局員工消費合作社印製 六、申請專利範圍 1. 一種製作金氧半場效電晶體的方法，該方法包括： 形成一閘極結構於具有一第一導電型之一半導體基 底上，該閘極結構係由一閘極氧化層與一導電層所構成； 以該閘極結構爲罩幕層，進行一第一次摻植步驟， 在該半導體基底中形成一第一摻植層； 沉積一第一絕緣層與一第二絕緣層於該閘極結構 上，並覆蓋該半導體基底； 蝕刻該第二絕緣層以形成一第一間隙壁； 以該閘極結構，該第一絕緣層以及該第一間隙壁爲 罩幕，進行一第二次摻植步驟，植入一第二導電型摻植於 該半導體基底中，在距離具有不同導電型之該半導體基底 比該第一摻植層更遠的位置，形成一第二摻植層； 移除該第一間隙壁； 蝕刻該第一絕緣層以形成一第二間隙壁； 以該閘極結構與該第二間隙壁爲罩幕，對該半導體 基底進行具有該第二導電型之一第三次摻植步驟，以在該 第一摻植層與該第二摻植層之間，形成一第三摻植層；以 及 進行回火步驟，以分別於該第一摻植層形成一輕摻 雜淺介面區，於該第二摻植層形成一第一重摻雜深介面 區，以及於第三摻植層形成介於該輕摻雜淺介面區以及該 第一重摻雜深介面區之間之一第二重摻雜淺介面區。 2. 如申請專利範圍第1項所述之製作金氧半場效電晶 體的方法，其中，該第一絕緣層與該第二絕緣層具有不同 (請先閱讀背面之注意事項再填寫本頁) 、vsPrinted by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 6. Application for Patent Scope 1. A method for making a metal-oxide half field effect transistor, the method comprising: forming a gate structure on a semiconductor substrate having a first conductivity type Above, the gate structure is composed of a gate oxide layer and a conductive layer; using the gate structure as a mask layer, a first implantation step is performed to form a first implantation step in the semiconductor substrate; Depositing a first insulating layer and a second insulating layer on the gate structure and covering the semiconductor substrate; etching the second insulating layer to form a first gap wall; using the gate structure, the first The insulating layer and the first gap wall are used as a mask, and a second implantation step is performed, a second conductivity type is implanted in the semiconductor substrate, and the semiconductor substrate having different conductivity types at a distance is smaller than the first conductivity type. A second implanted layer is formed further away from the implanted layer; the first spacer is removed; the first insulating layer is etched to form a second spacer; the gate structure and the second spacer are The curtain, Performing a third implantation step with the second conductivity type on the semiconductor substrate to form a third implantation layer between the first implantation layer and the second implantation layer; and tempering the semiconductor substrate; In the steps, a lightly doped shallow interface region is formed on the first doped layer, a first heavily doped deep interface region is formed on the second doped layer, and a lightly doped interfacial region is formed on the third doped layer. A doped shallow interface region and a second heavily doped shallow interface region between the first heavily doped deep interface region. 2. The method for making a metal-oxide-semiconductor field-effect transistor as described in item 1 of the scope of patent application, wherein the first insulating layer is different from the second insulating layer (please read the precautions on the back before filling this page) Vs 本紙張尺度適用中國國家標準（CMS〉A4現格（210X 297公釐) ABCD ^51422 4 0 7 3 p i f ιΐ 〇 c/fl 0 S 六、申請專利範圍 之蝕刻選擇率。 (請先閲讀背面之注意事項再填寫本頁) 3. 如申請專利範圍第2項所述之製作金氧半場效電晶 體的方法，其中，該第一絕緣層包括一氮化矽層，該第二 絕緣層包括一氧化砂層。 4. 如申請專利範圍第1項所述之製作金氧半場效電晶 體的方法，其中，該第一絕緣層之厚度大約爲20nm至 1 OOnm左右。 5. 如申請專利範圍第1項所述之製作金氧半場效電晶 體的方法，其中，該第二絕緣層之厚度大約爲至 lOOnm左右。 6. 如申請專利範圍第1項所述之製作金氧半場效電晶 體的方法，其中，該第二次摻植步驟所使用之摻質與該第 三次摻植步驟所使用之摻質具有相同之導電型。 7. 如申請專利範圍第1項所述之製作金氧半場效電晶 體的方法，其中，該第一次摻植步驟所使用之摻質包括砷 與磷，而其摻雜濃度範圍包括1X1012至ixl〇M atoms/cm2，其植入能量範圍包括lOkev至2 0kev。 經濟部t央標隼局員工消費合作社印裂 8. 如申請專利範圍第1項所述之製作金氧半場效電晶 體的方法，其中，該第二次摻植步驟所使用之摻質包括砷 與二氟化硼，而其摻雜濃度範圍包括1X1015至5X1015 atoms/cm2，其植入能量範圍包括25kev至401cev。 9. 如申請專利範圍第1項所述之製作金氧半場效電晶 體的方法，其中，該第三次摻植步驟所使用之摻質包括砷 與二氟化硼，而其摻雜濃度範圍包括1 X 1〇15至5 X 10i5 本紙張尺度適用中國國家操準（CNS ) A4規格（210X297公釐） A8 B8 C8 D8 4073pii'.d(ic/0(KS 六、申請專利範圍 atoms/cm2，其植入能量範圍包括lOkev至20kev。 10. 如申請專利範圍第1項所述之製作金氧半場效電 晶體的方法其中，該回火步驟包括在溫度大約爲700°c 至800t：的爐中進行約30分鐘。 11. 如申請專利範圍第I項所述之製作金氧半場效電 晶體的方法，其中，該回火步驟包括以大約900°C至1500 °C進行大約10秒至30秒之快速回火製程。 12. 如申請專利範圍第1項所述之製作金氧半場效電 晶體的方法，其中，該方法更包括於該回火步驟之後形成 一層間介電層覆蓋於該半導體基底，形成一接觸窗開口於 該層間藉電層中，並到達該濃摻雜深介面區，以及以一導 電層塡滿該接觸窗開口以形成一接觸電極。 13. —種製作具有PMOS區與NMOS區之CMOS電晶 體的方法，該方法包括= 形成一第一閘極結構於該NMOS區上，並形成一第 二閘極結構於該PMOS區上，其中，每一個該閘極結構包 括一閘極氧化層與一閘極導電層； 進行第一次N型摻雜，以各個該閘極結構爲罩幕， 形成一第一 N型摻植層於該半導體基底中； 沉積一第·…絕緣層與一第二絕緣層於該閘極結構 上，並覆蓋該半導體基底； 蝕刻該第二絕緣層以形成一第一間隙壁於該Ν Μ O S 區中； 利用一光阻圖案以暴露出該NMOS區； 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210Χ297公釐） . i i 裝— 訂 i I * I 1 H ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 A8 B8 CS D8 4073pil'.dnc/0iJ« 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 進行一第二次N型摻植步驟，將一 N型摻質植入該 半導體基底，以該閘極結構，該第一絕緣層以及該第一間 隙壁爲罩幕.，在比該第一摻植區距離具有不同電性之該半 導體基底更遠的位置，形成一第二N型摻植層； 移除該NMOS區中之該第一間隙壁； 飩刻該第一絕緣層以形成一第二間隙壁於該NMOS 區中； 以該閘極結構與該第二間隙壁爲罩幕，對該半導體 基底進行具有該第二導電性之一第三次N型摻植步驟，以 在該第一摻雜層與該第二摻雜層之間，形成一第三N型摻 雜層；以及 進行回火步驟，以分別於該第一摻植層形成一 N型 輕摻雜淺介面區，於該第二摻植層形成一 N型第一重摻雜 深介面區，以及於第三摻植層形成介於該輕摻雜淺介面區 以及該第一重摻雜深介面區之間之一 N型第二重摻雜淺介 面區於該NMOS區中。 14. 如申請專利範圍第13項所述之製作具有PMOS 區與NMOS區之CMOS電晶體的方法，其中，該第一絕 經濟部中央標準局員工消費合作社印製 緣層包括一氮化矽層。 15. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該第二絕緣 層包括一氧化砂層。 16. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該第一絕緣 本紙張尺度適用申國國家標準（CNS ) A4規格（210Χ；297公釐） ^ 5 /4以 •ΠΤ7 .^pir.cloc/OOS A8 B8 C8 D8 經濟部中央標率局員工消費合作社印裝 六、申請專利範圍 層之厚度大約爲20nm至lOOnm左右。 17. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該第二絕緣 層之厚度大約爲20nm至lOOnm左右。 18. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該第一次摻 植步驟所使用之摻質包括砷與磷，而其摻雜濃度範圍包括 1 X 1〇12至1 X丨〇14 atoms/cm2，其植入能量範圍包括lOkev 至 20Icev。 19. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該第二次摻 植步驟所使用之摻質包括砷，而其摻雜濃度範圍包括IX 1〇1:>至5 X 1013 atoms/cm2，其植入能量範圍包括25kev至 40kev 。 20. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該第三次摻 植步驟所使用之摻質包括砷，而其摻.雜濃度範圍包括IX 10ls至5 X l〇h atoms/cm2，其植入能量範圍包括lOkev至 201cev。 21. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該回火步驟 包括在溫度大約爲700°C至800°C的爐中進行約3.0分鐘。 22. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該回火步驟 (請先閲讀背面之注意事項再填寫本頁) .裝. 、tT il_ 本紙張尺度逋用中國國家操準（CNS ) A4現格（210X297公釐） 4 5 / 40 73 pi Γ. d〇c/00S A8 B8 C8 D8 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 包括以大約90〇t至1500°C進行大約10秒至30秒之快速 回火製程。 23. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該方法更包 括於該回火步驟之後形成一層間介電層覆蓋於該半導體基 底，形成一接觸窗開口於該層間藉電層中，並到達該濃摻 雜深介面區，以及以一導電層塡滿該接觸窗開口以形成一 接觸電極。 24. 如申請專利範圍第13項所述之製作具有PMOS區 與NMOS區之CMOS電晶體的方法，其中，該方法更包 括於該第三次摻植步驟之後，進行下列步驟： 移除該光阻圖案； | 以一第二光阻圖案暴露出該PM0S區； 以該閘極結構，該第一絕緣層以及該第一間隙壁爲 罩幕，植入一第一 P型摻質於該PM0S區中，在與該半導 體基底之距離大於該第一 N型摻植層與該半導體基底之距 離的位置，形成一第一 P型摻植層； 於該PM0S區中移除該第一間隙壁； 蝕刻該第一絕緣層以於該PM〇s區中形成一第二間 隙壁： 以該閘極結構以及該第一間隙壁爲罩幕，植入一第 二P型摻質於該PM0S區中，在該第一N型摻植層與該 .第一 p型摻植層之間形成一第二p型摻植層； 對該第一與該第二P型摻植層進行一回火步驟，於 20 -------Γ--κ 裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度逋用中國國家操準（CNS ) Μ規格（210X297公釐） Αδ B8 C8 D8 407；>pi1-.do>:/00S >申請專利範圍 法包括以大約l〇kev至20kev的能量，植入濃度大約爲1 X 1 0!5 至 5 X 1 atoms/cm2 的砷。 34. 如申請專利範圍第32項所述之金氧半場效電晶 體，其中，形成具有N導電型之該第二重摻雜介面區的方 法包括以大約25kev至40kev的能量，植入濃度大約爲1 X1013 至 5X10I：) atoms/cm2 的砷。 35. 如申請專利範圍第29項所述之金氧半場效電晶 體，其中，該第一導電型包括N導電型，且該第二導電型 包括P導電型。 36. 如申請專利範圍第35項所述之金氧半場效電晶 體，其中，形成具有P導電型之該第一重摻雜介面區的方 法包括以大約l〇kev至20kev的能量，植入濃度大約爲1 X 1013 至 5 X 1 0 1:1 atoms/cm2 的二氟化砸。 37. 如申請專利範圍第35項所述之金氧半場效電晶 體，其中1形成具有P導電型之該第二重摻雜介面區的方 法包括以大約25kev至40kev的能量，植入濃度大約爲1 父10|:>至5\10|;'31;〇1113/(：1112的二氨化棚。 (請先閱讀背面之注意事項再填寫本頁) .裝· 訂 經濟部中央標隼局員工消費合作社印製 23 本紙浪尺度適用中國國家標準（CMS ) A4規格（210X297公釐）This paper size applies the Chinese national standard (CMS> A4 now (210X 297 mm) ABCD ^ 51422 4 0 7 3 pif ιΐ 〇c / fl 0 S 6. Etching selection rate for patent application scope. (Please read the back page first Please fill in this page again for the matters needing attention) 3. The method for manufacturing a metal-oxide-semiconductor field-effect transistor as described in item 2 of the patent application scope, wherein the first insulating layer includes a silicon nitride layer and the second insulating layer includes a Oxidized sand layer. 4. The method for making a gold-oxygen half field effect transistor as described in item 1 of the scope of patent application, wherein the thickness of the first insulating layer is about 20nm to 100nm. 5. As the first scope of patent application The method for making a metal-oxide-semiconductor half-field-effect transistor according to item 1, wherein the thickness of the second insulating layer is about 100 nm. 6. The method for making a metal-oxide-semiconductor half-field effect transistor as described in item 1 of the scope of patent application. Among them, the dopant used in the second implantation step has the same conductivity type as the dopant used in the third implantation step. 7. Making a metal-oxygen half field as described in item 1 of the scope of patent application Effect transistor method, which The dopants used in the first doping step include arsenic and phosphorus, and the doping concentration range includes 1X1012 to ixl0M atoms / cm2, and the implantation energy range includes 10kev to 20kev. Ministry of Economic Affairs The employees of the Hong Kong Bureau of the Consumer Cooperative Association 8. The method of making a metal-oxygen half field effect transistor as described in item 1 of the scope of patent application, wherein the dopants used in the second doping step include arsenic and boron difluoride And its doping concentration range includes 1X1015 to 5X1015 atoms / cm2, and its implantation energy range includes 25kev to 401cev. 9. The method for making a gold-oxygen half field effect transistor as described in item 1 of the patent application range, wherein the The dopants used in the third doping step include arsenic and boron difluoride, and the doping concentration ranges from 1 X 1015 to 5 X 10i5. This paper is applicable to China National Standards (CNS) A4 (210X297). Mm) A8 B8 C8 D8 4073pii'.d (ic / 0 (KS VI. Patent application range atoms / cm2, the implantation energy range includes 10kev to 20kev. 10. The production gold as described in item 1 of the patent application range Oxygen half field effect transistor method, wherein the tempering step Including in a furnace at a temperature of about 700 ° C to 800t: for about 30 minutes. 11. The method of making a gold-oxygen half field effect transistor as described in the first patent application scope, wherein the tempering step includes 900 ° C to 1500 ° C for a rapid tempering process for about 10 seconds to 30 seconds. 12. The method for making a gold-oxygen half field effect transistor as described in item 1 of the patent application scope, wherein the method is further included in the method After the tempering step, an interlayer dielectric layer is formed to cover the semiconductor substrate, a contact window opening is formed in the interlayer borrow layer, and the heavily doped deep interface region is reached, and the contact window opening is filled with a conductive layer. To form a contact electrode. 13. —A method for manufacturing a CMOS transistor having a PMOS region and an NMOS region, the method includes: forming a first gate structure on the NMOS region, and forming a second gate structure on the PMOS region, wherein Each gate structure includes a gate oxide layer and a gate conductive layer; first N-type doping is performed, and each gate structure is used as a mask to form a first N-type doped layer on the gate. A semiconductor substrate; a first ... insulating layer and a second insulating layer are deposited on the gate structure and cover the semiconductor substrate; the second insulating layer is etched to form a first gap wall in the NM OS region ; Use a photoresist pattern to expose the NMOS area; This paper size uses the Chinese National Standard (CNS) A4 specification (210 × 297 mm). Ii Installation — Order i I * I 1 H ^ (Please read the note on the back first Please fill out this page again) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives A8 B8 CS D8 4073pil'.dnc / 0iJ «6. Scope of patent application (please read the precautions on the back before filling this page) N-type doping steps, one N-type dopant Into the semiconductor substrate, with the gate structure, the first insulating layer and the first gap wall as a cover, formed at a position farther than the semiconductor substrate with different electrical properties from the first implanted region; A second N-type implanted layer; removing the first spacer in the NMOS region; engraving the first insulating layer to form a second spacer in the NMOS region; using the gate structure and the first spacer The two gap walls are masks, and the semiconductor substrate is subjected to a third N-type doping step with the second conductivity to form a first doped layer between the first doped layer and the second doped layer. Three N-type doped layers; and a tempering step to form an N-type lightly doped shallow interface region on the first doped layer, and an N-type first heavily doped layer on the second doped layer respectively An interface region, and an N-type second heavily doped shallow interface region formed in the third doped layer between the lightly doped shallow interface region and the first heavily doped deep interface region in the NMOS region. 14. The method for fabricating a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the printed marginal layer of the Consumer Cooperative of the Central Standards Bureau of the First Ministry of Economic Affairs includes a silicon nitride layer . 15. The method for manufacturing a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the second insulating layer includes a sand oxide layer. 16. The method for manufacturing a CMOS transistor with a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the first insulating paper size is applicable to the national standard (CNS) A4 specification (210 ×; 297) (Centimeters) ^ 5/4 to • ΠΤ7. ^ Pir.cloc / OOS A8 B8 C8 D8 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. The thickness of the patent application layer is about 20nm to 100nm. 17. The method for fabricating a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the thickness of the second insulating layer is about 20 nm to 100 nm. 18. The method for manufacturing a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the dopants used in the first doping step include arsenic and phosphorus, and the doping concentration thereof The range includes 1 X 1012 to 1 X 1414 atoms / cm2, and its implantation energy range includes 10kev to 20Icev. 19. The method for manufacturing a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the dopant used in the second doping step includes arsenic, and the doping concentration range thereof includes IX 1〇1: > to 5 X 1013 atoms / cm2, and its implantation energy range includes 25kev to 40kev. 20. The method for manufacturing a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the dopant used in the third doping step includes arsenic, and its doping concentration range Including IX 10ls to 5 X l0h atoms / cm2, its implantation energy range includes 10kev to 201cev. 21. The method for fabricating a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of patent application, wherein the tempering step includes performing a temperature of about 3.0 in a furnace having a temperature of about 700 ° C to 800 ° C. minute. 22. The method for manufacturing a CMOS transistor with a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the tempering step (please read the precautions on the back before filling this page). Installation, tT il_ This paper size is in accordance with China National Standards (CNS) A4 (210X297 mm) 4 5/40 73 pi Γ. doc / 00S A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs The scope of patent application includes a rapid tempering process at about 90 to 1500 ° C for about 10 to 30 seconds. 23. The method for fabricating a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the method further comprises forming an interlayer dielectric layer to cover the semiconductor substrate after the tempering step, A contact window opening is formed in the inter-layer borrowing layer and reaches the heavily doped deep interface region, and the contact window opening is filled with a conductive layer to form a contact electrode. 24. The method for manufacturing a CMOS transistor having a PMOS region and an NMOS region as described in item 13 of the scope of the patent application, wherein the method further includes the third step after the third implantation step, and the following steps are performed: removing the light A resist pattern; | exposing the PM0S region with a second photoresist pattern; using the gate structure, the first insulating layer and the first spacer as a mask, implanting a first P-type dopant into the PM0S In the region, a first P-type implanted layer is formed at a position where the distance from the semiconductor substrate is greater than the distance between the first N-type implanted layer and the semiconductor substrate; and the first spacer is removed in the PMOS region. ; Etching the first insulating layer to form a second gap wall in the PM0s region: using the gate structure and the first gap wall as a mask, implanting a second P-type dopant in the PMOS region A second p-type planted layer is formed between the first N-type planted layer and the .first p-type planted layer; and tempering the first and the second P-type planted layer Steps, installed at 20 ------- Γ--κ-(Please read the precautions on the back before filling out this page) National Standards (CNS) M specifications (210X297 mm) Αδ B8 C8 D8 407; > pi1-.do >: / 00S > The patent application method includes an implantation concentration of approximately 10kev to 20kev, with an implantation concentration of approximately Arsenic from 1 X 1 0! 5 to 5 X 1 atoms / cm2. 34. The gold-oxygen half field-effect transistor as described in item 32 of the scope of patent application, wherein the method of forming the second heavily doped interface region having the N conductivity type includes implanting a concentration of approximately 25kev to 40kev at a concentration of approximately For 1 X1013 to 5X10I :) atoms / cm2 of arsenic. 35. The metal-oxygen half field effect transistor according to item 29 of the scope of the patent application, wherein the first conductivity type includes an N conductivity type and the second conductivity type includes a P conductivity type. 36. The gold-oxygen half field-effect transistor as described in claim 35, wherein the method of forming the first heavily doped interface region having a P conductivity type includes implanting at an energy of about 10 kev to 20 kev Difluoride at a concentration of approximately 1 X 1013 to 5 X 1 0 1: 1 atoms / cm2. 37. The gold-oxygen half field-effect transistor as described in item 35 of the scope of patent application, wherein 1 the method of forming the second heavily doped interface region having a P conductivity type includes implanting a concentration of about 25kev to 40kev at a concentration of about It is 1 parent 10 |: > to 5 \ 10 |; '31; 〇1113 / (: 1112 diammonization shed. (Please read the precautions on the back before filling this page). Assemble and order the central standard of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 23 This paper is compliant with China National Standard (CMS) A4 (210X297 mm)
TW087118740A 1998-03-26 1998-11-11 A metal-oxide semiconductor field effect transistor and a method for fabricating thereof TW451422B (en)

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