經濟部中央標準扃負工消费合作社印製 A7 B7 五、發明説明（） 發明镅媸： 本發明與一種製作電晶體元件之方法有關，特别是 一種製作具有不同臨界電壓之N型金屬氧化物半導體場 效電晶體用以作爲唯讀記憶體元件之方法。 發明背景： 唯讀記憶體（ROM)結構已經成功的被應用於非揮發 性（nonvolatile)半導體記憶元件。大部分的唯讀記憶體之 設計與製程通常都能以三種要件描述之。首先，埋入之位 疋線被置於石夕基板内，此位元線通常爲重摻雜區域，並與 基板（導電態相反❶其次，字元線’通常由複晶矽所構成， 位於氧化層之上，並與埋入位元線相互垂直。最後，一特 殊通道區域’由位元線與字元線相交之區域所構成，相較 於未收到程式處理（programmed treatment)之相交區域， 具有電性上選擇性不同之程式反應。此—程式區 (programmable cell)，於正常情況其製作之順序可以先於 或晚於複Ba *5夕字元線之製作。此一程式區（programmable cell)可以利用不同技術手段完成，大部分唯讀記憶體 (ROM)之設計與製程’例如（i )埋入位元線之結構可以參 考 “G. Hong，U.S. patent. Νο·:5,635,41 5(1 997)，’，（2)利用 離子植入形成具有不同臨界電壓之方法，則可以參考 “Y.J.Wann，et al.，U.S. patent. No.:5,5 14,61 0(1996)”等參 考資料。以第二件參考資料而言，其形成具有不同臨界電 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) ---! I.^-----------ί ^--- -n - - n In - I n - I - I In - - - I . A7 B7 五、發明説明（） 壓之過程t需要多一道罩幕 發明目的及概述： 本發明之目的爲提供-種簡單之方珐用以製作具 有不同臨界電壓之N型金屬氧化物半導禮場效電晶體作 爲唯讀記憶體（ROM)元件且無需額外之罩幕。 此方法包括’形成複數個場氧化區域於 上’接著形成一 N丼與P井於半導體基板之 及形成一 P井於基板上之程式區。形成一光 之P井上，接者，以上述光阻層作爲罩幕， 植入於元件區之N井中形成抗穿透 punchthrough stopping)，及於程式區之 p 井 通道（buried channel)。於去除光阻之後，一 體被製作於元件區上’ 一 NMOS電晶體被製 上。然後CMOS電晶體以標準之製程完成金 連線之製作。本發明所提供之優點爲（丨）具不 之N型金屬氧化物半導體場效電晶想可以很 出來而無須額外之罩幕，且（2)所提出之製程 造。 半導體基板 元件區上， 阻於元件區 施以鱗離子 阻播（anti-中形成埋入 CMOS電晶 作於程式區 屬接點舆内 同臨界電壓 容易被製作 參數易於製 請 先 閲 讀 背 A 之 注 項 再 填 繁装 頁 訂. 經濟部中央標準局男工消费合作社印製 圈式簡箪説明： 第一圖爲本發明之形成製作PMOSFET用之N丼與製作 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） A7 B7 五、發明説明（） NMOSFET用之P井之截面圖； 第二囷爲本發明之施以磷離子植入於PMOSFET作 透阻搶（anti-punchthrough)以及於 NMOSFET 作爲 道（buried channel)之截面圖； 第三囷爲本發明以標準製程形成CMOS電晶體 圈； 第四圖爲本發明於CMOS電晶體上形成金屬接點 線之截面圖； 第五 a圖爲本發明中有摻雜磷離子之〇.5 μβ1 NMOSFET之Id-Vg之特性曲線圖；及 第五b圖爲本發明中本發明中無掺雜嶙離子之〇 掺雜NMOSFET之Id-Vg之特性曲線圖。 爲抗穿 埋入通 之截面 與内連 輕摻雜 5 Um ^ C請先閎讀背面之注意Ϋ項再填寫本頁) 、可.Printed by A7 B7, Central Standard of the Ministry of Economic Affairs and Consumer Cooperatives V. Description of the Invention () Invention 镅 媸: The present invention relates to a method for making transistor elements, especially an N-type metal oxide semiconductor with different threshold voltages. Field-effect transistors are used as a method for read-only memory elements. BACKGROUND OF THE INVENTION: Read-only memory (ROM) structures have been successfully applied to nonvolatile semiconductor memory elements. Most read-only memory designs and processes can usually be described by three requirements. First, the buried bit line is placed in the Shixi substrate. This bit line is usually a heavily doped region and is opposite to the substrate (conducting state. Second, the word line is usually composed of polycrystalline silicon. Above the oxide layer and perpendicular to the buried bit line. Finally, a special channel area 'is composed of the area where the bit line and the word line intersect, compared to the intersection where no programmed treatment has been received. The area has a program response that is different in electrical selectivity. This—programmable cells (normally) can be produced in order before or after the production of complex Ba * 5x character lines. This program area (Programmable cells) can be accomplished using different technical means. Most of the ROM-only design and manufacturing processes, such as (i) the structure of embedded bit lines, can be referred to "G. Hong, US patent. No .: 5,635 , 41 5 (1 997), ', (2) For the method of forming different threshold voltages by ion implantation, please refer to "YJ Wann, et al., US patent. No .: 5,5 14,61 0 ( 1996) "and so on. For the second reference Its formation has different critical electrical paper sizes, using Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling this page) ---! I. ^ ------ ----- ί ^ --- -n--n In-I n-I-I In---I. A7 B7 V. Description of the invention () The process of pressing requires an additional screen. Purpose and summary of the invention The purpose of the present invention is to provide a simple square enamel for making N-type metal oxide semiconducting field-effect transistors with different threshold voltages as read-only memory (ROM) elements without the need for an additional cover. The method includes 'forming a plurality of field oxidation regions on top', and then forming a N 丼 and P wells on a semiconductor substrate and forming a pattern region of the P wells on the substrate. A light P well is formed, and then, the above photoresist is used. The layer is used as a mask, which is implanted in the N-well of the device area to form punchthrough stopping, and a p-well channel in the program area. After removing the photoresist, it is fabricated on the device area. The transistor is fabricated. Then the CMOS transistor completes the fabrication of the gold connection using a standard process. The advantages provided by the present invention are: (丨) the N-type metal oxide semiconductor field effect transistor can be easily realized without the need for an additional screen, and (2) the proposed process is made on the semiconductor substrate element area. In the element area, the scale ion blocking is applied (anti-formed embedded CMOS transistor is formed in the program area and the contact voltage is the same as the threshold voltage. It is easy to be made. The parameter is easy to make. Please read the note on A and fill in the complication. Binding. Printed circled description of the male workers' consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs: The first picture shows the formation of N 丼 for PMOSFET and the paper size applicable to the Chinese National Standard (CNS) A4 specification ( 210x297 mm) A7 B7 V. Description of the invention () Sectional view of P-well for NMOSFET; The second one is the application of phosphorus ions implanted in PMOSFET for anti-punchthrough and NMOSFET as the channel (Buried channel) cross-section view; the third figure is a cross-sectional view of the present invention forming a CMOS transistor circle using a standard process; the fourth figure is a cross-sectional view of the present invention forming a metal contact line on the CMOS transistor; the fifth a is The characteristic curve of the Id-Vg of the 0.5 μβ1 NMOSFET with doped phosphorus ions in the invention; and the fifth b figure is the characteristic of the Id-Vg of the 0-doped NMOSFET with no doped europium ions in the present invention in the present invention Graph. For resistance to cross-sections and interconnections, lightly doped 5 Um ^ C (please read the note on the back before filling out this page), yes.
經濟部中央標準扃貝工消费合作社印簟 4 本紙張尺度適用中國圃家標準（CNS ) A4規格（210X297公釐）Central Standard of the Ministry of Economic Affairs and the Seal of the Cooper's Consumer Cooperatives 4 This paper size applies to the Chinese Garden Standard (CNS) A4 (210X297 mm)
發明詳知説明： (請先閲讀背面之注意事項再填寫本頁j 本發明所要揭示的爲一種簡單之方法用以製作具 有不同臨界電壓之N型金屬氧化物半導體場效電晶體作 爲唯讀記憶體（ROM)元件且無需額外之罩幕。 參考第一圖，在一較佳實施例中，一具有<1〇〇>結 晶方向之單結晶矽基板2被提供，並於其上形成複數個厚 場氧化區域（FOX)4作爲元件間隔離用。舉例説，場氧化 區域（FOX)4可利用微影與蝕刻步驟蝕刻氧化矽_氮化矽 組合層而成。於濕触刻去除光阻之後，於氧氣環境下施以 熱氧化製程用以成長厚度約爲3000至8000埃之場氧化 區域（FOX) 4。上述場氧化區域亦可代之爲習知的淺溝渠 隔離區。 經濟部中央標準局貝工消費合作社印製 於隔離區域製作完成之後，利用離子植入方式形成 N井6用來製作PMOSFET元件，P井8a、8b分别用以製 作NMOSFET元件與NMOS胞於基板2上。以較佳實施例 而言，N井係用磷離子植入，劑量範園約爲5><10"ions/cin2 至lxl014ions/cm2，植入能量约爲80至3000 KeV。P井 係用硼離子植入，劑量範圍約爲SxIOnions/cm2至 lxl014ions/cm2，植入能量約爲50至3000 KeV。矽基板2 用以製作元件（週邊電路）之區域稱爲元件區，用以製作唯 讀記憶體單元（ROM cell)之區域稱爲可程式單元 (programmable cell)區域。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局MB；工消費合作社印聚 A7 --—_ —__B7_ 五、發明説明（) ^ 接著’參考第二囷，施一嶙離子植入於N井6作爲 作爲抗穿透阻標（anti_punchth rough stopping)，及於程大 區之P井中形成一低臨界電壓之NMOSFET作爲唯讀々己^ 體（ROM)。此一磷離子植入於元件區之n井6中形成抗^ 透阻擔（anti-punchthrough stopping)7，及於程式區之 井8b中形成埋入通道（buried channel)9，用以製作 NMOSFET之P井8a則被一第一光阻1〇所覆蓋作爲離子 植入罩幕。以較佳實施例而言，此—_難子植入，劑量範 圍約爲l〇12i〇ns/cm2至l〇14i〇ns/cm2，植入能量约爲π 至 200 KeV 參考第三圖，互補型金氧半場效電晶體 (CM0SFET) ’係以標準製程製作，大致簡述如下： 首先’我們製作閘極於元件區之P井8a與n井6上，以 及可程式單元區域（pr〇gramniable cell region)之p井“ 上。閘極包含以下元件，即閘極氧化層丨2、複晶矽閘極、 與側間隙壁1 6 ^於製作完閘極後，一第二光阻形成於N 井6上’並覆蓋住位於>!井6上之閘極，接著，施以一 η 型離子（例如砷、磷等）植入，劑量範圍约爲2χ丨〇I4i〇ns/cm2 至5xl016i〇ns/cm2，植入能量约爲5〇至12〇〖以分别形 成源極與汲極區域18於元件區之p井83中與可程式區之 P井8b中，以第二光阻爲離子植入罩幕。因此，我們已 裳作一 NMOSFET於元件區上，與一具有埋入通道9之 NMOSFET於可程式區域上。随後，移除第'二光阻，然後 f請先閲讀背面之注意事項再填寫本頁}Detailed description of the invention: (Please read the notes on the back before filling out this page. J The present invention is a simple method for making N-type metal oxide semiconductor field effect transistors with different threshold voltages as read-only memory ROM device without additional mask. Referring to the first figure, in a preferred embodiment, a single crystalline silicon substrate 2 having a < 100 > crystal orientation is provided and formed thereon. A plurality of thick field oxide regions (FOX) 4 are used for isolation between devices. For example, the field oxide regions (FOX) 4 can be formed by etching a silicon oxide-silicon nitride combination layer using lithography and etching steps. Removed by wet contact etching After photoresist, a thermal oxidation process is applied in an oxygen environment to grow field oxide regions (FOX) with a thickness of about 3000 to 8000 angstroms. 4. The above field oxidation regions can also be replaced by conventional shallow trench isolation areas. Printed in the isolation area by the Central Bureau of Standardization of the People ’s Republic of China. After the fabrication is completed, the N well 6 is formed by ion implantation to make PMOSFET elements, and the P wells 8a and 8b are used to make NMOSFET elements and NMOS cells on the substrate 2 In a preferred embodiment, the N well system is implanted with phosphorus ions, the dose range is about 5 < 10 " ions / cin2 to lxl014ions / cm2, and the implantation energy is about 80 to 3000 KeV. The P well system With boron ion implantation, the dose range is about SxIOnions / cm2 to lxl014ions / cm2, and the implantation energy is about 50 to 3000 KeV. The area where the silicon substrate 2 is used to make components (peripheral circuits) is called the component area, which is used to make only The area of the ROM cell is called the programmable cell area. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) MB of the Central Standards Bureau of the Ministry of Economic Affairs; A7 ---_ —__ B7_ V. Description of the invention () ^ Then, referring to the second example, Shi Yi was implanted in N well 6 as an anti-punchth rough stopping, and in Cheng Cheng District A low threshold voltage NMOSFET is formed in the P-well as a read-only silicon (ROM). This phosphorus ion is implanted in the n-well 6 in the element region to form an anti-punchthrough stopping 7 and A buried channel is formed in the well 8b of the program area. ) 9, the P-well 8a used to make the NMOSFET is covered by a first photoresistor 10 as an ion implantation mask. In a preferred embodiment, this -_ difficult child implantation, the dose range is about l 〇12i〇ns / cm2 to 1014i〇ns / cm2, the implantation energy is about π to 200 KeV Refer to the third figure, the complementary metal-oxide-semiconductor field-effect transistor (CM0SFET) is made by a standard process, and it is briefly described. It is as follows: First, we make gates P on wells 8a and 6 in the element region, and p wells on the programmable cell region. The gate includes the following elements, namely the gate oxide layer 2, the polycrystalline silicon gate, and the side spacer 1 6 ^ After the gate is completed, a second photoresist is formed on the N well 6 and covers the > The gate electrode on well 6 was then implanted with an n-type ion (such as arsenic, phosphorus, etc.) for implantation in a dose range of about 2 × 丨 I4i〇ns / cm2 to 5x1016i〇ns / cm2, and implanted energy Approximately 50 to 120. The source and drain regions 18 are respectively formed in the p-well 83 in the element region and the P-well 8b in the programmable region, and the second photoresist is used as an ion implantation mask. Therefore, we have made an NMOSFET on the device area and an NMOSFET with a buried channel 9 on the programmable area. Then, remove the second photoresist, then f Please read the precautions on the back before filling in this page}
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In m m · 本紙張尺度㈣tSSI家鮮(CNS)A4«^( 210X297^ )' A7 B7 經濟部中央標準局貝工消费合作社印製 五、發明説明（ 覆蓋-第三光阻於元件區上之NM0SFET，與可程式區域 上具有埋入通道NM0SFET上。施以—p型離子（例 如BF2等）植入’劑量範圍約爲2χΐ〇ΐ4“至 5x10 1〇ns/cm2,植入能量約爲〇 5至8〇KeV形成源極與 没極區域20於元件區之N井6中。然後去除第三光阻。 參考第四囷，以化學氣相沈積方式於全區域上沈積 一厚氧化層22。以較佳實施例而言，此—厚氧化層可以 是一二氧化矽層、一碉磷矽玻璃層、或是磷矽玻璃層。利 用標準之接觸窗、介層窗製程與金屬栓塞製程，於每一電 晶體之源極與汲極上形成金屬接觸24，並於每一電晶體 之閘極上形成内連線。 參考第五a圖，於圖中顯示出唯讀記憶體單元（R〇M cell)之臨界電壓。曲線51表示NMOSFET唯讀記憶體單 元（ROM cell)其基板偏壓Vsub = 0伏特，臨界電壓Vth = 0.56 伏特。曲線521表示NMOSFET唯讀記憶體單元（ROM cell) 其基板偏壓Vsub = -2伏特，臨界電壓Vth = 〇.84伏特。而週 邊電路中NMOSFET之臨界電壓則如第五b圖所示，曲線 511表示週邊電路中NMOSFET其基板偏壓Vsub = 0伏特， 臨界電壓Vth = 〇.73伏特。曲線521週邊電路中NMOSFET 其基板偏壓Vsub = -2伏特，臨界電壓Vth=1.30伏特》In mm · Paper size ㈣tSSI Home Fresh (CNS) A4 «^ (210X297 ^) 'A7 B7 Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs , And the programmable area has an embedded channel NM0SFET. Application of -p-type ions (such as BF2, etc.) is implanted in a dose range of about 2xΐ〇ΐ4 "to 5x10 10ns / cm2, and the implantation energy is about 05 To 80KeV, the source and non-electrode regions 20 are formed in the N-well 6 of the element region. Then, the third photoresist is removed. Referring to the fourth step, a thick oxide layer 22 is deposited on the entire region by chemical vapor deposition. In a preferred embodiment, this—the thick oxide layer may be a silicon dioxide layer, a phosphosilicate glass layer, or a phosphosilicate glass layer. Using standard contact windows, interlayer window processes, and metal plug processes, Metal contacts 24 are formed on the source and drain of each transistor, and interconnects are formed on the gate of each transistor. Referring to Figure 5a, a read-only memory cell (ROM) is shown in the figure. cell). The curve 51 indicates that the NMOSFET read-only memory cell (ROM cell) The substrate bias Vsub = 0 volts and the threshold voltage Vth = 0.56 volts. Curve 521 indicates that the NMOSFET read-only memory cell (ROM cell) has a substrate bias Vsub = -2 volts and a threshold voltage Vth = 0.84 volts. And the peripheral circuit The threshold voltage of the middle NMOSFET is shown in Figure 5b. Curve 511 represents the substrate bias voltage Vsub of the NMOSFET in the peripheral circuit = 0 volts and the threshold voltage Vth = 0.73 volt. Curve 521 shows the substrate bias voltage Vsub of the NMOSFET in the peripheral circuit. = -2 Volts, critical voltage Vth = 1.30 Volts "
根據本發明之精神，週邊電路，亦即於元件區域之 電晶體並不限定一定是CMOSFET，亦可么是NMOSFET 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） ^^1 n^— ^^^1 I —^1 in I - ? _· —i-1 m ,I0JI -1 1- I - - In I (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（） 或 PMOSFET。 仔細檢視本發明，我們可以發現具不同臨界電壓之 N型金屬氧化物半導體場效電晶體可以很容易被製作出 來而相較於參考資料“Y.J. Wann, et al.，U.S. patent, No. :5,514,610(1 99 6)”亦無需額外之罩幕（亦即無需遮蔽 氧化層）。 本發明所提供之優點爲（1)具不同臨界電壓之N型 金屬氧化物半導體場效電晶體可以很容易被製作出來而 無需額外之軍幕，且（2)所提出之製程參數易於製造。 本發明以較佳實施例説明如上，而熟悉此領域技藝 者，在不脱離本發明之精神範圍内，當可作些許更動潤 飾，其專利保護範圍更當視後附之申請專利範圍及其等同 領域而定。 —^n ^^^^1 nn mi ^ϋ·— ^^^^1 I nn ^ y flm HI— n t ,-/1 i {請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印褽 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）According to the spirit of the present invention, the peripheral circuit, that is, the transistor in the element area is not necessarily limited to CMOSFET, or can it be NMOSFET. This paper size applies to Chinese national standards (CNS > A4 specification (210X297 mm) ^^ 1 n ^ — ^^^ 1 I — ^ 1 in I-? _ · —i-1 m, I0JI -1 1- I--In I (Please read the precautions on the back before filling this page) A7 B7 V. Description of the invention () or PMOSFET. A closer inspection of the present invention reveals that N-type metal oxide semiconductor field effect transistors with different threshold voltages can be easily fabricated compared to the reference "YJ Wann, et al., US patent, No .: 5,514,610 (1 99 6) "also does not require an additional mask (ie, does not need to shield the oxide layer). The advantages provided by the present invention are (1) N-type metal oxide semiconductor fields with different threshold voltages The effect transistor can be easily manufactured without the need for an additional military curtain, and (2) the proposed process parameters are easy to manufacture. The present invention is described above with reference to the preferred embodiment, and those skilled in the art will not depart from this. Within the spirit of the invention, something should be done Change the retouching, the scope of its patent protection depends on the scope of the attached patent application and its equivalent field. — ^ N ^^^^ 1 nn mi ^ ϋ · — ^^^^ 1 I nn ^ y flm HI— nt ,-/ 1 i {Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is sized for the Chinese National Standard (CNS) A4 (210X297 mm)