TW401624B - Device structure of metal-oxide-semiconductor (MOS) and the manufacture method - Google Patents

Abstract

The invention provides a device structure of metal-oxide-semiconductor (MOS) and the manufacture method. The transistor comprises a substrate, a gate insulation layer, a dielectrics, and a gate which includes a conductive layer and a salicide layer. A drain and a source are included on the surface of the substrate. The drain and such source are arranged on two neighboring but disconnected regions on the surface of the substrate. The gate insulation layer is arranged on the surface of the substrate and sited between the drain and source. The conductive layer is arranged on the gate insulation layer, which comprises a bottom plane, a top plane, a left side and a right side. The salicide layer is arranged above the top plane of the conductive layer, which is used to lower the resistance of the conductive layer. The width of the salicide is larger than the width of the bottom plane. The dielectrics is arranged above the salicide layer of the drain, the source and the gate, and is used as the insulation layer outside the transistor. Between the left side of the conductive layer or the right side of the conductive layer and the dielectrics, there is provided with at least one side-groove sited below the salicide layer.

Description

401624 Five 'invention description (1)' ~ The present invention provides a metal oxide semiconductor (meta_semiconductor, abbreviated as MOS) transistor, especially a device structure and manufacturing method of MOS transistor. The application of M0S transistors in the semiconductor industry is very common. There are many tiny M0S transistors on semiconductor crystal 1, referred to as transistors, how to overcome the difficulties in the process 'to make smaller transistors and obtain electrical advantages' is Semiconductor manufacturing is not an important issue. Please refer to FIG. 1 ′ FIG. 1 is a cross-sectional view of a conventional transistor element structure. The conventional transistor 10 includes a rectangular gate electrode 14, an electrode 16, and a source electrode 18. The gate electrode 4 includes a gate conductive layer 15 and a metal oxide layer 20, and two side walls 17 are provided on two side walls of the gate electrode 14. ;: And electrodes 16 and 18 respectively include a high-concentration implant layer 21, 2 3, a high-concentration drain / low-concentration drain (HDD / LDD) structure HDD / LDD layers 25, 27, and a metal oxide layer 22, 24. The transistor 10_ is isolated on the substrate 11 of the semiconductor wafer with other semiconductor elements. ~ This structure of transistor 10 has been widely used, but when the semiconductor process below 〇 丨 'to make the transistor of this structure very small, there will be many disadvantages, such as: 1. Huang Guangbu Increased cost of lithography stepper: Huang Guangbu

401624 V. Description of the invention (2) Most of the light sources used in the machine are deep ultraviolet (Deepu V) light, and in the process below / (Λ 0 · 18 um), exposure is often caused by light interference or diffraction. After the poor graphics, it is necessary to replace the light source with a shorter wavelength to meet the requirements of the yellow light process, and the cost of replacing the light source or even the yellow light step will increase the cost. 2. Difficulties in forming metal silicide: metal silicide layer 20, 22, and 24 are used to reduce the conductive resistance of the gate 14, the drain 16, and the source 18. The metal silicide is formed by the reaction of the metal with the silicon on the semiconductor wafer, usually using rhenium and the gate 14, The silicon on the surface of the drain electrode 16 and the source electrode 18 reacts to form silicon titanate (Ti_saUcide). The area of silicon must be large enough for titanium to react with silicon to form silicon titanate. With the reduction of μ〇§ transistor 10, the gate The width of the pole 14 is also reduced. When the bean reaches a process size of less than 0.1 μm, the silicon width on the surface of the gate 14 is too small, which makes it difficult to form a metal silicide. Therefore, the main purpose of the present invention is to provide a pure 媸 L … P To recognize the opening of a M0S transistor:-the structure and the corresponding producer ☆ the 曰, point of the electric body, and the transistor of the present invention has many electrical advantages to overcome the simple illustration shown in Figure 81 is a conventional electric In the south of the crystal furnace of the element furnace, the earthen figure-method, the cross section of 卞, 〇 is not intended.-The cross section of the transistor element m-^ ^ 卄,, 、 of the transistor of the present invention is not intended.

Fig. 10 is a schematic cross-sectional view of the method for making si-lei__ plate-making method 1.疋 Figure 1 Flow chart of the production method of the electric sun. 4〇1β ^ 4

Symbols shown in the figure 29 transistor 3 3 base well 3 4 > and pole 38 gate insulating layer 42 conductive layer, dielectric layer 5 8, 60 0 high concentration drain or low concentration 62, 64 pocket layer 6 8 nitrogen Ε evening layer 7 2 trench side wall 7 5 side wall 31 substrate 3 2, 3 5 South concentration implant layer 3 6 source 4 0 gate 48, 54, 56 metal silicide layer 5 2 side slot drain Level layer 66 Shallow trench 70 The bottom 74 of the first silicon oxide layer is as shown in FIG. 2; FIG. 2 is a schematic cross-sectional view of the element structure of the transistor 29 of the present invention. The transistor 29 of the present invention includes a substrate 3l, a gate insulating layer 38 ', a dielectric layer 50', and a gate 4O. The transistor 29 includes a conductive layer 42 and a metal silicide layer 46. The surface layer of the substrate 31 includes a substrate well 33, which includes an electrode 34 and a source 36 ', and the electrode 34 and the source 36 are provided on the two adjacent and non-connected areas of the surface of the substrate 31. The gate insulating layer 38 is disposed on the surface of the substrate 31 and is located between the drain electrode 3 4 and the source electrode 36. The conductive layer 42 is disposed on the gate insulating layer 38. The conductive layer 42 includes a bottom plane 43, a top plane 44, a left side 45, and a right side 46 '. The width of the top plane 44 is greater than the bottom plane 43.

Page 7 5. The left and right width of the description of the invention (4). The metal crack layer 48 is disposed on the top plane 44 of the conductive layer 42 'to reduce the resistance of the conductive layer 42' and the width of the metal silicide layer 48 is greater than the width of the bottom plane 43. The dielectric layer 50 is laid on the metal silicide layer 48 of the drain 34, the source 36, and the gate 40, and is used as an insulating layer outside the transistor. The left and right sides 45, 46 of the conductive layer 4 2 and the dielectric layer 50 each include a side groove 5 2 having a similar shape, which is located below the metal silicide layer 48 and the top plane 44. The drain electrode 34 and the source electrode 36 each include a high-concentration implant layer 32, 35, and the metal silicide layers 54, 56 are disposed on the surface layers of the high-concentration implant layers 32 and 35, and are used to reduce the drain electrode 34 and the source electrode 36 A conductive resistance, an HDD / LDD layer 58 and 60 are provided on the surface of the substrate well 33 near the gate 40 to reduce the thermoelectronic effect of the transistor 29, and a pocket layer 62 and 64 are provided on the HDD / Below the LDD layers 58 and 60 and covering the HDD / LDD layers 58 and 60, the through voltage of the transistor 29 is adjusted. Please refer to FIGS. 3 to 10, which are schematic cross-sectional views of a method for manufacturing the transistor 29 in FIG. The transistor manufacturing method of the present invention is used for manufacturing a transistor 29 on a semiconductor wafer 30. As shown in Figure 3, the base of the semiconductor wafer 30

The bottom 31 is provided with a plurality of shallow trenches 6 6 ′ made by a shallow trench isolation method as electrical isolation of the semiconductor elements on the wafer 30, and the surface layer of the base 31 is provided with an ion implantation method. The p-type (or N-type) basement well 33.

Page 8 V. Description of the invention (5) " '-As shown in Fig. 4, the method for fabricating a transistor of the present invention first forms a silicon nitride layer 68 on the surface of a semiconductor wafer 30. Next, the silicon nitride layer 68 of a predetermined area is divided by the yellow light and the etching process Z to form a vertical trench 71 that reaches the surface of the substrate well 33. This step is referred to as gate patterning. The trench 71 includes a trench bottom 70 and two trench sidewalls U 2, and then ion implantation is performed on the trench 71 to adjust the threshold voltage of the transistor 29 (referred to as punch-through v). 〇ltage (referred to as Vp) / This step is referred to as local implantation, and the dotted line shown in Figure 4 is the ion implantation area. X As shown in Figure 5, followed by chemical vapor deposition (chemical vap 〇r (abbreviated as CVD) method is applied to the nitride layer 68 and the surface of the trench 7 and the silicon layer 74 ′, and then uses silicon nitride as the material between the trench bottom 70 and a trench sidewall 72. The two corners form a two-sided sidewall. Figure ^ Jin shows, and then remove the bottom of the trench 70 located on the two-sided sidewall ^ and then the abundance layer 74 'This step is referred to as oxide dip (〇xide dip).: , R: sheet 3. Performing-thermal oxidation G: formation of Γ removal sites-formation of oxidized stone (si--0xlde) surface deposition 2: edge layer 38. Then the CVD method is used on the semiconductor wafer 30 to m ^ Day-to-day silicon layer, and then chemical mechanical polishing (chemical crystal stone r, caj Γ1 ishing, simplified (Called CMP) method to remove the polycrystalline silicon layer outside the trench 71-filling the conductive layer 42 of the trench 71 as

401624 V. Description of the invention (6) The gate of the transistor 40. As shown in FIG. 7, the silicon nitride layer 68 is then removed by hot phosphoric acid. Then, an ion implantation is performed on a predetermined area of the surface of the base well 33 adjacent to the two trench sidewalls 72 to form high-concentration implantation layers 32 and 35 as the drain 34 and the source 36. This step is referred to as source implantation. / drain impiantati〇n). Then a thermal / drain thermal annealing process is performed on the drain 34 and the source 36 to repair the damage to the surface of the semiconductor wafer 30 caused by the source implant and activate the implanted source implant. For cloth plants, this step is referred to as S / D annealing. As shown in FIG. 8, a wet etch method is then used to remove the first oxonite layer 7 4 ′ on a trench sidewall 7 2. This step is also referred to as oxygen; g leaching. Then, a self-aligned (se 1 f-a 1 i gn) metal silicide formation method is used to form metal silicide layers 4 8, 5 4, and 4 on the surfaces of the conductive layer 42, the drain 34, and the source 36, respectively. 5 6, as shown in Figure 8. The metal petrochemical layers 48, 54 and 56 are composed of titanium silicide or petroxide, which can reduce the conductive resistance of the gate 40, the drain 34, and the source 36. As shown in FIG. 9 ', the two side walls 7 5 are then removed by hot phosphoric acid wet lasting method. Then, ion implantation is performed on the removed portion of the second sidewall 75 to form HDD / LDD layers 58 and 60, so that the drain 34 and the source electrode 36 extend below the removed portion of the second sidewall 75. This step is abbreviated HDD / LDD deployment. Then, ion implantation was performed again on the removed part of the two side walls 7 5.

V. Description of the invention (7) Two pocket layers 62, 64 are formed under the HDD / LDD layers 58, 60. This step is commonly referred to as a halo deployment. The two pockets 62 and 64 cover the two HDD / LDD layers 58 and 60, and the penetration voltage of the transistor can be adjusted. Then a rapid thermal process (RTP) is performed on the semiconductor wafer 30 for a short period of time (RTP) to activate the HDD / LDD implantation and pocket implantation. As shown in the figure, a dielectric layer 50 is formed on the semiconductor wafer 30 using borophospho silicate glass (BPSG) or undoped silicate glass (USG) to cover the gate electrode 4 by CVD. , Drain 34, and source 36 surfaces, and side grooves 52 of air gaps are formed at the removed portions of the two side walls 75. This step is referred to as in-line dielectric (int er). i ay er ^ ie 1 ec tric (ILD for short) deposition, and the production of the transistor 29 is completed. Since the side groove 52 is carved from the original side wall member 75, the shape of the side side groove 52 is similar to that of the side wall member 7 5. The side groove 52 is an empty groove, and its dielectric constant is 1 or approximately 1, which can be used to reduce the parasitic capacitance between the gate and the drain or between the gate and the source. FIG. 11 is a flowchart of a method for manufacturing the transistor 29 of the present invention. In summary, when the shallow trench 66 and the P-type (or N-type) base well 33 of the STi process on the semiconductor wafer 30 are completed, the method for manufacturing the transistor 29 of the present invention and the transistor 29 of the present invention can be performed. The production method can be briefly expressed by the following steps:

Page 11 4Qt- $ 24 V. Description of the invention (8) Step 80: Nitride stone deposition to form an atmosphere layer 6 8; Step 81: Gate definition, define the vertical trench on the nitride layer 68 71; Step 8 2: Partial implantation; Step 8 3 ·· First oxygen silicon layer 74 deposition; Step 84: Fabrication of two side walls 75; Step 8 5: Oxygen crushing leaching; Step 86: Gate insulation Layer 38 is formed; step 87: polycrystalline silicon layer deposition; step 88: polycrystalline silicon CMP, removing polycrystalline silicon layer outside trench 71 to form gate 40; step 89: removing silicon nitride layer 68; step 90: Source drain is planted to form drain 34 and source 36; Step 9 1: Source drain annealing; Step 9 2: Oxygen-silicon leaching; Step 9 3: Formation of metal dream layer; Step 94 ·· Two sidewalls 75 Removal; 'Step 95: HDD / LDD implantation to form HDD / LDD layers 58, 60; Step 96: ha 1 0 implantation to form two pocket layers 6 2, 6 4; Step 97: spike RTP; Step 98: ILD deposition. The transistor 29 structure and manufacturing method of the present invention have many advantages, such as:

Page 12 401624 V. Description of the invention (9) 1. The parasitic capacitance of the gate 40 to the non-pole 34 and the gate 40 to the source 36 becomes smaller: the gate 40 to the drain 34 and the gate 40 to the source 36 The parasitic capacitance depends on the material between the gate 40 to the drain 34 and the gate 40 to the source 36. The greater the dielectric constant of the material, the larger the capacitance and the slower the electronic signal response of the transistor. . Because the transistor 2 9 of the present invention has a side groove 52, and the side groove 52 is an empty groove, the dielectric constant thereof is close to 1 which is the smallest in nature, so the parasitic capacitance becomes smaller, and the electronic signal response speed of the transistor can be increased. . 2. 3. The parasitic capacitance of f pole 36 and drain 34 to substrate well 3 3 can be suppressed: the local implantation is to adjust the vt and Vp of transistor 29, and the cloth implanted during the local implantation of the present invention Plants (dosage) will only be placed in the basement well 33 below the gate 40 (the area enclosed by the dotted line shown in Figure 4 is the ion implantation area), and will not be placed in the source 36 and the drain 34 inside the basement well 33. Therefore, in addition to the local implantation, the Vt and Vp 'of the transistor μ can be effectively adjusted, and the parasitic valley of the source well 36 and the drain 34 to the base well 33 cannot be excessively increased. Only the light stepper (lithography stepper) does not need to be changed as the process evolves. When the transistor 29 process is defined in the gate, it is only necessary to use the mask of the 2u line width spear king and the yellow light stepper. A groove 7i with a width of 2um (space Wjdth) is adjusted, and the sidewalls are appropriately adjusted. &Amp; 'The bottom plane 43 of the gate conductive layer 42 can be controlled to a line width of about 4. ^ 1 um, As a smaller transistor, the present invention does not require replacement of the yellow light stepper. Easy formation of metal silicide: Because the metal silicide layer of the present invention has a shape of 48

Page 13 V. Description of the invention (10) Before completion, the conductive layer 42 of the gate electrode 40 has a structure with a wide width and a narrow width. When the bottom plane 43 of the conductive layer 42 reaches a line width of about 0.1 lum, metal silicide is formed. The gate electrode 40 in front of the material layer 48 has a line width on the surface of the conductive layer 42 greater than 0.1 um, and a line width on the surface of the conductive layer 42 can even reach 0.2 um. This width is very easy for the formation of metal silicide. 5. Short channel ef feet can suppress: general HDD / LDD structure will cause lateral diffusion due to high temperature, which will cause short channel effect under the gate insulation layer 38. The HDD / LDD layers 58, 60 of the present invention are formed after the sidewalls 75 are removed (steps 94, 95), while the HDD / LDD layers 58, 60 only encounter spike RTP (step 97), and will not be affected for a long time. Affected by the high temperature (for example, step 91), since the lateral diffusion of the HDD / LDD layers 58 and 60 due to the high temperature decreases the channel growth, the present invention can suppress the short-pass two-layer edge layer compared to the conventional transistor 10 'In the element structure of the transistor 29 of the present invention, the left and right width of the top plane of the conductive layer is greater than the right and left width of the bottom flat plane, the left and right width of the gate metal silicide layer, and the left and right width of the plane, and the transistor 29 has fs-these structures make the present invention have a lot of electrical properties and = side grooves, this body 'at the same time and make the transistor transistor point ... the element structure of the transistor of the present invention is electrically superior to the line width 0. 18. Semiconductor process below. Sigh ^ • The method is very applicable

Page 15

Claims (1)

Scope of Patent Application 1. A metal-oxide-seffliconductor transistor includes: a substrate, the surface of which includes a drain and a source, and the source and the source It is located in two adjacent but unconnected areas of the base surface layer; a gate insulating layer is provided on the surface of the base and is located between the drain and source; a gate includes: a conductive layer Is provided on the gate insulating layer, and includes a bottom plane, a top plane, a left side and a right side ·, and a metal silicide layer provided on the top plane of the conductive layer. To reduce the electrical resistance of the conductive layer, the left and right width of the metal silicide layer is greater than the left and right width of the bottom plane; 'On layer' is used as an insulating layer outside the transistor; wherein at least one side groove between the left side or the right side of the conductive layer and the dielectric layer is located under the metal silicide layer. 2. If applying for The transistor of item 1 of the utility model, wherein the left and right width of the top plane of the conductive layer is greater than the width of the bottom plane. 3. For the transistor of the item 1 of the patent application, the left side of the conductive layer and Each of the dielectric layers includes a side with a similar shape below the top plane. 4 · t: Second search :: The transistor around item 1, where the side groove is' Wu Er 1's electric constant system is 1 or approximately 1, which is used to reduce the intermediate electrode ... ° 3 Parasitic capacitance between the sources. The shape of the etched 5.:1 patent liL surrounds the transistor of item 1. The side of the recessed ⑥ in ⑥ is similar to a spacer, which is formed by one. J 6 .: Shen? The transistor in item i of the patent is a silicon oxide layer. m rent, also marginal layer system 7. If the application of the scope of the patent application 丨 transistor, the material layer is composed of titanium crane or a dream of the metal alloy of the pole electrode 8. If the scope of the patent application of the patent i The system is a township spar. The conductive layer of the gate electrode 9. The transistor of the first scope of the patent, in which the dielectric layer is-Λ, silicon glass (b〇r〇phospho silicate giass, / ρς ('... impurity silicon broken glass (undoped silicate glass, USG).), or a method of making a 1G.i ^ oxide semiconductor transistor, which includes the following Page 17 VI. Scope of patent application. A silicon nitride layer is formed on the surface of a semiconductor wafer. A vertical trench is formed on the silicon nitride layer and reaches the surface of the semiconductor wafer. The trench includes a trench bottom and two trenches. Forming a first oxygen silicon layer on the surface of the trench; forming two sidewalls on the bottom of the trench and two corners between the sidewalls of the two trenches; removing the bottom of the trench on the two sidewalls A first oxide silicon layer between the two, and a gate insulating layer is formed at the removed portion; a conductive layer filling the groove is formed in the trench as an electrode between the transistors; and the surface of the semiconductor wafer is removed A silicon nitride layer; performing an ion implantation on a predetermined area of the surface of the conductor wafer adjacent to the sidewalls of the two trenches to form the drain and source of the transistor; removing the first silicon oxide on the sidewalls of the two trenches Layer; removing the two sidewalls; performing an ion implantation on the removed portion of the two sidewalls at the bottom of the trench to extend the drain and source electrodes to the removed portion of the two sidewalls; and on the semiconductor A wafer Layer to cover the gate, drain and source surface and form two recesses for the removal of the two sidewall portions of the child. 11. The manufacturing method according to item 10 of the patent application scope, wherein the two sidewalls are formed of silicon nitride. Page 18 401624 VI. Application for Patent Scope 12 The manufacturing method of item 10 in the scope of patent application, wherein when the first oxygen silicon layer is formed on the surface of the trench, the first oxygen silicon layer is also formed at the same time: The silicon layer surface, and the conductive layer in the trench is formed by: forming the silicon nitride layer and the trench-filling the conductive layer in the trench; and chemical mechanical polishing (CMP) The conductive layer above the silicon nitride layer and the oxygen oxide layer are removed to form a conductive layer in the trench. 13 .: The manufacturing method of the scope of application for patent No. 10, wherein after forming the drain and source of the electric body, the method further includes the following steps: applying a thermal anneal treatment to repair Damage to the wafer due to ion implantation and activation of the implanted plant. 14. The manufacturing method of item 10 in the scope of patent application, wherein before removing the two sidewalls, the method further includes the following steps:; the conductive layer of the idler electrode and the surface of the drain and source electrodes form a metal = The material layer to reduce the closed-electrode conductive layer and the; and the source and the source, such as the part of the patent application scope of the manufacturing department of the second side of the removal of the two side walls of the part further includes the following steps: After the trench bottom is ion implanted, the method 401624