558754 5320twf.doc/006 A7 B7 五、發明說明（/) 本發d是有關於一種半導體元件的製造法，且特別是 有關於一種自動對準金屬矽化製程的方法。 (請先閱讀背面之注意事項再填寫本頁) 夾著高熔點、穩定性及低電阻率等優點，金屬矽化物 (Metal Silicide)於積體電路製程上的應用，已愈來愈普 遍。而在線寬、接觸面積及接面深度等逐漸縮小的深次微 米積體電路的技術中，爲了能有效地提高元件的工作品 質，降低電阻並減少電阻及電容（RC)所造成的信號傳遞延 遲，因此習知在複晶矽閘極上或源極/汲極區之接面處會 再形成一層金屬矽化物，以達到降低閘極電阻、接面電阻， 進而提高整個元件的驅動電流，反應時間或電路的操作速 度。 目前廣泛應用於積體電路製程的技術係一種稱之爲自 動對準金屬矽化物（Self-Aligned Silicide，Salicide) 的製程。自動對準金屬矽化製程，係在基底上沉積金屬層 之後，直接利用熱製程即可以使得金屬層與所接觸的矽成 分，例如是複晶矽閘極或是源極/汲極區發生矽化反應而 生成矽化金屬層，至於未與矽接觸的部分則可以蝕刻去 除。由於整個形成金屬矽化物的製程並不需透過微影的方 式以定義其圖形，故稱之爲自動對準金屬矽化物製程。 經濟部智慧財產局員工消費合作社印製 第1A圖至第1C圖係繪示習知一種進行自動對準金屬 矽化製程之半導體元件的製造流程面圖。 請參照第1A圖，首先，在基底100的互補式金氧半 電晶體區120與靜電放電保護元件區122分別形成N型金 氧半電晶體（NMOS)102、P型金氧半電晶體（PMOS)104與靜 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 558754 5320twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（芝） 電放電保護電晶體106。之後，在基底1〇〇上沉積並定義 一層金屬矽化阻擋層108，以覆蓋靜電放電保護元件區122 中預定不形成矽化金屬層的區域，例如是閘極與汲極區。 通常，在進行自動對準金屬矽化製程時，爲了增加矽化金 屬層的成核數目，典型的作法係在金屬矽化阻擋層108形 成之後進行一道預非晶格化之離子植入（Pre-Amorphous Implant ’ PAI)步驟110，以使預定形成矽化金屬層的區域 非晶格化。 之後請參照第1B圖，在基底1〇〇上形成一層金屬層 112 ’再進行熱製程，以使金屬層112與所接觸的矽成分 反應，而形成矽化金屬層114，其後，再將金屬層112未 參與反應的部分以及金屬矽化阻擋層108去除，以形成如 第1C圖所示之結構。 由於預非晶格化之離子植入110步驟係在形成金屬矽 化阻擋層108之後’而在圖案化金屬矽化阻擋層1〇8的蝕 刻過程中，由於蝕刻終點掌握不易，部分的基底1〇〇表面 遭受蝕刻的破壞，使得後續之預非晶格化之離子植入11〇 造成基底的漏電流以及通道效應（Channel EffecU。 因此，本發明的目的就是在提供一種自動對準金屬矽 化製程的方法，可以避免元件因爲非晶格化之離子植入製 程所造成的漏電流問題。 本發明的目的再一目的是提供一種自動對準金屬矽化 製程的方法，可以避免元件因爲非晶格化之離子植入製程 所造成的通道效應。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) · ! ! I 訂·！ ！！' 558754 5320twf.doc/006 A7 ___ B7 五、發明說明（>) 本發明提出一種自動對準金屬矽化製程的方法，此方 法係在基底上覆蓋金屬矽化阻擋層之前，先分別對基底的 N型金氧半電晶體與P型金氧半電晶體進行N型預非晶格 化之離子植入製程與P型預非晶格化之離子植入製程，以 使該N型金氧半電晶體與P型金氧半電晶體之閘極與源極 /汲極的表面非晶格化，接著，再於基底上預定不形矽化 金屬層的區域覆蓋一層金屬砂化阻擋層，之後，在基底上 覆蓋一層金屬層，並進行熱製程，使部分金屬層發生砂化 反應而形成矽化金屬層，最後再去除金屬層未反應的部分 以及金屬矽化阻擋層。 依照本發明的較佳實施例所述，可以控制上述之N型 預非晶格化之離子植入製程與P型預非晶格化之離子植入 製程所植入的離子劑量，以符合N型金氧半電晶體與P型 金氧半電晶體進行自動對準金屬矽化製程之需求。 而且，本發明在預定不形成的區域之中，並未進行非 晶格化之離子植入步驟，因此，可以避免其閘極或源極/ 汲極區因爲植入非晶格化之離子而造成阻値上升的問題。 此外，由於非晶格化之離子植入步驟，係在圖案化金 屬矽化阻擋層之蝕刻製程之前施行，因此可以避免習知因 爲蝕刻破壞基底所造成的漏電流問題並且可以避免習知通 道效應等問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 5 本紙張尺度適用f國國家標準（CNS)A4規格（210 X 297公楚） (請先閱讀背面之注意事項再填寫本頁) 罗裝--------訂--------- si. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 558754 5320twf.doc/006 pj B7 五、發明說明（斗） 圖式之簡單說明： 第1A圖至第1C圖係繪示習知一種進行自動對準金屬 矽化製程之半導體元件的製造流程面圖。 第2A圖至第2H圖，其繪示依照本發明一較佳實施例 的一種進行自動對準金屬矽化製程之半導體元件的製造流 程剖面圖。 - 圖式之標示說明：558754 5320twf.doc / 006 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for automatically aligning a metal silicidation process. (Please read the precautions on the back before filling out this page.) With the advantages of high melting point, stability, and low resistivity, the application of metal silicide in integrated circuit manufacturing has become more and more common. In the technology of deep sub-micron integrated circuits with gradually decreasing line width, contact area, and interface depth, in order to effectively improve the working quality of components, reduce resistance and reduce signal transmission delay caused by resistance and capacitance (RC) Therefore, it is known that a layer of metal silicide will be formed on the polycrystalline silicon gate or the junction of the source / drain region to reduce the gate resistance and junction resistance, thereby increasing the driving current and response time of the entire device. Or the operating speed of the circuit. The technology currently widely used in integrated circuit manufacturing is a process called Self-Aligned Silicide (Salicide). Automatic alignment of metal silicidation process. After the metal layer is deposited on the substrate, the thermal process can be used directly to make the metal layer and the silicon components in contact with it, such as a polysilicon gate or a source / drain region. The silicided metal layer is formed, and the portion not in contact with the silicon can be removed by etching. Since the entire process of forming metal silicide does not require lithography to define its pattern, it is called an automatic alignment metal silicide process. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figures 1A to 1C are diagrams showing the manufacturing process of a conventional semiconductor device that performs automatic metal silicidation process. Referring to FIG. 1A, first, an N-type metal-oxide-semiconductor (NMOS) 102 and a P-type metal-oxide-semiconductor (NMOS) 102 and a P-type metal oxide semiconductor ( PMOS) 104 and static paper sizes are in accordance with Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 558754 5320twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Discharge protection transistor 106. After that, a metal silicide blocking layer 108 is deposited and defined on the substrate 100 to cover regions in the ESD protection element region 122 where the silicide metal layer is not to be formed, such as the gate and drain regions. Generally, in the process of auto-aligning metal silicidation, in order to increase the number of nucleation of the silicided metal layer, a typical method is to perform a pre-amorphous ion implantation after the metal silicide blocking layer 108 is formed. 'PAI) step 110 to make the region where the silicide metal layer is to be formed amorphous. After referring to FIG. 1B, a metal layer 112 ′ is formed on the substrate 100, and then a thermal process is performed to make the metal layer 112 react with the silicon component in contact with it to form a silicided metal layer 114. The portion of the layer 112 that does not participate in the reaction and the metal silicide blocking layer 108 are removed to form a structure as shown in FIG. 1C. Because the pre-amorphized lattice ion implantation step 110 is performed after the metal silicide barrier layer 108 is formed, and during the etching process of the patterned metal silicide barrier layer 108, part of the substrate 100 is difficult to grasp due to the difficulty of grasping the etching end point. The surface is damaged by etching, so that the subsequent pre-amorphized ion implantation 11 causes the leakage current of the substrate and the channel effect (Channel EffecU. Therefore, the object of the present invention is to provide a method for automatically aligning the metal silicidation process. It can avoid the leakage current problem caused by the amorphous lattice ion implantation process. Another object of the present invention is to provide a method for automatically aligning the metal silicidation process, which can avoid the element because of the amorphous lattice ion. Channel effect caused by the implantation process. 4 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling out this page) ·!! I Order !! 558754 5320twf.doc / 006 A7 ___ B7 V. Description of the invention (>) The present invention proposes a method for automatically aligning a metal silicidation process. This method is Before covering the substrate with a metal silicidation barrier layer, firstly perform N-type pre-lattice ion implantation process and P-type pre-amorphous lattice on the N-type metal-oxide-semiconductor and P-type metal-oxide-semiconductor of the substrate. An ion implantation process is performed to make the surface of the gate and source / drain of the N-type metal-oxide semiconductor and the P-type metal oxide semiconductor to be amorphous, and then to form a non-silicide on the substrate. The area of the metal layer is covered with a metal sanding barrier layer. After that, a metal layer is covered on the substrate and a thermal process is performed to sand the part of the metal layer to form a silicided metal layer. Finally, the unreacted part of the metal layer is removed. And a metal silicidation barrier layer. According to a preferred embodiment of the present invention, the implanted N-type pre-amorphized ion implantation process and the P-type pre-amorphized ion implantation process can be controlled. The ion dose is in accordance with the requirements of the metal silicidation process for automatic alignment of N-type metal-oxide semiconductor and P-type metal-oxide semiconductors. Moreover, the present invention does not perform amorphous lattice formation in regions that are not expected to form. Ion implantation steps Therefore, the problem that the gate or source / drain region is prevented from rising due to the implantation of amorphous lattice ions can be avoided. In addition, because the amorphous lattice ion implantation step is in the patterned metal silicide The barrier layer is etched before the etching process, so it is possible to avoid the leakage current problem caused by etching damage to the substrate and the conventional channel effect. To make the above and other objects, features, and advantages of the present invention more obvious It is easy to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings, which are described in detail as follows: 5 This paper size applies to National Standards (CNS) A4 (210 X 297). (Please read the back first Please note that this page is to be filled out again.) Luo Zong -------- Order --------- si. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 558754 5320twf.doc / 006 pj B7 V. Brief description of the invention (figure) Figures 1A to 1C are diagrams showing the manufacturing process of a conventional semiconductor device for automatic alignment metal silicidation process. FIG. 2A to FIG. 2H are cross-sectional views showing a manufacturing process of a semiconductor device performing an automatic alignment metal silicidation process according to a preferred embodiment of the present invention. -Schematic description:
100、200 :基底 102 、 262 : NMOS 104 、 266 : PMOS 106、264 :靜電放電保護電晶體 108、242a :金屬矽化阻擋層 110 :預非晶格化之離子植入 112、246 :金屬層 114、248、250、252、254、256 :矽化金屬層 202 :隔離區 204 ·· P 井 206 : N 井 208、210、212 :閘極 214、216 :淡摻雜源極/汲極區 218 :間隙壁 220、228、234、238、244 ··光阻層 222 : N型離子植入 224、226、232 :源極/汲極區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) _裝----IIII 訂---------%i. 558754 5320twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（夕） 230 : P型離子植入 236 : N型預非晶格化之離子植入 240 : P型預非晶格化之離子植入 242 :絕緣層 實施例 第2A圖至第2H圖，其繪示依照本發明一較佳實施例 的一種自動對準金屬矽化製程的製造流程剖面圖。 請參照第2A圖，提供一基底200，此基底200可區分 爲互補式金氧半電晶體區260與靜電放電保護元件區 270。首先，在基底1〇〇中形成隔離區202，並在互補式金 氧半電晶體區260形成P型井204與N型井206。之後， 在互補式金氧半電晶體區260之P型井204與N型井206 上分別形成閘極208與閘極210，並在靜電放電保護元件 區270形成閘極212。接著，再分別於閘極208以及閘極 210兩側的基底200之中形成N型淡摻雜源極/汲極區214 與P型淡摻雜源極/汲極區216。 之後，請參照第2B圖，在閘極208、210、212的側 壁形成間隙壁218，然後，在基底200上形成一層光阻層 220，以覆蓋N型井206上方之閘極210、間隙壁218與P 型淡摻雜源極/汲極區216，裸露出互補式金氧半電晶體區 260之P型井204上之閘極208、間隙壁218、與N型淡摻 雜源極/汲極區214以及靜電放電保護元件區270之閘極 212、間隙壁218。接著，以光阻層220、閘極208、212 與間隙壁218爲植入罩幕，進行N型濃摻雜離子植入222 7 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） -----------^^裝--------訂---------^^1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 558754 5320twf.doc/006 pj —___ B7 五、發明說明（6) 步驟，之後去除光阻層220，再進行回火製程，以在互補 式金氧半電晶體區260之閘極208的間隙壁218其兩側的 基底200中形成濃摻雜源極/汲極區224，並在靜電放電保 護元件區270之閘極212的間隙壁218其兩側的基底200 中形成源極/汲極區226。N型濃摻雜離子植入222步驟， 係在閘極208、212與基底200中植入N型離子，例如是 磷或砷。而施行回火製程的溫度例如是攝氏800度。此時， 互補式金氧半電晶體區260其P井204上已形成一 N型金 氧半電晶體262 ;而靜電放電保護元件區270已形成一靜 電放電保護電晶體264。 然後，請參照第2C圖，接著，在基底200上形成另 一層光阻層228，以覆蓋互補式金氧半電晶體區260之N 型金氧半電晶體262與靜電放電保護元件區270之靜電放 電保護電晶體264，裸露出互補式金氧半電晶體區260之 N型井206上之閘極210、間隙壁218、與P型淡摻雜源極 /汲極區216。接著，以光阻層228、閘極210與間隙壁218 爲植入罩幕，進行P型濃摻雜離子植入230步驟，之後去 除光阻層228，再進行回火製程，以在互補式金氧半電晶 體區260之閘極210的間隙壁218其兩側的基底200中形 成濃摻雜源極/汲極區2324型濃摻雜離子植入230步驟， 係在閘極210與基底200中植入P型離子，例如是硼。而 施行回火製程的溫度例如是攝氏1050度。此時，互補式 金氧半電晶體區260其N井206上已形成一 P型金氧半電 晶體266。100, 200: Substrate 102, 262: NMOS 104, 266: PMOS 106, 264: Electrostatic discharge protection transistor 108, 242a: Metal silicide barrier layer 110: Pre-amorphized ion implantation 112, 246: Metal layer 114 , 248, 250, 252, 254, 256: silicided metal layer 202: isolation region 204.P well 206: N well 208, 210, 212: gate 214, 216: lightly doped source / drain region 218: Spacer wall 220, 228, 234, 238, 244 ·· Photoresist layer 222: N-type ion implantation 224, 226, 232: Source / drain region This paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) _Installation ---- Order IIII ---------% i. 558754 5320twf.doc / 006 A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative V. Description of the invention (Even) 230: P-type ion implantation 236: N-type pre-amorphized ion implantation 240: P-type pre-amorphous ion implantation 242: Insulation layer implementation Examples 2A to 2H are cross-sectional views illustrating a manufacturing process of an auto-aligned metal silicidation process according to a preferred embodiment of the present invention. Referring to FIG. 2A, a substrate 200 is provided. The substrate 200 can be divided into a complementary metal-oxide semiconductor region 260 and an electrostatic discharge protection element region 270. First, an isolation region 202 is formed in the substrate 100, and a P-type well 204 and an N-type well 206 are formed in the complementary metal-oxide semiconductor region 260. Thereafter, a gate 208 and a gate 210 are formed on the P-type well 204 and the N-type well 206 of the complementary metal-oxide semiconductor region 260, respectively, and a gate 212 is formed on the ESD protection element region 270. Next, an N-type lightly doped source / drain region 214 and a P-type lightly doped source / drain region 216 are formed in the substrate 200 on both sides of the gate 208 and the gate 210, respectively. Then, referring to FIG. 2B, a spacer 218 is formed on the side walls of the gates 208, 210, and 212. Then, a photoresist layer 220 is formed on the substrate 200 to cover the gate 210 and the spacers above the N-type well 206. 218 and P-type lightly doped source / drain region 216, exposing the gate 208, spacer 218, and N-type lightly doped source / on the P-type well 204 of the complementary metal-oxide-semiconductor region 260. The gate electrode 212 and the spacer 218 of the drain region 214 and the ESD protection element region 270. Next, the photoresist layer 220, the gate electrodes 208, 212, and the spacer 218 are used as implantation masks to perform N-type heavily doped ion implantation 222. 7 This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇X). 297 mm) ----------- ^^ 装 -------- Order --------- ^^ 1 (Please read the notes on the back before filling in this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 558754 5320twf.doc / 006 pj —___ B7 V. Description of the invention (6) Steps, after which the photoresist layer 220 is removed, and then the tempering process is performed to supplement the metal oxide The doped source / drain region 224 is formed in the substrate 200 on both sides of the gap 218 of the gate 208 of the semi-transistor region 260, and two of the gap 218 of the gate 212 of the electrostatic discharge protection element region 270 A source / drain region 226 is formed in the substrate 200 on the side. The N-type heavily doped ion implantation step 222 involves implanting N-type ions, such as phosphorus or arsenic, in the gates 208, 212 and the substrate 200. The temperature at which the tempering process is performed is, for example, 800 degrees Celsius. At this time, in the complementary metal-oxide-semiconductor region 260, an N-type metal-oxide-semiconductor 262 has been formed on the P well 204; and the electrostatic discharge protection element region 270 has formed an electrostatic discharge protection transistor 264. Then, referring to FIG. 2C, another photoresist layer 228 is formed on the substrate 200 to cover the N-type metal-oxide-semiconductor 262 of the complementary metal-oxide-semiconductor region 260 and the electrostatic discharge protection element region 270. The electrostatic discharge protection transistor 264 exposes the gate 210, the spacer 218, and the P-type lightly doped source / drain region 216 on the N-type well 206 of the complementary metal-oxide semiconductor region 260. Next, the photoresist layer 228, the gate 210, and the spacer 218 are used as the implant mask, and the P-type heavily doped ion implantation 230 step is performed. After that, the photoresist layer 228 is removed, and then the tempering process is performed to make the The spacer 218 of the gate electrode 210 of the metal-oxide semiconductor region 260 forms a heavily doped source / drain region 2324 type heavily doped ion implantation 230 in the substrate 200 on both sides, and the steps are performed between the gate 210 and the substrate. P-type ions are implanted in 200, such as boron. The temperature at which the tempering process is performed is, for example, 1050 degrees Celsius. At this time, in the complementary metal-oxide semiconductor region 260, a P-type metal-oxide semiconductor 266 has been formed in the N well 206 thereof.
X 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — — — -ml — — — ^ i — — — — — — — ^^^1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 558754 5320twf.doc/006 fij B7 五、發明說明（ο ) 其後，請參照第2D圖，在基底200上形成一層光阻 層234，以覆蓋P型金氧半電晶體266與靜電放電保護電 晶體，裸露出互補式金氧半電晶體區260之N型金氧半電 晶體262。之後，進行N型預非晶格化之離子植入236製 程，以使該N型金氧半電晶體262之閘極208與源極/汲 極區224之表面非晶格化。N型預非晶格化之離子植入236 製程例如是在閘極208與源極/汲極區224的表面植入N 型之磷或砷。 之後，請參照第2E圖，去除光阻層234，接著，在基 底200上形成另一層光阻層238，以覆蓋N型金氧半電晶 體262與靜電放電保護電晶體264，裸露出互補式金氧半 電晶體區260之P型金氧半電晶體266。之後，進行P型 預非晶格化之離子植入240製程，以使N型金氧半電晶體 266之閘極210與源極/汲極區232之表面非晶格化。P型 預非晶格化之離子植入240製程例如是在閘極210與源極 /汲極區232之表面植入P型之硼。値得一提的是，本發 明之P型預非晶格化之離子植入240製程與N型預非晶格 化之離子植入240製程可以將所植入的離子控制不同的劑 量，以符合N型金氧半電晶體與P型金氧半電晶體在進行 自動對準金屬矽化製程之需求。 接著，請參照第2F圖，去除光阻層238。之後，在基 底200上形成一層絕緣層242。絕緣層242例如是以四乙 基矽氧烷（TEOS)爲氣體源，利用電漿增益型化學氣相沉積 法（PECVD)所形成之氧化矽。其後，在基底200上形成一 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------·裝--------訂---------^9— (請先閱讀背面之注意事項再填寫本頁) 558754 ^320twf.doc/006 fij --- B7 五、發明說明（》） 層圖案化的光阻層244,以覆蓋靜電放電保護元件區270 預定不形成矽化金屬層的區域，例如是覆蓋靜電放電保護 元件區270之閘極212與汲極區226a。 然後，請參照第2G圖，以光阻層244爲蝕刻罩幕， 蝕刻去除未被光阻層244覆蓋的絕緣層242，使留下的絕 緣層242a作爲金屬矽化阻擋層。之後，在基底200上覆 蓋一層金屬層246。金屬層246之材質例如是鈦、鎢、鈷、 鎳、鈾或鈀，其形成的方法例如是濺鍍法。 最後，請參照第2H圖，進行熱製程，以使金屬層246 與所接觸之閘極208、210之複晶矽以及所接觸的基底200 的表面（源極/汲極區224、226與232)反應，而形成矽化 金屬層250、254、248、256、252。之後，再將金屬層246 未參與反應的部分以及絕緣層242a去除。 在以上的實施例中，係以靜電放電保護元件之汲極區 作爲預定不形成矽化金屬層之區域的例子。然而，預定不 形成矽化金屬層的區域，並不限定於此。預定不形成矽化 金屬層的區域尙可包括記憶胞區的源極與汲極區，例如是 動態隨機存取記憶體之源極與汲極區。X This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) — — — — — — — — — — — — — — ^ i — — — — — — — ^^^ 1 ( Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 558754 5320twf.doc / 006 fij B7 V. Description of the invention (ο) Then, please refer to the 2D drawing on the substrate 200 A photoresist layer 234 is formed to cover the P-type metal-oxide semiconductor 266 and the electrostatic discharge protection transistor, and expose the N-type metal-oxide semiconductor 262 in the complementary metal-oxide semiconductor region 260. After that, a N-type pre-amorphized ion implantation 236 process is performed to make the surfaces of the gate 208 and the source / drain regions 224 of the N-type metal-oxide semiconductor transistor 262 amorphous. The N-type pre-amorphized ion implantation 236 process is, for example, implanting N-type phosphorus or arsenic on the surfaces of the gate 208 and the source / drain regions 224. After that, referring to FIG. 2E, the photoresist layer 234 is removed, and then another photoresist layer 238 is formed on the substrate 200 to cover the N-type metal-oxide semiconductor transistor 262 and the electrostatic discharge protection transistor 264, exposing the complementary type. A P-type metal-oxide semiconductor 266 in the metal-oxide semiconductor region 260. Thereafter, a P-type pre-amorphization lattice implantation 240 process is performed to make the surfaces of the gate 210 and the source / drain regions 232 of the N-type metal-oxide semiconductor transistor 266 amorphous. The P-type pre-amorphized ion implantation 240 process is, for example, implanting P-type boron on the surfaces of the gate 210 and the source / drain regions 232. It is worth mentioning that the P-type pre-amorphized lattice implantation 240 process and the N-type pre-amorphous ion implantation 240 process of the present invention can control the implanted ions at different doses to Meet the needs of N-type metal oxide semiconductor and P-type metal oxide semiconductor in the process of automatic alignment metal silicidation process. Next, referring to FIG. 2F, the photoresist layer 238 is removed. After that, an insulating layer 242 is formed on the substrate 200. The insulating layer 242 is, for example, silicon oxide formed by using tetraethylsiloxane (TEOS) as a gas source and plasma gain chemical vapor deposition (PECVD). Thereafter, a 9-paper size was formed on the substrate 200, which was in compliance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- · installation -------- Order --------- ^ 9— (Please read the precautions on the back before filling this page) 558754 ^ 320twf.doc / 006 fij --- B7 V. Description of the invention (") Patterned light The resist layer 244 covers the area where the ESD protection element region 270 is not to be formed with a silicide metal layer, for example, the gate electrode 212 and the drain region 226 a covering the ESD protection element region 270. Then, referring to FIG. 2G, using the photoresist layer 244 as an etching mask, the insulating layer 242 not covered by the photoresist layer 244 is etched and removed, and the remaining insulating layer 242a is used as a metal silicide blocking layer. After that, a metal layer 246 is covered on the substrate 200. The material of the metal layer 246 is, for example, titanium, tungsten, cobalt, nickel, uranium, or palladium, and a method for forming the metal layer 246 is, for example, a sputtering method. Finally, referring to FIG. 2H, a thermal process is performed to enable the metal layer 246 to contact the polycrystalline silicon of the gates 208 and 210 and the surface of the substrate 200 (the source / drain regions 224, 226, and 232). ) Reaction to form silicided metal layers 250, 254, 248, 256, and 252. After that, the portion of the metal layer 246 that has not participated in the reaction and the insulating layer 242a are removed. In the above embodiments, the drain region of the ESD protection element is taken as an example where the silicide metal layer is not to be formed. However, the region where the silicide metal layer is not intended to be formed is not limited to this. The region where the silicided metal layer is not to be formed may include the source and drain regions of the memory cell region, such as the source and drain regions of the dynamic random access memory.
本發明係在進行自動對準金屬矽化製程之前，先在互 補式金氧半電晶體之NMOS與PMOS分別植入N型與P型離 子，以使NMOS與PMOS非晶格化。由於所植入之離子的型 態均與NMOS以及PMOS之閘極與源極/汲極區之離子型態 相同，而且其劑量可以視實際的需要而分別調整，因此， 本發明可以在進行自動對準金屬矽化物製程時符合NMOS 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------·裝—— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Before the automatic alignment metal silicidation process is performed, the present invention first implants N-type and P-type ions into the NMOS and PMOS of the complementary metal-oxide-semiconductor to make the NMOS and PMOS amorphous. Because the implanted ions are of the same type as those of the gate and source / drain regions of NMOS and PMOS, and their doses can be adjusted separately according to actual needs, the present invention can The metal silicide process is in line with NMOS. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- · Installation—— (Please read the note on the back first Please fill in this page for further information) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
558754 5320twf.doc/006 pj B7 五、發明說明（1) 與PMOS之不同需求。 而且，本發明在預定不形成的區域之中，並未進行非 晶格化之離子植入步驟，因此，可以避免其閘極或源極/ 汲極區因爲植入非晶格化之離子而造成阻値上升的問題。 此外，由於非晶格化之離子植入步驟，係在圖案化金 屬矽化阻擋層之蝕刻製程之前施行，因此可以避免習知因 爲蝕刻破壞基底所造成的漏電流問題並且可以避免習知通 道效應等問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）558754 5320twf.doc / 006 pj B7 V. Description of the invention (1) Different requirements from PMOS. In addition, the present invention does not perform an amorphous lattice implantation step in a region that is not expected to be formed. Therefore, the gate or source / drain region can be avoided due to implantation of amorphous lattice ions. Caused the problem of obstruction. In addition, since the amorphous latticed ion implantation step is performed before the etching process of the patterned metal silicide barrier layer, the leakage current problem caused by etching damage to the substrate can be avoided and the channel effect can be avoided. problem. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ----------- Equipment -------- Order --------- (Please read the precautions on the back before filling out this page) Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs The paper size printed by the cooperative applies the Chinese National Standard (CNS) A4 (210 X 297 mm)