TW469589B - Silicide manufacture process - Google Patents

Abstract

A semiconductor substrate with an N well area, a P well area and an isolation area is given. Polysilicon gate and its source and drain are formed on individual N well area and P well area. An ion barrier layer is formed to cover the source/drain area and expose the gate surface structure. Subsequently, a pre-amorphization process is carried out to create an amorphous region on the gate surface. In the other embodiment, the material of gate spacer is used to function as the ion barrier layer forming an amorphous region on the gate surface. After the removal of the ion barrier layer, a self-aligned metal silicide process is performed and thus metal silicide is formed on the polysilicon gates of the individual N well area and P well area and also on the source/drain area.

Description

469589 V. Description of the invention (l) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a metal silicide of a P-type metal oxide semiconductor device. 5-2 Background of the Invention: With the increasing accumulation of semiconductor devices, such as Metal-Oxide-Semiconductor (MOS) devices, in order to keep the area of the chip (ch ip) the same, or even shrink, to continue The only way to reduce the unit cost of a circuit is to continually reduce the design rule of the circuit in order to comply with the future development trend of the high-tech industry. Therefore, the space area occupied by components also follows the circuit design specification (des ru 1 e) while gradually shrinking. With the development of semiconductor technology, the size of components of integrated circuits has been reduced to the range of deep sub-microns. When the semiconductor is continuously reduced to the range of deep sub-microns, some problems in process scaling have occurred, such as the first A to As shown in FIG. 1C, a cross-sectional view showing a conventional P-tyPe Metal Oxide Semiconductor (PM0S) device structure is provided. First, a semiconductor substrate 100 having an N-well region is provided. A gate electrode 110 is formed on the surface. On the semiconductor substrate

469589 V. Description of the invention (2) A P-type ion implantation is performed in 100 to facilitate the formation of a lightly doped drain (

Lightly Doped Drain; LDD) 120. Next, a gap wall 130 ′ is formed on the side wall of the gate electrode 110, and then a heavily doped (P +) type ion implantation is performed in the semiconductor substrate 1000 to facilitate the formation of the source electrode. Sources / Drain regions 140, wherein the P-type ion and the P + -type ion system are a group 1 ion, such as boron ion (boron; B). Then proceed—Self-aligned silicide process ι50 (Self-Aligned Silicide), in order to form on the surface of the semiconductor substrate 100 and the surface of the gate electrode 110—the metal silicide layer A Annealing thermal process. f In the deep sub-micron component manufacturing process, the source / drain region and the gate electrode are treated as an important and widely used process technology. This can be achieved by a self-aligned silicide process (Sel Bu Siignicide), where the self-aligned silicide process still requires a tempering step (Annea Γηε) ^ ^ material structure. & In the conventional manufacturing method of the p-type metal oxide semiconductor (PM0S) device described above, the metal silicide layer 16 is often caused by

The tempered thermal process causes the metal fragmentation layer i 6 0 to form a spherical shape. As shown in the first figure C, this phenomenon not only causes the poor structure of the metal silicide layer 16 〇 but also results in the s V-induced metal silicide layer. Sheet resistance, especially the decline of the metal silicide layer 16 on the gate 110, makes the gate 110 more prone to failure. In view of the defects of the above process, another P-type metal oxygen is traditionally proposed

469589 V. Description of the invention (3) Metal silicide process of semiconductor device 'as shown in Figures 2A to 2C' shows a conventional amorphous siliconization process of P-type metal oxide semiconductor devices Section view. First, a semiconductor substrate 200 with an N-well region is provided to form a gate 210 on its surface. A P-type ion implantation 'is performed in the semiconductor substrate 200 to form a lightly doped drain (LDD) 220. Next, a gap wall 230 is formed on the side wall of the gate electrode 21, and then a heavy doping (P +) type ion implantation is performed in the semiconductor substrate 2000 in order to form a source. Sources / Dra in regions 240, wherein the P-type ion and the P + -type ion system are a group 111 ion, such as boron (Bron); An arsenic pre-amorph i za ti on process (pre-amorph i za ti on process) 2 5 0 is then used to form an amorphous region (amorphous r eg i οns) 2 6 0 at the source / non-polar region 24 0 and gate 2 1 0 ° Finally, a self-aligned silicide process 270 (Self-Aligned Silicide) is performed, so as to form a metal on the surface of the semiconductor substrate 20 0 and the surface of the gate 210 Silicone layer 280. Finally, an annealing process is performed. Advances in integrated circuits have involved the downsizing of component geometries. In deep sub-micron metal oxide semiconductor technology, the gate size is bound to shrink with the progress of the process. As the channel length becomes shorter, the sheet resistance of the metal silicide also increases. In order to avoid the effects caused by the short channel effect in the process below 0.1 8 microns1, it is necessary to first perform a pre-amorphization process in the traditional process to

469589 V. Description of the invention (4) Make the metal silicide grow more perfect. Although the pre-amorphous implantation process will produce an amorphous layer (a m ο r p h 〇 u s 1 a y er) in the crystalline substrate. However, this design method also has defects, that is, there are still voids at the interface between the amorphous layer / crystalline substrate in the substrate, which makes the subsequent growth of the metal silicide poor. The above-mentioned P-metal oxide semiconductor pre-amorphous implantation process is usually performed with arsenic ions, so if too many arsenic ions are implanted, it will offset the boron in the source / drain region. Ions (boron) cause damage to the source / drain region of the P-type metal oxide semiconductor. In view of this, in the traditional integration process, a photomask process is still needed to avoid reducing the quality of the P-type metal oxide semiconductor device, which greatly increases the process cost. In view of the above reasons, we need a new method of manufacturing semiconductor devices in order to form metal silicides of P-type metal oxide semiconductor devices. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the conventional method for manufacturing metal silicides of P-type metal oxide semiconductors has many disadvantages. The present invention provides a method to overcome the problems in the traditional process.

469589 V. Description of the invention (5) The purpose of the present invention is to provide a metal silicide process for P-type metal oxide semiconductor devices, in order to manufacture semiconductor devices with smaller size and high reproducibility. This method is not only applicable to deep sub-micron technology, but also does not increase the resistance value of the junction surface of the P-type metal oxide semiconductor device. Another object of the present invention is to provide a method for forming a metal silicide. The present invention not only makes the growth of the metal silicide better, but also is compatible with the conventional P-type metal oxide semiconductor manufacturing process. In addition, the method of the present invention does not require a lithography process to form a photomask, which can save the process cost to meet economic benefits. A further object of the present invention is to provide a method for forming a metal silicide. The present invention replaces the lithography process by the formation of an ion barrier layer, and can further avoid the pre-amorphous silicidation process of arsenic against P by this method. The surface of the source / drain of a metal-oxide-type metal oxide semiconductor causes damage, so that only the gate is previously amorphous siliconized. According to the above-mentioned object, the present invention discloses a new method for manufacturing a semiconductor device. In this embodiment, a semiconductor substrate having an N-well region, a P-well region, and an isolation region is provided, and a polycrystalline silicon gate and its source / drain are formed on the N-well region and the P-well region, respectively. Polar region. Then, an ion barrier layer is formed so as to cover the source / drain regions' and expose the gate surface structure. Next, a pre-amorphization process is performed on the gate to form an amorphous region on the gate surface. After removing the ion barrier layer,

469589 V. Description of the invention (6) A self-aligned metal silicide process is performed, and metal silicide is formed on the polycrystalline silicon gate and its source / drain regions in the N-well region and the P 丼 region, respectively. Finally, a tempered thermal process is performed. In another embodiment, a semiconductor substrate having an N-well region, a P-well region, and an isolation region is provided. A polycrystalline silicon gate and a lightly doped drain region are then formed on the N-well region and the P-well region of the semiconductor substrate, respectively. Next, an ion barrier layer is formed on the aforementioned structure and etched back to expose the surface structure of the polycrystalline silicon gate. Then, a pre-amorphization process is performed on the polycrystalline silicon gate to form an amorphous region on the polycrystalline silicon gate. An anisotropic etch is used to etch the ion barrier layer to form the spacer structure of the polycrystalline silicon gate. Subsequently, a heavily doped ion implantation is performed to form the source / drain regions. Then, a self-aligned metal silicide process is performed, and metal silicides are formed on the polycrystalline silicon gates in the N-well region and the P-well region and their source / drain regions, respectively. Finally, an annealing process is performed. 5-4 Detailed Description of the Invention: The present invention is directed to a method for manufacturing a metal silicide of a P-type metal oxide semiconductor device. In order to understand the present invention thoroughly, detailed steps will be proposed in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the art of semiconductor devices. On the other hand, well-known process steps are not described in detail to avoid

469589 V. Description of the invention (7) Exempt unnecessary restrictions on the present invention. The preferred embodiments of the present invention will be described in detail as follows. However, in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited. The following patent scope shall prevail . Referring to FIG. 3A, in an embodiment of the present invention, 'a semiconductor substrate 3 0 0 having an N-well region 310, a P-well region 32 0, and an isolation region 33 0 is first provided. Polycrystalline silicon gate 340, and then performing a P-type lightly doped drain (LDD) ion implantation on the above structure, so as to form a lightly doped drain in the semiconductor substrate 300 Area (LDD) 3 5 0. The above-mentioned P-type ion system is a group I ion, such as boron ion (Boronions; B). Secondly, a gap wall 360 is formed on the side wall of the polycrystalline silicon gate 34, and then a heavily doped (P +) type ion implantation in the semiconductor substrate 300 is performed. A tempering process of an ion implantation is performed, so that the heavily doped implanted region is extended to form a source / dead region (S / D) 3 7 0. Wherein p: is an in group ion, for example, boron ion (b0rronion); above, source = :: 5: two-layer, = the aforementioned structure 380 is etched back to reveal the polycrystal The surface society of Shi Xijian pole 34o: 'Ion barrier layer 38. The material can be the same as the material of a photoresist layer. The concentration is concentrated on the Xi crystal: the gate 34 0 is a pre-arsenic system of arsenic. An amorphous region 390 is on the surface of the polycrystalline silicon gate 340. Then 385 is formed

589 V. Description of the invention (8) Referring to the third figure C, after forming the amorphous region 3 9 0, the ion barrier layer 3 8 0 can be removed and a self-aligned metal silicide process 3 9 1 can be performed. Metal silicide layers 3 95 are formed on the polysilicon gates 3 4 0 and their source / drain regions 3 7 0 in the N-well region and the P-well region, respectively. Finally, a tempered thermal process is performed. Referring to FIG. 4A, in another embodiment of the present invention, a semiconductor substrate 4 0 with an N-well region 4 1 0, a P-well region 4 2 0, and an isolation region 4 3 0 is first provided. . Then, a polycrystalline silicon layer is formed on the semiconductor substrate 400. A photoresist layer is defined on the polycrystalline layer in the N well region 4 10 and the P well region 4 2 0, and the polycrystalline layer is etched by using the photoresist layer as a mask to etch the polycrystalline layer. A polycrystalline silicon gate 4 40 is formed on the N well region 4 1 0 and the P well region 4 2 0 respectively. Then, a lightly doped drain (LDD) ion implantation of P-type ions is performed on the above structure, so as to form a lightly doped drain region (LDD) in the semiconductor substrate 400. 4 5 0. Among them, the p-type ion system is a group II A ion, such as a butterfly ion (boron i ons; B). Referring to the fourth diagram B, an ion barrier layer 460 A is deposited on the aforementioned structure to protect the lightly doped drain region 450. The ion barrier layer 460 A is etched back to reveal the surface structure of the polycrystalline silicon gate 440. Among them, the material of the ion barrier layer 460 A may be made of a general spacer. After that, a polycrystalline silicon gate 4 4 0 is subjected to a pre-amorphous process of arsenic 4 7 0 to form a

Page 11 V. Description of the invention (9) The amorphous region 480 is on the polycrystalline silicon region 440. Subsequently, an anisotropic etch can be used to contact the ion barrier layer 460A to form a spacer 460B structure of the polycrystalline silicon gate 440. Second, a heavy doping (P +) type ion implantation is performed in the semiconductor substrate 400, and an ion implantation tempering process is performed, so that the heavily doped implanted region is extended to form a source electrode. / Drain region (S / D) 48 5. The P + -type ion system is an I I I group ion, such as boron ions (B), as shown in Figure 4C. Referring to the fourth D diagram, a self-aligned metal silicide process 490 is performed, and is formed on the polycrystalline silicon gate 440 and its source / drain region 485 in the N-well region and the P-well region, respectively. Metal stone oxide layer 4 9 5. Finally, a tempered thermal process is performed. In an embodiment of the present invention, a process for manufacturing a metal silicide of a P-type metal oxide semiconductor device is provided, so as to manufacture a semiconductor device with a smaller size and high reproducibility. This method is not only suitable for deep sub-micron technology *, but also does not increase the resistance of the junction surface of P-type metal oxide semiconductor devices. In addition, the present invention can also make the growth of metal silicide better, and is compatible with the traditional P-type metal oxide semiconductor manufacturing process. At the same time, the method of the present invention does not require a lithography process to form a photomask, so the process cost can be saved to comply with economic benefits. The invention can use the formation of an ion barrier layer instead of the lithography process, and can also use this method to avoid the pre-amorphous silicidation process of arsenic from causing damage to the source / drain surface of the P-type metal oxide semiconductor, thereby achieving The purpose is to pre-amorphize the gate.

Page 12 469589 V. Description of the Invention (o) Obviously, according to the description in the above embodiment, the present invention may have many modifications and differences. Therefore, it needs to be understood within the scope of the appended claims. In addition to the above detailed description, the present invention can be widely implemented in other embodiments. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following application patents Within range.

Page 13 469589 Figures briefly explain Figures A to C are cross-sectional structural diagrams of the conventional metal silicide process for P-type metal oxide semiconductor devices; Figures A to C A schematic cross-sectional structure diagram of a metal silicide process including a pre-amorphous silicidation process of a P-type metal oxide semiconductor device, and FIGS. 3A to 3C are P-type metal oxide semiconductor devices illustrating a preferred embodiment of the present invention. A cross-sectional structure diagram of a metal silicide process; and FIGS. 4A to 4D are schematic cross-sectional structure diagrams illustrating a metal silicide process of a P-type metal oxide semiconductor device in another preferred embodiment of the present invention. The main part of the symbol: 100 semiconductor substrate. 110 gate. 12 0 Lightly doped drain region. 130 bulkhead. 14 0 Source / dead area. 15 0 Align the gold eyebrow breaking process by itself. 16 0 metal lithoate layer. 2 0 0 Semiconductor substrate.

Page 14 469589 Schematic illustration of 210 closed pole. 220 lightly doped; and polar region 〇 230 bulkhead. 240 source / dead area. 250 Pre-amorphous process. 260 Amorphous region. 270 Self-aligned metal silicide process. 280 metal silicide layer 〇 300 semiconductor substrate. 310 N well area. 320 P well area. 330 ρ (? Ι ionization zone. 340 gate. 350 lightly doped non-electrode region 0360 spacer. 370 source /; and electrode region c 1 380 ion barrier layer. 385 pre-amorphization process. 390 non Crystallization area. 391 Self-aligned metal silicide process. 395 Metal silicide layer. 0 400 semiconductor substrate. 410 N well area. 420 P well area.

Page 15 469589 Simple illustration of the drawing 430 440 450 4 60A 4 6 0 B 470 480 485 490 495 Isolated area. Gate. Lightly doped drain region. Ion barrier layer. Gap wall. Pre-amorphization process ° Amorphization region. Source / drain region. Self-aligned metal silicide process.

Page 16

Claims (1)

6. Scope of Patent Application 1. A method for forming a metal silicide layer of a semiconductor device, the method includes at least the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a gate electrode, a nudge region And a source A and a pole region, forming and covering an ion barrier layer on the semiconductor substrate and the gate electrode to protect the source / drain region; etch back the ion barrier layer to expose Out of the surface of the gate; forming an amorphous region on the surface of the gate; removing the ion barrier layer; and separately forming a metal silicide layer on the amorphous region and the gate of the gate On the source / drain region of the semiconductor substrate. 2. The forming method according to item 1 of the scope of patent application, wherein the above-mentioned semiconductor substrate has a first conductivity. 3. The method as described in item 1 of the scope of patent application, wherein the lightly doped drain region includes at least a second conductive dopant. 4. The forming method as described in item 1 of the scope of the patent application, wherein the source / drain region includes at least a second conductive dopant. 5. The formation method as described in item 1 of the scope of patent application, wherein the formation of the above-mentioned ion barrier layer is formed by a deposition method. Page 17 4 6 9 5 8 9 6. Scope of patent application 6. The method of forming as described in item 1 of the scope of patent application, wherein the material of the above ion barrier layer includes at least one photoresist material. 7. The forming method as described in item 1 of the scope of patent application, wherein the forming of the above-mentioned amorphous region includes at least a pre-amorphous process. 8. The forming method as described in item 7 of the scope of patent application, wherein the above-mentioned pre-amorphization process includes at least one dopant having a first conductivity. 9. The forming method as described in item 1 of the scope of the patent application, wherein the formation of the above-mentioned metal silicide layer includes at least a self-aligned metal silicide process. 10. A method for forming a metal silicide layer of a semiconductor device. The method includes at least the following steps: providing a semiconductor substrate; forming a polycrystalline silicon layer on the semiconductor substrate; defining a photoresist layer on the polycrystalline silicon layer Using the photoresist layer as an etching mask and etching the polycrystalline silicon layer to form a gate; removing the photoresist layer; forming a lightly doped drain region in the semiconductor substrate; forming and covering a An ion barrier layer on the semiconductor substrate and the gate to protect the lightly doped drain region; etch back the ion barrier layer to expose the surface of the gate; Page 18 6. The scope of the patent application forms an amorphous region on the surface of the gate; the ion barrier layer is etched to form two gaps on the two side walls of the gate respectively; forming a source / The drain region is in the semiconductor substrate; and a metal silicide layer is formed on the amorphous region of the gate and the source Λ and the electrode region, respectively. 11. The forming method according to item 10 of the scope of patent application, wherein the above-mentioned semiconductor substrate has a first conductivity. 12. The forming method as described in item 10 of the scope of patent application, wherein the lightly doped drain region includes at least a second conductive dopant. 1 3. The formation method as described in item 10 of the scope of patent application, wherein the formation of the above-mentioned ion barrier layer is formed by a deposition method. 14. The forming method as described in item 10 of the scope of the patent application, wherein the material of the ion barrier layer is the material of the partition wall. 15 · The formation method as described in item 10 of the scope of patent application, wherein the formation of the above-mentioned amorphization region includes at least a pre-amorphization process. 16. The forming method as described in item 15 of the scope of the patent application, wherein the aforementioned pre-amorphization process includes at least one dopant having a first conductivity. Page 19 469589 VI. Application for patent scope 1 7. The formation method described in item 10 of the scope of patent application, wherein the formation of the above-mentioned partition wall is an anisotropic etching process " 1 8. The forming method according to item 10 of the scope, wherein the source / drain region includes at least a second conductive dopant. 19. The forming method as described in item 10 of the scope of the patent application, wherein the forming of the metal silicide layer includes at least a self-aligned metal silicide process. 2 0. A method for forming a metal silicide layer of a semiconductor device, the method includes at least the following steps: providing a semiconductor substrate having an isolation region, a first conductive well region and a second conductive well region; Material, wherein the first conductive well region includes at least a first lightly doped electrode region, a first source electrode / 7; and a pole region and a first gate and the second conductive well region at least Containing a second lightly doped drain region, a second source electrode region and a second gate electrode; protecting the second gate electrode from forming and covering an ion barrier layer on the first electrode The conductive well region and the first gate electrode and the second conductive well region and the second gate electrode are divided into a source / drain region and the second source / > and a pole region; Forming a first amorphous system region on the first gate and a second non-ionic barrier layer to etch back to expose the first gate and the surface; Page 20 6. The scope of patent application is that the crystallized region is on the surface of the second gate; the ion barrier layer is removed; and a metal silicide layer is formed on the first source / drain region and The first amorphous region of the first gate, the second source / drain region, and the second amorphous region of the second gate. 2 1. The forming method as described in item 20 of the scope of patent application, wherein the first lightly doped drain region includes at least a second conductive dopant. 2 2 · The forming method as described in item 20 of the scope of the patent application, wherein the second lightly doped drain region includes at least a first conductive dopant. 2 3. The forming method as described in item 20 of the scope of patent application, wherein the first source / drain region includes at least a second conductive dopant. 24. The forming method as described in item 20 of the scope of the patent application, wherein the second source / drain region includes at least a first conductive dopant. 25. The method as described in item 20 of the scope of patent application, wherein the formation of the above-mentioned ion barrier layer is formed by a deposition method. 2 6. The forming method as described in item 20 of the scope of patent application, wherein the material of the above-mentioned ion barrier layer includes at least one photoresist material. Page 21 d 69 5B9 Page 22 469589 VI. Patent application scope The first photoresist layer and the second photoresist layer are used as a money engraving mask and the polycrystalline dream layer is etched to form a first gate electrode on the first A conductive well region and a second gate electrode on the second conductive well region; removing the first photoresist layer and the second photoresist layer; forming a first lightly doped drain region respectively Forming and covering an ion barrier layer in the first conductive well region and the second conductive well region in the first conductive well region and a second lightly doped drain region in the second conductive well region; and A first gate electrode and the second conductive well region and the second gate electrode to protect the first lightly doped drain region and the second lightly doped drain region; Etch back to expose the surface of the first gate and the second gate; forming a first amorphous system region on the first gate and a second amorphous system region on the second gate, respectively; On the surface; the ion barrier layer is etched to be formed on the sidewall of the first gate electrode respectively-a first gap wall and a sidewall of the second gate electrode are formed to form a first Two spacers; forming a first source / drain region in the semiconductor substrate, the first conductive well region and a second source / drain region in the semiconductor substrate, the second conductivity And a metal silicide layer is formed on the first gate and its first source / drain region and the second gate and its second source / drain region, respectively. 33. The method according to item 32 in the scope of the patent application, wherein the first lightly doped drain region includes at least a second conductive dopant. Page 23 4 6 9 5 8 9 6. Application for patent scope 34. The formation method as described in item 32 of the scope of patent application, wherein the second lightly doped drain region includes at least one dopant of first conductivity . 3 5. The method as described in item 32 of the scope of patent application, wherein the above-mentioned ion barrier layer is formed by a deposition process. 3 6. The forming method as described in item 32 of the scope of the patent application, wherein the material of the above-mentioned ion barrier layer is the material of the partition wall. 37. The forming method as described in item 32 of the scope of the patent application, wherein the forming of the first amorphization region includes at least a pre-amorphization process. 38. The forming method according to item 32 of the scope of the patent application, wherein the forming of the second amorphization region includes at least a pre-amorphization process. 39. The forming method as described in item 37 of the scope of patent application, wherein the above-mentioned pre-amorphization process includes at least one ion having a first conductivity. 40. The forming method according to item 38 of the scope of the patent application, wherein the above-mentioned pre-amorphization process includes at least one ion having a first conductivity. 41. The forming method as described in item 32 of the scope of the patent application, wherein the formation of the above-mentioned partition wall is an anisotropic etching process. Page 24 469589 6. Scope of patent application 4 2. The forming method as described in item 32 of the scope of patent application, wherein the above-mentioned first source / drain region includes at least one dopant of second conductivity. 43. The forming method as described in item 32 of the scope of patent application, wherein the second source / drain region includes at least one dopant having a first conductivity. 4 4. The forming method as described in item 32 of the scope of patent application, wherein the forming of the above-mentioned metal silicide layer includes at least a self-aligned metal silicide process. 4 5. A method for forming a metal silicide layer of a semiconductor device, the method includes at least the following steps: providing a semiconductor substrate having an isolation region, an N-type well region, and a P-type well region, wherein the N-type The well region includes at least a lightly doped drain region of a P-type ion, a source / drain region of the P-type ion, and a first gate and the lightly doped drain of the P-type well region includes at least an N-type ion. A polar region, an N-type ion source / pole region, and a second gate electrode; depositing an ion barrier layer and forming the ion barrier layer and the first gate electrode and the P-type well region and On the second gate electrode to protect the source / drain region of the P-type ion and the source / drain region of the N-type ion; etch back the ion barrier layer to expose the first gate electrode And a surface of the second gate; performing a pre-amorphization process of N-type ions to form a first amorphized region on the first gate and a second amorphized region on the First Page 25 463589 6. The scope of the patent application on the surface of the second gate; removing the ion barrier layer; and performing a self-aligned metal silicide process to form a metal silicide layer respectively at the source of the P-type ions Electrode / drain region and the first amorphous region of the first gate and the source / drain region of the N-type ion and the second amorphous region of the second gate . 46. The forming method as described in item 45 of the scope of patent application, wherein the P-type ion includes at least one boron ion. 4 7. The forming method as described in item 45 of the scope of patent application, wherein the N-type ions include at least one divine ion. 4 8. A method for forming a metal silicide layer of a semiconductor device, the method includes at least the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has an isolation region, an N-type well region, and a P-type well; Forming a polycrystalline layer on the semiconductor substrate, and respectively defining a first photoresist layer on the N-type well region of the semiconductor substrate and a second photoresist layer on the polycrystalline silicon of the F-type well region Layer; using the first photoresist layer and the second photoresist layer as an etch mask and #etching the polycrystalline layer to form a first gate electrode in the N-type well area and a first Two gate electrodes on the P-well area; removing the first photoresist layer and the second photoresist layer; Page 26 469589 The scope of the six-patent application forms a lightly doped drain region of a P-type ion in the N-type well region and a lightly doped drain region of an N-type ion in the P-type well region; An ion barrier layer is formed on the N-type well region and the first gate electrode and the P-type well region and the second gate electrode to protect the lightly doped drain region of the P-type ion and the N Lightly doped drain region of the type ion; etch back the ion barrier layer to expose the surface of the first gate and the second gate; and perform a pre-amorphization process of an N-type ion, respectively Forming a first amorphous region on the surface of the first gate and a second amorphous region on the surface of the second gate; performing an anisotropic etching to etch the ion barrier layer and A first gap wall is formed on the side wall of the first gate electrode and a second gap wall is formed on the side wall of the second gate electrode respectively; a source / drain region of a P-type ion is formed in the N-type well region And a source / drain region of an N-type ion in the P-well region; and a self-aligning metal lithotripsy process to form a Metal silicide layer on the first gate and the source of the P-type ion source / drain region and the second gate electrode and the source of the second N-type ions / drain regions. 49. The forming method as described in claim 48, wherein the P-type ions include at least one boron ion. 50. The forming method as described in item 48 of the scope of patent application, wherein the N-type ions include at least one arsenic ion. Page 27